HK1165626B - Low dissipation amplifier - Google Patents

Description

Low power consumption amplifier

Information of related applications

The present application claims the benefit of U.S. provisional application serial No. 61/155,385 (attorney docket No. 157835-0041), filed on 25/2/2009, which is incorporated herein by reference as if fully set forth.

Technical Field

The field of the invention relates generally to amplifiers and more particularly to an improved method of minimizing distortion and power consumption in compact amplifiers.

Background

Amplifiers used in a variety of applications include audio signal processing, video processing, communications, control systems, satellites, and the like. The amplifier may be classified as class a, class B, class AB, class D, class G, or class H based on its power consumption characteristics. General background content for different amplifier levels can be found, for example, in "Analysis, design and Association of ClassA, B, AB, GandHAudio Power Amplifier OutputStages Basedon MATLAB" in May 12-15 pages R. Bortoni et al, at 110 th conference of Audio engineering Association (AES) 2005Software "and journal of the Audio engineering Association in 2006Found on page 319 and 323 of phase 4, volume 54.

Class a amplifiers are known to require relatively large non-operational power and are inefficient, and therefore are unreliable in many applications requiring low power consumption. Class B amplifiers can have very low non-operational power consumption but introduce distortion. The class AB amplifier is in between and uses a bias current to reduce distortion inherent in the class B amplifier. Class AB amplifiers have higher power consumption than class B amplifiers due to bias current.

As devices become smaller, amplifiers are becoming more of a limitation in the ability to reduce package size. The inevitable limited efficiency of the amplifier leads to power dissipation that must be dissipated by a heat sink in order to prevent the amplifier from overheating; however, a larger heat sink can occupy an excessive amount of the packaging space. Techniques exist to improve the efficiency of standard class AB amplifier designs and thus reduce the need for a heat sink, but these approaches often result in compromises in the bandwidth, noise or distortion performance of the amplifier.

There are at least two aspects to the power consumption of the amplifier system. The first is what is commonly referred to as no load power consumption or no run power consumption-that is, power consumption when the amplifier is not delivering power to the load. With conventional linear amplifiers, this inoperative power consumption, including the bias current applied to the amplifier, is primarily concentrated on the driver and output stages of the amplifier and is generally required in conventional amplifier designs to minimize crossover distortion. In a high performance audio power amplifier providing a nominal 100 watt sine wave power capability of 4 to an 8 omega load, for example, the idle current may be approximately 100-. With a quiescent power supply voltage of typically +/-45 volts, this no-load current results in no-load power dissipation of approximately 9-18 watts per channel. This is a serious problem for stereo amplifiers, which is also a greater problem for multi-channel amplifiers, since the idle power consumption is rapidly excessive due to the increase in the number of amplifiers.

For home type audio amplifiers, a larger heat sink can generally be used to dissipate energy and keep the power device at a lower temperature, but for size-limited applications, such as automotive entertainment systems, the size and weight of the heat sink cannot be tolerated.

The no-load current of the amplification system must be set substantially at production time to optimize distortion performance and thus increase production costs. The idle current requirement also varies with temperature and lifetime. Thus, over time or after extended use, the quality of the amplifier output may deteriorate.

In addition to the power consumption problem of idle power, the amplifier generates additional power consumption when it delivers a signal to the load, sometimes referred to as dynamic power consumption. In practice, a linear power amplifier of nominal 100 watt capacity can dissipate well the worst case of 40 watts when delivering a sine wave signal to the load. Using music as the audio source for the amplifier, this data is lower because music has a higher crest factor than a sine wave, but still approaches 30 watts per channel.

Various techniques have been used to reduce the idle power consumption and the dynamic power consumption of linear amplifiers. A technique that may be used to reduce idle power consumption is to reduce the output stage bias current. However, this will result in an increase in crossover distortion, which is difficult to cancel by conventional negative feedback around the amplifier. Furthermore, this technique has little effect on dynamic power consumption.

Another approach to reduce both idle and dynamic power consumption is to use a 'stage G' amplifier configuration. This 'G' level term is commonly used in Hitachi (see "HighestEffeiciencyandSuperQualityAudioAmplifier Using SporoverFeTsIn ClassGOperation", IEEEtan section on Consumer electronics, volume 8 1978, CE-24, No. 3), although the basic technology has been previously described (see, for example, U.S. Pat. No. 3,622,899). The 'class G' amplifier device also reduces dynamic power consumption by ensuring that the voltage across the power device is also reduced when driving signals to the load, maintaining a low voltage across the output device under no load conditions. Thus, both idle power consumption and dynamic power consumption are reduced. However, switching of the output device between the power rails typically results in a small failure of the output waveform, which is considered distortion. These small faults have very high frequency energy and are therefore difficult to correct by negative feedback. Careful design can reduce this effect but does not eliminate it completely and tends to raise the power consumption of the high frequency dynamics.

An alternative approach to reduce the power consumption of the amplifier is to implement a switching amplifier and in particular a so-called 'D-stage' architecture. With this design, the linear amplifier is replaced by a power switch, which operates at typically several hundred kilohertz for high performance audio amplifiers. The nominal efficiency of such a design carrying an impedance load is theoretically very high, but in practice switching losses and output filter losses significantly reduce the actual efficiency. High switching frequencies can cause significant EMI problems, which then require bulky inductors to prevent connection to the power supply and output lines, and careful screening to avoid radiation. These increases mean that while the basic amplifier components can be small and low cost, the overall size is significantly increased and the cost is increased due to the need for sensing and filter components. Furthermore, continuous switching results in large idle currents, since dynamic switching losses and Pulse Width Modulation (PWM) processes for generating the switching signal result in poor distortion performance compared to linear amplifiers.

An example of a class D amplifier is the model TDF8590TH amplifier from NXP semiconductors, which is headquartered in switzerland. When the amplifier is configured to provide a nominal 100 watt sine wave to an 8 Ω load, no-load power consumption exceeds 4 watts per channel. Total harmonic distortion is above 0.1% at all levels above 10 watt output at 10kHz and rises sharply at higher output levels-and even these data are an underestimate of temporal distortion due to the use of AES17 filters to remove the effect of the residual switch comment component on the measurement device. Intermodulation distortion (IMD) performance is worse than a well-designed linear amplifier. The output inductors are typically also large so that they are not saturated or introduce other distortion, and typically measure 4 to 5 cubic centimeters, which is an impediment to miniaturization of the overall circuit and package.

Thus, there remains a need for an amplifier topology that can be stably minimized while providing ground power consumption. There is also a need for an amplifier that can provide ground idle and dynamic power consumption levels, does not require bias settings, and does not have inductors for EMI or filtering. There is also a need for amplifiers that deliver very low distortion levels.

Disclosure of Invention

In accordance with one or more embodiments, there are provided power amplifier systems and methods including one or more of the following features: topology to reduce distortion; an AB driver stage; a current protection mechanism; distortion reduction, particularly when configured as class G or class H amplifiers; and nested distortion reduction structures.

In accordance with one aspect of one or more embodiments, a low power, low distortion amplifier includes a first amplifier configured as or including a driver stage and a second amplifier configured as or including a column output stage, and with a plurality of impedance networks providing inputs to the first amplifier from outputs of the first and second amplifiers, a first connection path from an output of the second amplifier to a load, and a second connection path from an output of the first amplifier to a load. The impedance network may be a resistor, a capacitor, or a combination of networks for them. An additional feedback path may be provided at the input from the load to the first amplifier. One or more intermediate amplifier stages may also be disposed between the first amplifier and the second amplifier.

In accordance with another aspect of one or more embodiments, a method for amplifying an input source signal includes the steps of: receiving an input source signal at a first amplifier and generating therefrom a driver signal; providing a driver signal to an input of the second amplifier as a primary output stage; operating the first amplifier in class AB or low power mode; operating the second amplifier in a class B, class G, class H and/or low power mode; and providing selective or feedback connections from the outputs of the first and second amplifiers to the inputs of the first and second amplifiers and to a load to keep the first and second amplifiers operating in their respective modes.

In accordance with another aspect of one or more embodiments disclosed herein, a low power, low distortion amplifier includes a plurality of cascaded stages, wherein a driver stage is biased to operate in a class AB mode, a main output stage is operated in a low power consumption mode, and a plurality of impedance networks provide feedback paths or connections between the outputs and inputs of the cascaded stages or loads, whereby the amplifier provides low distortion and maintains a substantially constant frequency response over a wide range of frequencies. The low power amplifier may be configured to have very low off-going or dynamic power consumption.

According to some embodiments or variations, the first amplifier may operate in class G or class H mode.

Other embodiments, alternatives, and variations are also described or illustrated herein in the drawings.

Drawings

Fig. 1 is a general schematic diagram of a conventional linear amplifier known in the prior art.

Fig. 2 is a schematic diagram illustrating an amplifier including an impedance network or device according to one embodiment disclosed herein.

Fig. 3 is a schematic diagram of another embodiment similar to the amplifier of fig. 2 but with an additional feedback loop.

Fig. 4 is an example of distortion performance that can be achieved by an amplifier at certain load parameters according to the principles disclosed herein.

Fig. 5 is a block diagram of another amplifier design using an amplifier cascading technique.

Fig. 6 is a block diagram illustrating another example of an amplifier design in accordance with various embodiments disclosed herein.

Fig. 7a is a schematic diagram of a current limiting circuit known in the prior art, while 7b is a schematic diagram of an alternative current limiting circuit that may be used in connection with the various embodiments disclosed herein.

Fig. 8a and 8b are plots comparing the frequency response of different amplifier designs.

Detailed Description

In accordance with one or more embodiments, a low power amplifier is provided having at least a first amplifier configured as or including a driver stage and a second amplifier configured as or including a main output stage that is biased to an operating mode that requires very little idle power when enabled and yet consumes very little dynamic power. The plurality of impedance networks provide, among other things, a feedback path from the outputs of the first and second amplifiers to the first amplifier, thereby enabling the low amplifier to withstand distortion to some extent. The impedance network may also provide a connection path from the second amplifier output, including the main output stage, to the load and a connection path from the first amplifier output, including the driver stage amplifier, to the load. The impedance network is preferably a resistor, a capacitor or a combination of networks with respect to them.

An additional feedback path is also provided at the input from the load to the first amplifier. The additional feedback path may include a low pass filter and more specifically a T-network of two resistors and capacitors and may assist the amplifier in leveling the frequency response at low frequencies. An intermediate amplifier stage may also be sandwiched between the driver stage amplifier and the main output stage to provide additional various functions and distortion reduction.

Both the first amplifier and the second amplifier are preferably operated in a low power consumption mode, although in some embodiments where power consumption is not important, one or both amplifiers can be operated in a high power consumption mode to simplify design, further reduce distortion (if necessary), or for some other reason. As used herein, the low power mode or modes generally include which non-operational or idle current power consumption remains low operating modes, and thus generally include class B, class G, and class H modes, and potentially class AB in some configurations.

As one example, a first amplifier including a driver amplifier stage may operate in class AB mode, while a second amplifier including a main output stage may operate in class B and/or class G or class H mode. Thus, the overall apparent power of the amplifier can be kept very low. The second amplifier may alternatively be operated in class AB mode at increased power consumption, which may further reduce distortion. As another example, both the first amplifier and the second amplifier can operate in class G mode, or both operate in class H mode or one operates in class G mode and the other operates in class H mode. The novel amplifier designs disclosed and taught herein thus provide greater flexibility and versatility in operating mode selection and overall design configuration. Amplifier designs can be tailored to specific purposes including very low power consumption, compact structure, and the like or combinations thereof.

Fig. 1 is a general schematic diagram of an example of a conventional linear amplifier 100 known in the prior art. As shown in fig. 1, linear amplifier 100 includes input and output stages 110, a driver stage 120, and an output stage 150, which output stage 150 may include, for example, a pair of resistors 131 and 132 (also labeled Q1 and Q2 in fig. 1) connected to positive and negative voltage rails 130, 135 (also labeled + V and-V in fig. 1). The output stage 110, the driver stage 120 and the output stage 150 are connected in a sequential arrangement. The input stage 110 receives an input signal 106 from an input signal source 105. The output stage resistors Q1, Q2 are biased to either the class B or class AB mode of operation by a voltage source 128 (also designated Vb). Although shown as a single resistor in fig. 1, the output stage resistors Q1 and Q2 may be implemented as different circuit types, such as a single resistor, a composite resistor, or a FET. The output stage 150 provides an amplified output signal 140 to the load 145 (representing the impedance in fig. 1).

Also in fig. 1, feedback capacitor 124 (also labeled Z2 in fig. 1) applies local feedback around driver stage 120 while ensuring stability by introducing 6 dB/octave to the open loop frequency response of amplifier 100. Driver stage 120 is typically biased into class a operation. The input stage 110 is typically implemented as a transconductance stage (transconductance). The additional resistors 115 and 112 (also labeled R4 and Rg in fig. 1) provide overall negative feedback around the entire amplifier.

As mentioned earlier, this type of amplifier typically suffers from poor idle and dynamic power consumption performance when biased to AB operation, and poor distortion performance when biased to B-stage operation. Power consumption can be reduced by the G-stage mode, but then more distortion mechanisms are introduced that are difficult to solve by conventional negative feedback.

In accordance with one or more embodiments disclosed herein, and as explained for example with respect to fig. 2, distortion is significantly reduced in the conventional linear amplifier of fig. 1 by the signal path from gain/driver stage X1 to the output provided by impedance network Z3, while introducing the other impedance network Z1. Fig. 2 is a schematic diagram of a novel amplifier design illustrating, in one example manner, beneficial impedance network devices and other amplifier circuitry, according to one embodiment disclosed herein. In fig. 2, amplifier 200 includes, among other things, a gain/driver stage 210 (also labeled as X1 in fig. 2) and an output stage 250, which output stage 250 may include, for example, a pair of transistors 231 and 232 connected to positive and negative voltage rails + V and-V (not shown in fig. 2) similar to fig. 1. The gain/driver stage 210 receives an input signal 206 from an input signal source 205. Although shown in fig. 2 as a single transistor, as in fig. 1 and all others that will be described herein, the output stage transistors Q1 and Q2 may be implemented as different types of circuits, such as single transistors, composite transistors, or FETs. The output stage 250 provides an amplified output signal 240 to a load 245 (represented as an impedance in fig. 2).

More generally, although gain/stage 210 is conceptually illustrated in fig. 2 as a single amplifier, it may be constructed of multiple amplifier stages or may be included as part of a larger amplifier block. Likewise, while output stage 250 is shown as being comprised primarily of transistors Q1 and Q2, it may be included as part of a larger amplifier block containing one or more stages, and will also be understood to include biasing components, protection elements, and other conventional components not shown in detail in fig. 2 for the sake of brevity. Those skilled in the art will appreciate that there are many different ways to implement the gain/driver stage 210 and the output stage 250 of the amplifier 200.

As described above, an impedance network 290 (also labeled Z3 in fig. 2) is provided between the gain/driver stage 210 and the load 245. Another impedance network 280 (also designated Z1 in fig. 2) is provided between the output stage 250 and the load 240. Another impedance network 270 (also labeled Z2 in fig. 2) is provided in a differential from the output of the gain/driver stage to the gain/driver stage 210. A fourth impedance network 260 (also labeled Z4 in fig. 2) is provided in the same differential input from the output stage 250 to the gain/driver stage 210. The impedance networks 260 and 270 are connected to ground (or other reference potential) through another impedance network 212 (also labeled Zg in fig. 2).

In the example of fig. 2, the impedance network 290 is implemented as a capacitor 291 and a resistor 292 connected in parallel. Impedance network 280 is implemented as resistor 281. Impedance network 270 is also implemented as circuit 271. The impedance network 260 is implemented as a resistor 262 and a capacitor 261 connected in series.

By selecting the values of the impedance networks Z1, Z2, Z3, Z4 to satisfy the relationship Z1(s) × Z2(s) ═ Z3(s) × Z4(s), the distortion of the amplifier 200 is significantly reduced compared to the standard feedback amplifier type shown in fig. 1. As described above, in this example, the impedance network Z1 is preferably implemented as a resistor, the impedance network Z2 is preferably implemented as a capacitor, the impedance network Z3 is preferably implemented as a parallel combination of a resistor and a capacitor, and the impedance network Z4 is preferably implemented as a series combination of a resistor and a capacitor, although other equivalent impedance networks may also be used. The time constant of impedance network Z3 is preferably matched to the time constant of impedance network Z4. At low frequencies, below the frequency at which the impedance Z3 becomes capacitive, the impedance network Z3 appears resistive in nature and the impedance network Z4 appears capacitive. The presence of impedance network Z3 softens the crossover point of output stage 250 since impedance network Z3 connects the driver stage to the load.

To achieve maximum distortion reduction, the impedance network Z4 is preferably capacitive in nature, such that the impedance ratio Z2: Z4 is equal to Z3: Z1. However, this means that the open loop gain of the feedback loop around the output stage 250 no longer decreases with frequency. The combination of the series resistors in Z4 again recovers a gain drop as the frequency exceeds the knee point where Z4 stops exhibiting capacitive and becomes resistive in nature. Resistor 262 in impedance network Z4 is selected to set the overall loop gain frequency to ensure stability.

To keep the overall distortion reduced, the impedance network Z3 should be made capacitive at high frequencies; thus matching the time constants of the impedance networks Z3 and Z4. There is generally a free choice of time constants for the components of the impedance networks Z3 and Z4. However, the larger the time constant, the larger the capacitor in impedance network Z3 at high frequencies, and the larger the current that can be drawn from gain/driver stage 210 (i.e., X1). To minimize the size of amplifier 200, the time constants of impedance networks Z3 and Z4 should be kept low.

Balancing of the impedance network (balancing) will work even if there are parasitic elements in the impedance network. For example, a parasitic inductor in series with resistor 281 can be balanced by a resistance of an appropriate value placed in series with capacitor 291. As reflected in the example of fig. 2, all of the components of the impedance network Z1-Z4 can be implemented by resistors, capacitors, or a combination thereof (including parasitic elements). This design approach enables the fabrication of very compact amplifier packages. In this context, the term "resistor" includes any resistive element that exhibits a substantially constant impedance over the applicable operating frequency range, and generally, but not necessarily, conventional discrete resistor elements are introduced.

By itself, the selection and arrangement of the impedance network in fig. 2 works adequately but can be improved. For example, the incorporation of series capacitor 262 within impedance network Z4 means that the closed loop gain of the complete amplifier 200 rises by 6 dB/octave with decreasing frequency below the knee frequency formed by elements 261 and 262 of its series resistor/capacitor combination. Furthermore, due to the arrangement of the impedance networks Z2 and Z4 and the gain/driver stage 210, the open loop gain around the transistors Q1, Q2 is constant at low frequencies rather than increasing with decreasing frequency by 6 dB/octave as in conventional feedback amplifiers. Thus, distortion reduction around transistors Q1 and Q2 through negative feedback will be reduced compared to a conventional amplifier with such a selected impedance network. Additional distortion reduction will be achieved by incorporating impedance network Z3 into amplifier 20 two, but there is still room for improvement, as will be explained in more detail below. Further, the output impedance of amplifier 200 is approximately equal to the parallel combination of impedance networks Z1 and Z3. In case the first impedance network Z1 is implemented as a resistor, the output impedance of the amplifier 200 at low frequencies is generally higher than in case of a pure conventional feedback amplifier as illustrated in fig. 1.

Fig. 3 illustrates how other improvements in performance and closed loop response to distortion may be made on the basic amplifier design of fig. 2. In FIG. 3, elements labeled 3xx are generally responsive to similar elements labeled 2xx in FIG. 2. In fig. 3, an amplifier 300 receives an input signal 306 from an input signal source 305. Similar to amplifier 200 of fig. 2, amplifier 300 of fig. 3 includes a gain/driver stage 310, an output stage 350 including transistors 331 and 332 (also labeled Q1 and Q2), and impedance networks 360, 370, 380, and 390 (also labeled Z4, Z2, Z1, and Z3, respectively, in fig. 3). A network 356 including resistors 352, 353 (also labeled R5, R6 in fig. 3) and a capacitor 354 (also labeled C7 in fig. 3) has been added to the amplifier 300 to form an additional feedback loop. The feedback is taken from the final output 340 of the amplifier 300 rather than directly from the output stage 350, although it is then fed to the same feedback input terminal of the gain/driver stage 310 as the existing feedback loop based on impedance networks Z2 and Z4. Nevertheless, this connection of the additional feedback loop is not disturbed to maximize the distortion reduction.

Simply another resistive feedback path to the amplifier arrangement of fig. 2 will generally result in a non-flat frequency response because the additional feedback loop is placed near the closed loop system of fig. 2 and the closed loop gain is not large enough to ensure that the final closed loop response of the amplifier is independent of the value of the closed loop gain of fig. 2. However, by designing the additional feedback network to have a low pass filter response with a cutoff frequency matching the knee frequency of the impedance networks Z3 and Z4 and an appropriate gain, the overall amplifier 300 can then be designed to have a flat response. Thus, raising the low frequency response of the amplifier system of fig. 2 is perfectly compensated by the added design of fig. 3.

The additional feedback loop provided by the added feedback network 356 of fig. 3 also additionally reduces low frequency distortion, thereby compensating for the amplifier embodiment of fig. 2 that compromises low frequency distortion performance. In addition, this additional feedback loop also reduces the output impedance of the amplifier at low frequencies because the feedback is taken directly across the load 345 and thus the impedance network Z1 is within the feedback loop.

Having an additional overall frequency dependent feedback loop to lower the output impedance of amplifier 30 allows bridge impedance network Z1 to have a higher impedance than would otherwise be possible, within the limits of power loss in resistor 381 of impedance network Z1; therefore, the impedance of element Z3 can be similarly raised to lower the value of the shunt capacitance and thereby the high frequency current must originate from gain/driver stage 310.

The available choice of capacitor and resistor values for Z1-Z4 for the impedance network means that the balance at the high frequency range can be more accurately achieved because the values of the capacitors and resistors used for the amplifier design of FIG. 3 can be readily obtained through tight manufacturing tolerances. The voltage presented across capacitor 391 in impedance network Z3 is very small (it is simply the gain/error loss of the output stage plus the product of the output current times the impedance of Z1) and given that capacitor 391 requires a low voltage request, its package size is also quite small, allowing for miniaturization of amplifier 300. Multiple amplifiers using the design shown in fig. 3 can be located very close together, with small interaction between the impedance networks, since there are no balanced inductors, which means that there is less chance of magnetic connection between the amplifiers.

The use of additional impedance networks Z1, Z2, Z3 and Z4 and the additional feedback loop provided by the addition of feedback network 356 allows the high frequency distortion of amplifier 300 to be significantly reduced compared to conventional feedback amplifiers and thus output stage 350 can potentially operate in, for example, class B mode while still avoiding crossover distortion. Thus, the idle power dissipation that would normally occur due to the quiescent current required to bias the conventional amplifier output stage to class AB mode is eliminated by the design of fig. 3. This may be of limited use if the gain/driver stage 310 of the amplifier 300 needs to have a high on-load current drain. However, in this example the gain/driver stage 310 operates at a lower power than the main output stage 350 based on surrounding transistors Q1 and Q2. And thus the gain/driver stage 310 can be referred to as an AB stage output stage 350 with linear, fast output devices (transistors Q1 and Q2) and thus still operate with low distortion compared to the main output stage 350. Thus, the power consumption at the gain/driver stage 310 can also be very low.

By incorporating a low power AB stage inside the gain/driver stage 310, the distortion introduced to the error signal by the AB stage operation of the gain/driver stage 310 can be made very small. In general, for an audio power amplifier capable of delivering 100 watts of nominal output power into a 16 ohm load according to the design shown in fig. 3, the gain/driver stage 310 can be configured to operate with a quiescent current of only 1-2 milliamps, for example, which is very low.

The dynamic power consumption of the amplifier 300 can also be reduced by using a G-stage or H-stage architecture, provided that the high frequency distortion of the output stage 350 is significantly reduced. Unlike conventional feedback amplifiers, transitions from G-rail switches or H-stage high frequency tracking algorithms will be reduced by using the amplifier feedback configuration of some embodiments disclosed herein to enable very low distortion, windfarm no-load power consumption, lower dynamic power consumption amplifiers. One example of a tracking power supply that can be incorporated into the amplifier design disclosed herein to provide additional power savings is described in co-pending U.S. patent application publication No. 12/253,047 filed on 16/10/2008, which has been assigned to the assignee of the present application and is hereby incorporated by reference as if fully set forth herein. Using a G-stage or G-stage architecture for the first amplifier comprising the gain/input stage may have the potential to introduce non-linearities into the system, which needs to be controlled or otherwise taken into account.

In the case where a G-stage or H-stage architecture is applied to the first and second amplifiers, no power silicon (with different voltage levels) may be provided to the first and second amplifiers to, for example, assist in isolation, reduce non-linearity, and minimize power consumption.

Fig. 4 shows one example of distortion performance achieved by the construction of an amplifier according to the principles listed above when a 56 volt peak signal can be driven to 16 ohms using an amplifier design constructed according to fig. 3. As shown in fig. 4, the total harmonics is that this is very low at relatively low frequencies (typically from about 0.0003 to 0.0010 percent distortion level at 1 kHz) and remains low at high frequencies (typically from about 0.0020 to 0.0050 percent distortion level at 10 kHz).

Fig. 8a and 8b idealized frequency response plots showing the effect of the additional feedback loop 356 in the embodiment of fig. 3. Fig. 8a shows that at relatively low frequencies, the overall amplifier gain drops, then stays horizontal in the flat region (shelfrection), and then drops again as the frequency increases. By using the additional feedback loop of fig. 3, the frequency response can be changed as shown in fig. 8B. The low frequency response is very well compensated by the outer feedback loop resulting in a flat frequency response output with relatively high frequencies. The outer frequency loop can also be used for additional purposes, such as extending the operating range of the amplifier by introducing additional zeros and poles at high frequencies.

Modifications or extensions not specifically described can also be made to the amplifier structure described above. For example, although the distortion of the AB stage gain/driver stage 310 may be made low compared to the output stage 350, it will produce some residual distortion. To overcome this disadvantage, the AB stage gain/drive stage 310 itself can use the same distortion reduction techniques as those used around the output stage 250, as previously listed in connection with fig. 2.

This "cascading" approach is illustrated in the amplifier design shown in fig. 5. Elements labeled "5 xx" in fig. 5 generally correspond to similar elements labeled "3 xx" in fig. 3. In fig. 5, an amplifier 500 receives an input signal 506 from an input signal source 505. Similar to the design of fig. 3, amplifier 500 includes a gain/driver stage 510, an output stage 550 including transistors 531 and 532 (also labeled as Q1 and Q2), and impedance networks 560, 570, 580, 590 (also labeled as Z4, Z2, Z1, and Z3, respectively, in fig. 5). Including resistors 552, 552 (also labeled R5, R6 in fig. 5) and capacitor 554 (also labeled C7 in fig. 5) are included in the amplifier 500, which has the same general purpose as in fig. 3, and carries the final output 540 of the curved sub-amplifier 500 and is input to the feedback input terminal of the gain/driver stage 350. Also added to fig. 5 is an intermediate stage 542 which functions, in one aspect, as a second or supplemental driver stage, including transistors 543 and 544 (also labeled Q3 and Q4) and voltage bias blocks 546 and 547. Transistors 543 and 544 are connected to positive voltage rail + V and negative voltage rail-V, respectively, and may be biased to class AB mode of operation by bias blocks 546 and 547.

The output of the intermediate stage 542 is connected to the input of the output stage 550 via a resistor 529 (also labeled Z1i in fig. 5). An additional resistor 528 (also designated as Z3i) is connected from the input of the output stage 550 to the input of the intermediate stage 542. The feedback taken from the impedance network 590(Z3) is therefore passed through resistor 528 for the purpose of the intermediate stage 542, although it is still applied directly to the input of the output stage 550. An additional capacitor 548 (also labeled Z2i in fig. 5) is provided from the output of gain/driver stage 510 to a feedback input terminal with respect thereto. The feedback derived by the impedance network is taken from the output of the intermediate stage 542 rather than the output of the gain/driver stage 510. The additional elements 529, 548 and 528(Z1i, Z2i and Z3i) form part of the inner feedback loop, while the impedance network 570(Z2) shares its operation between the inner and outer feedback loops.

Both gain/driver stage 510 and intermediate stage 542 provide some method of feed-forward operation, in that they both provide current to the load when column output stage 550 is relatively unloaded, and they are both considered to have some degree of driver functionality. Both stages may also supply gain. In this regard, the designation of a particular stage as "gain" or "driver" is not intended to be limiting.

In the example shown in fig. 5, the inner loop components 529, 548 and 528(Z1i, Z2i and Z3i) have been selected, and impedance network 570, such that the inner loop implements the distortion reduction case described for the amplifier design of fig. 3, where the AB stage (i.e., the inner output stage of gain/driver stage 510 in some embodiments) maintains an integrator-type response with respect to the effects observed by the outer loop. A resistor 572(R2) has been added to the impedance network 570(Z2) to help ensure stability of the inner feedback loop around transistors Q3 and Q4, while another resistor 593(R3i) has been added to the impedance network 590(Z3) to compensate the outer feedback loop for the zero order introduced into the integrator response through resistor 572. This arrangement makes it possible to keep the other outer ring components of the impedance network Z1-Z4 the same as in the example illustrated in fig. 3. The high frequency off-record of the improved driver stage, including the gain/driver stage 510 and the intermediate stage 542, allows for stability of the feedback loop around the output stage 550, and ultimately the overall feedback loop still allows for low output impedance of the amplifier 500 at audio frequencies.

Other arrangements of the inner loop impedance network are also possible. For example, if an additional gain stage is introduced before the gain/driver stage 510, then the capacitor 571(C2) in the impedance network 570(Z2) may be dispensed with and the resistor 528(Z3i) may be replaced by a capacitor. The gain of this inner loop will then be flat over frequency, so an additional gain stage may give the integrator response and the outer bridge and loop components Z4, R5, R6, C7, Zg may be connected to the input of the additional integrator gain stage.

Such a device is illustrated in detail in fig. 6. Elements labeled "6 xx" in fig. 6 generally correspond to similar elements labeled "5 xx" in fig. 5. In fig. 6, an amplifier 600 receives an input signal from an input signal source 605. Similar to fig. 5, the amplifier 600 includes a gain/driver stage 610B, an output stage 650 including transistors 643 and 644 (also labeled as Q3 and Q4) and voltage bias components 646 and 647, and transistors 631 and 632 (also labeled as Q1 and Q2), and impedance network impedance networks 660, 670, 680, 690 (also labeled as Z4, Z2, Z1, and Z3, respectively, in fig. 6). An additional gain stage 610A has been added before gain/driver stage 610B. The amplifier 600 further includes an external feedback network 656 comprising resistors 652, 653 (designated R5, R6) and a capacitor 654 (designated C7), which has the same purpose as fig. 3 and 5, wherein feedback is taken from the final output 640 of the amplifier 600 and delivered to the feedback input terminal of the gain stage 610A. In this case, impedance network 670(Z2) is positioned between the output of gain stage 610A and the input terminal feedback of gain stage 610A. Similarly, impedance network 660(Z4) is positioned between the output of driver stage 650 and the feedback input terminal of gain stage 610A.

Feedback from the input of gain/driver stage 610B is continuously input into the feedback input terminal of gain/driver stage 610B through capacitor 648(Z2 i). The feedback connection is also made from the output of the intermediate stage 642 to the feedback input terminal of the gain/driver stage 610B. In this case, the feedback element is resistor 619 (also labeled R2), the feedback element is resistor 619 (also labeled R2), and another resistor 618 has been added connecting the feedback input terminal of gain/driver stage 610B to ground (or some other reference potential). Capacitor 628 and resistor 629 (also designated as Z3i and Z1i, respectively) perform similar functions to their counterparts in fig. 5, both of which form part of an internal feedback loop.

In the design of fig. 6, added gain stage 610A is configured with an integrator response (using capacitor 671 of impedance network Z2), and outer bridge and loop components Z4, R5, R6, C7, Zg are connected to the feedback input of added gain stage 610A instead of gain/driver stage 610B. The gain of the inner feedback loop, including resistors 618 and 619(Rgi and R2), is flat with frequency.

As with fig. 5, in the example of fig. 6, the other inner ring members 629, 648 and 628(Z1i, Z2i and Z3i), and impedance network 670(Z2) are selected so that the inner ring implements the distortion reduction condition described for the amplifier design of fig. 3, where the stages of the AB stage (i.e., the internal output stage of gain/drive stage 510 in some embodiments) maintain the integrator type response in terms of the effect observed by the outer ring. The selection of the outer loop impedance network value to ensure maximum distortion reduction has taken into account the gain of the inner loop, which raises the effective impedance Z2 by the ratio [ R2+ Rgi ]/Rgi. Resistors are no longer needed in the impedance network 670(Z2) to ensure stability of the feedback loop around transistors Q3 and Q4. The arrangement here makes it possible to keep the other outer loop components of the impedance network Z1-Z4 of the amplifier design of fig. 3 the same. The high frequency rating of the inner amplifier subsystem comprising gain stage 610A, gain/driver stage 610B and intermediate stage 642 allows for stability of the feedback loop around output stage 650, and ultimately the overall feedback loop still allows for low output impedance of amplifier 600 at audio frequencies.

If the output impedance of the internal amplifier subsystem is an appropriate value compared to impedance Z3, then impedance network Z3 can be modified (i.e., raised) to ensure proper distortion reduction.

By utilizing these additional network devices in the amplifier designs of fig. 5 and 6, the power consumption of the AB driver stage (i.e., the internal output stage of gain/driver stage 510 or 610B in some embodiments) can be made very low by further reducing the AB stage quiescent current, since its distortion can be greatly reduced by the described techniques. The stage of the AB stage of the gain/driver stage 510 or 610B may itself be biased as the B stage, resulting in a reduction in idle power consumption.

A further reduction in idle power consumption can be obtained by running the gain/driver stage 210, 310, 510 or 610B in either the G-stage or H-stage mode, since the static power supply voltage to the gain/driver will be lower than would otherwise be the case. This may also be in the way of a royal city without the additional network of fig. 5 or 6, but requires additional attention in order to eliminate any power supply switch peak voltage (spike) affecting the gain/driver stage output. The additional network circuitry allows any switching distortion introduced into the gain/driver stage to be significantly reduced

The amplifier typically incorporates a small current sense resistor in series with the output transistor to provide a current limiting protection circuit. The impedance networks used in the various amplifier designs of fig. 2, 3, 5 and 6 can be used to replace the harmonious current sense resistances as depicted in fig. 7a and 7 b. Fig. 7a shows a conventional current limiting circuit arrangement, wherein a push-pull output stage 700 comprises an n-type transistor 711 and a p-type transistor 712 (also denoted as Q1 and Q2) interconnected by a combination of circuits comprising transistors 721, 722, and 723 (also denoted as Q3, Q4, and Q5, respectively), a current source 724 (also denoted as I1), and resistors 714 and 715, through which an output signal reaches a final output 720 of the output stage 700. The amount of current that can be output from transistor 711 is limited by the current through resistor 714, and in turn is determined by the ratio of the base to emitter voltage of transistor 721. Resistor 715 and transistor 722 operate in a similar manner to protect transistor 712 from excessive output current.

Fig. 7b, on the other hand, shows a modified current limiting circuit arrangement that avoids resistors 714 and 715 with the presence of impedance network Z1. In fig. 7b, the output stage 750 includes an n-type transistor 731 and a p-type transistor 732 (also labeled Q1 and Q2) that are again interconnected by a combination of circuits including transistors 751, 752, and 753 (also labeled Q3, Q4, and Q5, respectively), a current source 754 (also labeled I1), and in this case, a resistor 781 that may be a resistor of the impedance network Z1 of any of the previously described embodiments. In this case, when transistor 731 is on, then the resistor is used to limit the output current in the same manner as resistor 714, i.e., using the relatively fixed base-to-emitter voltage ratio of n-type transistor 751 to limit the output current, and when transistor 732(Q2) is on, then resistor 781 limits the output current in the same manner as resistor 715, i.e., using the relatively fixed emitter-to-base voltage ratio of p-type transistor 752 to limit the output circuit.

The invention has been generally illustrated and discussed with specific reference to audio power amplifiers, but is in no way intended to be limited to this field of application. The disclosed techniques apply to, among other things, low power audio amplifiers, video amplifiers, and radio frequency amplifiers, for example.

According to various embodiments disclosed herein, power amplifiers with low power consumption are provided, and more particularly, power amplifiers capable of low idle and dynamic power consumption levels. The power amplifier may not require bias settings and may be even more free of inductors for EMI or filtering. The power amplifier may also deliver very low distortion levels.

In certain embodiments described herein, a low power, low power dissipation amplifier includes a gain/driver stage, an optional intermediate stage, and an output stage in a cascaded arrangement. The connection path, which in one aspect may be considered a feed-forward path, is provided from the output of the gain/driver stage to the load via a feed-forward impedance network, which may include a capacitor and a resistor in parallel. The output stage may be connected to a load through another impedance network, such as a resistor. The output stage may also be connected to the input of the gain/driver stage by a further impedance network, which may take the form of a capacitor and a resistor in a series arrangement. The output of the gain/driver stage may also be connected to its input through another impedance network, which may take the form of a capacitor.

Furthermore, a feedback network may be provided from the load to the input of the gain/driver stage for stabilization, which may have the effect of leveling the overall frequency response at low frequencies and will keep the response constant at high frequencies. The additional feedback network may take the form of a low pass filter and, more particularly, a T-network of resistors and capacitors connected in series between their common point and a reference voltage (e.g., ground). An additional feedback network may be used to counteract the resistive characteristic of the frequency response of the feed-forward impedance network at low frequencies. Because the additional feedback network is fed into the negative input of the gain/driver stage, it effectively cancels the low frequency components of the amplifier frequency response contributed by the feed-forward impedance network.

In some embodiments, an additional intermediate amplifier stage may be provided which in some aspects acts as a driver stage and has a feed-forward path connected to the load via a third impedance element.

In some embodiments, the main output stage operates in class B mode, while the gain/driver stage operates in class AB mode, thus resulting in a low power consumption configuration. At low signal levels, the gain/driver stage (and/or intermediate amplifier stage) may provide drive for the output signal via a feed-forward or connection (through impedance network Z3) between the gain/driver (and/or intermediate amplifier stage) and the load, while at high signal levels, the main output stage drives the load. In an alternative embodiment, one or both of the gain/driver stage and the main output stage operate in either the G-stage or H-stage mode, with an increased appropriate power supply for the amplifier. In alternative embodiments, the main output stage may operate in class AB, or otherwise class A mode. While doing so may increase power consumption, this configuration still takes advantage of other benefits provided by the novel designs discussed herein.

The novel power amplification embodiments of fig. 2, 3, 5 and 6 may be implemented in very small packages and in particular may be packaged entirely on a single chip, with the possible exception of capacitive components with impedance network Z3, which may be larger in some cases but still relatively small compared to the inductor, thus allowing for smaller overall package sizes. Because of the low power consumption of the amplifier, a plurality of amplifiers (e.g. four, eight, or possibly more) may be included on a single chip without risk of overheating. Such chips can be particularly convenient for multi-channel amplifier systems, such as those used in audio applications or other purposes.

As described above, the amplifier designs disclosed herein may be suitable for a variety of different applications, including audio or sound reproduction, communications, satellite, and other applications. The new amplifier design can potentially have a very wide frequency range with substantially flat or constant gain while maintaining low power consumption and low distortion. For example, the amplifier may provide a relatively flat or constant gain over 20Hz to 20kHz audio applications, but is not limiting and may theoretically provide a flat or constant gain over a wider bandwidth, again depending on the particular application.

While preferred embodiments of the invention have been described herein, many variations are possible which remain within the concept and scope of the invention. Such variations would become clear to one of ordinary skill in the art after inspection of the specification and drawings. The invention, therefore, is not to be restricted except in the spirit and scope of any appended claims.

Claims (45)

1. A power amplifier system, comprising:

a first amplifier for receiving an input source signal;

a second amplifier downstream of the first amplifier; and

a plurality of impedance networks providing (i) feedback paths from outputs of the first and second amplifiers to an input of the first amplifier, respectively; (ii) (ii) a first connection path from the output of the second amplifier to a load, and (iii) a feed-forward signal path from the output of the first amplifier to the load;

wherein all of said impedance networks are comprised of resistors, capacitors, or a network combination thereof.

2. The power amplifier system of claim 1 wherein the first impedance network providing the first connection path comprises a resistor connected between the output of the second amplifier and the load.

3. The power amplifier system of claim 2, wherein a second impedance network of the plurality of impedance networks provides a first feedback path from an output of the first amplifier to an input of the first amplifier, the second impedance network comprising a capacitor.

4. The power amplifier system of claim 3 wherein a third impedance network of the plurality of impedance networks providing the feed-forward signal path comprises a resistor and a capacitor connected in parallel between the output of the first amplifier and the load.

5. The power amplifier system of claim 4 wherein a fourth impedance network of the plurality of impedance networks provides a second feedback path from the output of the second amplifier to the input of the first amplifier, the fourth impedance network comprising a capacitor and a resistor in series.

6. The power amplifier system of claim 1 wherein a fifth impedance network of the plurality of impedance networks provides a third feedback path from the load to the input of the first amplifier, the fifth impedance network comprising a low pass filter.

7. The power amplifier system of claim 1, wherein the second amplifier operates in class AB mode, class G mode, or class H mode.

8. The power amplifier system of claim 7 wherein the first amplifier operates in class AB mode.

9. The power amplifier system of claim 1 wherein the power amplifier system has a constant frequency response over a low frequency band.

10. The power amplifier system of claim 1, wherein each of the plurality of impedance networks consists of only one or more resistors, one or more capacitors, or a network combination thereof.

11. A power amplifier system, comprising:

a first amplifier that receives an input signal to be amplified and supplies it to a load;

a second amplifier downstream of the first amplifier, the second amplifier operating in a low power consumption mode;

a feed-forward network connecting an output of the first amplifier to the load, the feed-forward network comprising a capacitor and a resistor in parallel;

a resistor connecting the second amplifier to the load; and

a plurality of negative feedback paths from respective outputs of the first and second amplifiers to an input of the first amplifier.

12. The power amplifier system of claim 11 further comprising an additional feedback path from the load to an input of the first amplifier.

13. The power amplifier system of claim 12 wherein the additional feedback path includes a low pass filter and is configured to cancel the frequency response of the power amplifier system at low frequencies without the additional feedback path, thereby providing a constant frequency response at low frequencies.

14. The power amplifier system of claim 11, wherein the second amplifier operates in class B mode.

15. The power amplifier system of claim 14 wherein the first amplifier operates in class AB mode.

16. The power amplifier system of claim 11, wherein the second amplifier operates in class G or class H mode.

17. The power amplifier system of claim 16 wherein the first amplifier operates in class AB mode.

18. The power amplifier system of claim 11 wherein each of the negative feedback paths comprises a feedback network comprising only one or more resistors, capacitors, or a combination thereof.

19. The power amplifier system of claim 11, further comprising an intermediate amplifier stage disposed between the first amplifier and the second amplifier.

20. A low dissipation amplifier, comprising:

a driver amplifier for receiving an input signal;

an output amplifier;

a first impedance network Z1 connecting the output amplifier to a load;

a second impedance network Z2 providing a feedback signal indicative of the feedback signal from the output of the driver amplifier to the input of the driver amplifier;

a third impedance network Z3 providing a feed-forward signal path from the output of the driver amplifier to the load; and

a fourth impedance network Z4 providing a feedback signal indicative of the output amplifier to the input of the driver amplifier;

wherein the third impedance network Z3 comprises a capacitor and a first resistor in parallel; and

wherein the first impedance network Z1 comprises a second resistor.

21. The low dissipation amplifier of claim 20, wherein said second impedance network Z2 comprises a third resistor, and wherein said fourth impedance network Z4 comprises a fourth resistor and a second capacitor in series.

22. The low dissipation amplifier of claim 21, wherein each of said first, second, third or fourth impedance networks Z1, Z2, Z3 and Z4 consists of only one or more resistors, one or more capacitors, or a network combination thereof.

23. The low dissipation amplifier of claim 20, wherein the low dissipation amplifier does not include a balanced inductor in any of impedance networks Z1, Z2, Z3, and Z4.

24. The low dissipation amplifier of claim 20, further comprising a fifth impedance network providing a feedback path from the load to an input of the driver amplifier.

25. The low dissipation amplifier of claim 20, wherein the values of said first, second, third and fourth impedance networks Z1, Z2, Z3 and Z4 satisfy the relationship Z1(s) × Z2(s) ═ Z3(s) × Z4(s).

26. The low dissipation amplifier of claim 20, wherein the time constant of said third impedance network Z3 matches the time constant of said fourth impedance network Z4.

27. The low dissipation amplifier of claim 26, wherein the impedance characteristic of impedance network Z3 appears capacitive at high frequencies.

28. The low dissipation amplifier of claim 27, wherein the impedance characteristic of said third impedance network Z3 is resistive at low frequencies below where the impedance characteristic of said third impedance network Z3 is capacitive.

29. The low dissipation amplifier of claim 20, wherein said fourth impedance network Z4 comprises a series resistor and a series capacitor, and wherein the value of said series resistor is selected to provide an overall loop gain frequency to promote stability of the low dissipation amplifier.

30. The low dissipation amplifier of claim 20, wherein said output amplifier operates in class B mode.

31. The low dissipation amplifier of claim 30, wherein said driver amplifier operates in an AB mode.

32. The low dissipation amplifier of claim 20, wherein said output amplifier and said driver amplifier each operate in class G or class H mode.

33. The low dissipation amplifier of claim 20, further comprising an intermediate amplifier stage disposed between said driver amplifier and said output amplifier.

34. A method of amplifying an input source signal, comprising:

receiving the input source signal at a first amplifier and generating therefrom a driver signal;

providing the driver signal to an input of a second amplifier as a primary output stage;

operating the first amplifier in class AB mode;

operating the second amplifier in class B, class G, or class H mode; and is

Providing selective connection paths or feedback paths from the outputs of the first and second amplifiers to the inputs of the first and second amplifiers and to a load to keep the first and second amplifiers operating in their respective modes while alternatively driving the load from the first and second amplifiers through the connection paths;

wherein the connection path consists of only a resistor element and a capacitor element.

35. The method of claim 34, comprising the steps of: the driver signal is provided to an intermediate amplification stage before being provided to the second amplifier.

36. The method of claim 34, wherein the step of providing a selective connection path or a feedback path comprises connecting the load to the output of the first amplifier through a capacitor and a resistor in parallel.

37. The method of claim 36, wherein the step of providing a selective connection path or a feedback path comprises connecting the load to an output of the second amplifier through a resistor.

38. The method of claim 37, wherein the step of providing a selective connection path or a feedback path comprises providing a feedback path from the load to an input of the first amplifier via a feedback network.

39. The method of claim 38, wherein the feedback network comprises a low pass filter.

40. The method of claim 38, wherein the feedback network compensates for a frequency response with low frequency boost associated with a resistor and capacitor in parallel between a load and an output of the first amplifier by making the frequency response constant over a low frequency range.

41. The method of claim 34, wherein the method provides low idle power consumption.

42. The method of claim 41, wherein the input signal remains distortion free.

43. The method of claim 34, wherein the connection or feedback path from the outputs of the first and second amplifiers to the inputs of the first and second amplifiers and to a load is formed by resistors, capacitors, or a combination thereof, without a balancing inductor.

44. The method of claim 34, wherein the second amplifier operates in class B mode.

45. A low dissipation amplifier, comprising:

a driver amplifier connected to the input signal;

an output amplifier;

a first impedance network Z1 connecting the output amplifier to a load;

a second impedance network Z2 providing a feedback signal indicative of the feedback signal from the output of the driver amplifier to the input of the driver amplifier;

a third impedance network Z3 providing a feed-forward signal path from the output of the driver amplifier to the load; and

a fourth impedance network Z4 providing a feedback signal indicative of the feedback signal from the output of the output amplifier to the input of the driver amplifier;

wherein the values of the first, second, third and fourth impedance networks Z1, Z2, Z3 and Z4 satisfy the relationship Z1(s) × Z2(s) ═ Z3(s) × Z4(s); and

wherein all of said impedance networks are comprised of resistors, capacitors, or a combination thereof.