HK1159945A - Core layer structure having voltage switchable dielectric material - Google Patents

Description

Core layer structure with voltage switchable dielectric material

L. Kesosoo cover, R. Fleming

RELATED APPLICATIONS

This application claims priority to U.S. provisional patent application No. 61/091,288 filed on 22/8/2008; the above-mentioned prior application is hereby incorporated by reference in its entirety.

Background

Voltage Switchable Dielectric (VSD) material is material that is insulating at low voltages and conductive at higher voltages. These materials are generally composite materials consisting of conductive, semiconductive and insulating particles in an insulating polymer matrix (matrix). These materials are used for transient protection of electronic devices, in particular for electrostatic discharge protection (ESD) and Electrical Overstress (EOS). Generally, VSD material behaves like a dielectric unless a characteristic voltage or range of voltages is applied, in which case the VSD material behaves like a conductor. There are a variety of VSD materials. Examples of voltage switchable dielectric materials are provided in documents such as us patent No. 4,977,357, us patent No. 5,068,634, us patent No. 5,099,380, us patent No. 5,142,263, us patent No. 5,189,387, us patent No. 5,248,517, us patent No. 5,807,509, WO 96/02924 and WO 97/26665; all of the above documents are incorporated by reference in their entirety.

VSD material can be formed using a variety of methods. One conventional technique is: the polymer layer is filled with high levels of metal particles until very close to the percolation threshold, typically greater than 25% (by volume). Semiconductor and/or insulator materials are then added to the mixture.

Another conventional technique is: VSD material is formed by mixing doped metal oxide powders, then sintering the powders to make particles with grain boundaries (grain boundaries), and then adding the particles to a polymer matrix until a percolation threshold is exceeded.

Other techniques for forming VSD MATERIAL are described in U.S. patent application No. 11/829,946 entitled "VOLTAGE SWITCHABLE DIELECTRIC MATERIAL HAVING switching OR SEMI-switching OR switching MATERIAL arrangement" and U.S. patent application No. 11/829,948 entitled "VOLTAGE SWITCHABLE DIELECTRIC MATERIAL HAVING HIGH ASPECT rating devices".

Drawings

Fig. 1 is an exemplary (not to scale) cross-sectional view of a layer or thickness of Voltage Switchable Dielectric (VSD) material, showing the composition of the VSD material according to various embodiments.

Fig. 2A is a simplified and representative cross-sectional view of a core layer structure used to form a substrate (e.g., a Printed Circuit Board (PCB)) and a packaged device according to one or more embodiments.

Fig. 2B shows the core layer structure of fig. 2A being further processed and layered as part of a build-up (build) process to form a printed circuit board or substrate device.

Fig. 2C illustrates the use of additional material layers over the core layer structure shown in fig. 2B.

Fig. 2D illustrates the use of a resistive material in the core layer structure according to one embodiment.

Fig. 2E shows a core layer structure according to an embodiment, which includes an embedded resistive layer or element to electrically insulate the conductive elements.

Figure 2F is a representative circuit diagram of how the embedded resistive material can be used to electrically isolate selected devices and further protect the selected devices in conjunction with a layer of VSD material according to one embodiment.

Fig. 3 is a representative cross-sectional view of a core layer structure according to another embodiment.

Fig. 4A-4C illustrate a method for forming a core layer structure according to one or more embodiments.

Fig. 5A-5C illustrate a method for forming a core layer structure described herein according to various embodiments.

Fig. 6A and 6B illustrate another embodiment that uses a seed layer to form one of the conductive layers, such as the core layers described herein.

Detailed Description

Embodiments described herein provide a core layer structure with an integrated layer of Voltage Switchable Dielectric (VSD) material, such as for producing a printed circuit board or packaged substrate device. The core layer structure with integrated layers of VSD material has, among other advantages, the inherent ability to handle ESD or EOS events. Such a core layer structure may be used as a building block for producing printed circuit boards or substrate devices; the inclusion of VSD material in the core layer structure enables these devices to more easily provide ground traces and elements to protect the sensitive electrical elements of the device from ESD, EOS or other detrimental electrical events.

Embodiments further confirm that the use of integrated VSD material layers in the core layer structure can be configured to switch vertically (or in a vertical plane) to handle electrical events, such as those caused by ESD or EOS. More specifically, the integrated VSD layer may form the ESD protection circuit in a vertical plane of the substrate (e.g., across the thickness of the substrate) rather than in a horizontal plane of the substrate. Embodiments recognize that these vertical ESD protection circuits can be implemented using VSD material deposited as a thick layer in the foil or conductive core of the substrate device and package. The use of VSD material in the thickness of the conductive layer allows smaller, more controllable gap sizes for the ESD circuit to be formed on the conductive surface. Embodiments described herein provide techniques and improved methods for applying a layer of VSD material within the thickness of a conductive layer or conductive surface.

A core layer structure for a substrate and a packaged device is provided. The core layer structure includes a first layer, a second layer bonded to the first layer. A layer of Voltage Switchable Dielectric (VSD) material is disposed between the first layer and the second layer.

According to some embodiments, at least one of the first layer or the second layer is comprised of a conductive material and is in direct contact with the VSD material. In some embodiments, either the first layer or the second layer is comprised of conductive material and is in contact with the VSD material. Alternatively or in addition, layers of insulating or resistive material may be included in the core layer structure.

Still further, some embodiments provide a core layer structure that uses resistive material in combination with VSD material to electrically isolate discrete components disposed on corresponding conductive layers. In one embodiment, the conductive surface layer is patterned to provide a plurality of discrete components. A layer of VSD material is located below the surface layer; the conductive elements electrically connect the layer of VSD material to ground. The surface layer includes a resistive material occupying a space between two or more of the discrete elements.

Voltage Switchable Dielectric (VSD) material

As used herein, a "voltage switchable material" or "VSD material" is a composition or combination of compositions: the composition has dielectric or non-conductive characteristics unless a field or voltage is applied to the material that exceeds the characteristic level of the material, at which point the material becomes conductive. Thus, if no voltage (or field) is applied to the VSD material that exceeds a characteristic level (e.g., provided by an ESD event), the material is dielectric; if a voltage (or field) is applied to the VSD material that exceeds a characteristic level (e.g., as provided by an ESD event), the material is switched into a conductive state. VSD material can be further described as non-linear resistive material. In many applications, the characteristic voltage of VSD material is within a range of values: the value exceeds the operating voltage level of the circuit or device by more than a few times. Such voltage levels may be levels of transient conditions, such as those resulting from electrostatic discharge, although embodiments may include the use of planned electrical events. In addition, in one or more embodiments, the material acts like an adhesive (i.e., it is non-conductive or dielectric) in the event that the voltage does not exceed the characteristic voltage.

Still further, in one embodiment, VSD material may be described as material that includes a binder partially mixed with conductor or semiconductor particles. In the event that the voltage does not exceed the characteristic voltage level, the material as a whole conforms to the dielectric characteristics of the adhesive. The material as a whole conforms to the conductive feature under application of a voltage exceeding the feature level.

According to embodiments described herein, the components of the VSD material may be homogeneously mixed into the binder or polymer matrix. In one embodiment, the mixture is dispersed on a nanometer scale, which means that: particles comprising conductive/semiconductive materials are nanoscale in at least one dimension (e.g., cross-section), and a large number of particles comprising all of the dispersed amounts in a volume are individually separated (so as not to aggregate or be close-packed together).

Still further, an electronic device can be provided with VSD material according to any of the embodiments described herein. These electronic devices may include substrate devices such as printed circuit boards, semiconductor packages, discrete devices, thin film electronic devices, Light Emitting Diodes (LEDs), Radio Frequency (RF) elements, and display devices.

Some compositions of VSD material function by incorporating conductive and/or semiconductive materials into the polymer binder in amounts just below the percolation (percolation). Bleeding may correspond to a statistically determined threshold by which a continuous conductive path exists when a relatively low voltage is applied. Other materials (insulating or semiconducting materials) may be added to better control the percolation threshold. Still further, some embodiments may construct VSD material formed from varistor particles dispersed in a polymer resin.

Figure 1 is an exemplary (not to scale) cross-sectional view of a layer or thickness of VSD material showing the composition of the VSD material according to various embodiments. As shown, the VSD material 100 includes a matrix binder 105 and various types of particulate components dispersed in the binder at various concentrations. The particle component of the VSD material may include metal particles 110, semiconductor particles 120, and/or high-aspect ratio (HAR) particles 130. It should be noted that the type of particle components included in the VSD composition can vary, depending on the desired electrical and physical characteristics of the VSD material. For example, some VSD compositions may include metallic particles 110, but not semiconductive particles 120 and/or HAR particles 130. Still further, other embodiments may not use conductive particles 110.

Examples of matrix binders 105 include polyethylene, silicone, acrylates, polyimides, polyurethanes, epoxies, polyamides, polycarbonates, polysulfones, polyketones, and copolymers, and/or mixtures thereof.

Examples of the conductive material 110 include metals such as copper, aluminum, nickel, silver, gold, titanium, stainless steel, chromium, other metal alloys, or conductive ceramics such as titanium diboride. Examples of the semiconductive material 120 include an organic semiconductor and an inorganic semiconductor. Some inorganic semiconductors include silicon carbide, boron nitride, aluminum nitride, nickel oxide, zinc sulfide, bismuth oxide, titanium dioxide, cerium oxide, bismuth oxide, tin oxide, indium tin oxide, antimony tin oxide, and iron oxide. The particular formulation and composition may be selected for the mechanical and electrical properties that are best suited for the particular application of the VSD material. HAR particles 130 may be organic (e.g., carbon nanotubes, graphene) or inorganic (e.g., nanowires or nanorods), and may be dispersed among other particles in various concentrations. More specific examples of HAR particles 130 may correspond to conductive or semiconductive inorganic particles, such as those provided by nanowires or certain types of nanorods. Materials for these particles include copper, nickel, gold, silver, cobalt, zinc oxide, tin oxide, silicon carbide, gallium arsenide, aluminum oxide, aluminum nitride, titanium dioxide, antimony, boron nitride, tin oxide, indium zinc oxide, bismuth oxide, cerium oxide, and antimony zinc oxide.

The dispersion of the various types of particles in the matrix 105 can make the VSD material 100 non-stratified and compositionally uniform while exhibiting the electrical characteristics of a voltage switchable dielectric material. Typically, the characteristic voltage of VSD material is measured in volts per length (e.g., every 5 mils), although other field measurement units may be used in place of volts. Thus, the voltage 108 applied across the boundary 102 of the layer of VSD material can switch the VSD material 100 into a conductive state if the characteristic voltage of the gap distance L is exceeded. In the conductive state, the matrix composite (including matrix binder 105 and particle components) conducts electrical charge (as shown by conductive paths 122) between the conductive particles 110, from one boundary of the VSD material to the other. In one or more embodiments, the VSD material has a characteristic voltage level that exceeds a characteristic voltage level of the working circuit. As described above, other characteristic field measurement units may be used.

Specific compositions and techniques for incorporating ORGANIC and/OR HAR PARTICLES into a composition of VSD MATERIAL are described in U.S. patent application No. 11/829,946 entitled "VOLTAGE SWITCHABLE DIELECTRIC MATERIAL HAVING switching OR SEMI-CONDUCTIVE ORGANIC anode MATERIAL" and U.S. patent application No. 11/829,948 entitled "VOLTAGE SWITCHABLE DIELECTRIC MATERIAL HAVING HIGH ASPECT proportional MATERIALs"; the above-mentioned patent applications are all incorporated by reference in their entirety.

In embodiments where the VSD material is formed from varistor particles dispersed in a polymer resin, metal oxide varistors may be formed using Bi, Cr, Co, Mn, W, and Sb. The composition may be formed by using a doped ZnO or TiO2 powder sintered at 800 ℃ to 1300 ℃, although other temperature ranges may be used. Sintering causes the electrical conductivity of the electrical particles to vary non-linearly with the applied electric field.

Core structure

Fig. 2A is a simplified and representative cross-sectional view of a core layer structure for forming a substrate (e.g., a Printed Circuit Board (PCB)) and a packaged device according to one or more embodiments. The core layer structure may correspond to a foil or plate of conductive material having a layer of VSD material inserted therein. The core layer structure as described herein may include a layer of conductive material, a layer of insulating material, and/or a layer of resistive material. In some embodiments, a cross-sectional portion of the thickness of the core layer structure includes a plurality of metal/conductive layers sandwiching the layer of VSD material. In other embodiments, the core layer structure may sandwich the VSD material between a conductive layer and a resistive layer, or between a conductive layer and an insulating layer, such as a prepreg (preprg). Either core layer structure may be further processed, such as by patterning (e.g., etching), to remove material from the layer and to enable integration of another material.

Fig. 1 illustrates an example of different types or formulations of VSD material that may be used in a core layer structure, such as those described in the various embodiments provided below (including fig. 2A-2E).

Referring to the embodiment of fig. 2A, a conductive foil 200 (or core layer structure) includes a first layer 210, a second layer 220, and a VSD layer 230 disposed directly therebetween. At least one of the first or second layers 210, 220 is formed of a conductive material, such as copper, silver, gold, or other metal. The VSD material may have a formulation according to the embodiment depicted in figure 1. In one embodiment, a layer of VSD material 230 is deposited (or sandwiched) between two layers of conductive material 110, 120. For example, VSD material 230 may be sandwiched between two layers of copper.

The conductive foil 200 may be subjected to different processes to form circuits and may be packaged or otherwise integrated into devices such as Printed Circuit Boards (PCBs) and packaged devices. Configurations such as those shown enable the ESD protection circuitry to function in the vertical plane of the thickness.

Because of the inherent properties of VSD material, VSD material is insulative in the absence of ESD or EOS conditions; in the presence of ESD or EOS conditions, the VSD layer is switched into a conductive state. In particular, in various embodiments, VSD material may be switched from an insulator to a conductor in the event that a voltage or field exceeds a threshold level (e.g., a clamp voltage). This property of VSD material enables VSD material to provide an integrated protective layer for substrates and packaged devices that include conductive foils (or core layer structures) as described in figure 2A.

Fig. 2B shows the core layer structure as described in fig. 2A, which is further processed and layered (as part of the build-up process) to form a printed circuit board or substrate device. In fig. 2B, the second conductive layer 220 is patterned and then optionally filled with one or more other layers of material. In the embodiment shown in fig. 2B, the second conductive layer 220 is patterned and filled with a layer of insulating material 232 (e.g., prepreg). The insulating material 232 enables the formation of an insulated electrical component. Alternatively or in addition, the resistive material may fill some or all of the gaps. Still further, some gaps formed when patterning the second conductive layer 220 may remain unfilled, especially when the second conductive layer 220 is a surface layer. As shown in the embodiment of fig. 2B, the first conductive layer 210 may be grounded 236. If an electrical event occurs, the layer of VSD material 230 can "switch" (enter a conductive state) and transfer the resulting current to ground 236. As described above, the direction in which the VSD layer 230 is switched to ground is along a vertical plane (shown by V).

Fig. 2C illustrates the use of additional material layers over the core layer structure. In the illustrated embodiment, an additional conductive layer 224 is provided over the insulating layer 232. Optionally, an additional layer of VSD material 234 is included, as well as another electrical layer 228. Vias 242 (with surface contacts 243) may electrically connect the VSD layers 230, 234 and conductive layers 210, 224 to ground 236 with each other. In the presence of an electrical event at the surface layer, the VSD layer, e.g., 234, can be switched vertically, with the event being grounded through the use of vias 242.

Fig. 2D illustrates the use of a resistive material in the core layer structure according to one embodiment. In the embodiment of fig. 2D, the conductive core layer structure 200 includes a first conductive layer 210, a VSD layer 230, and a second conductive layer 220 that includes elements (including elements 220A, 20B). Resistive material 252 overlies VSD material 230 to separate adjacent elements of the second conductive layer. Resistive material 252, in combination with VSD material 230, can enable significant electrical events to be grounded while providing electrical isolation for more sensitive electrical elements 220B. For example, in the presence of an electrical event at element 220A, the VSD layer 230 can switch to carry current vertically. The presence of resistive material 252 precludes large currents from being dispersed laterally to element 220B due to the event, since the path to ground 236 provides the least resistance.

Fig. 2E shows a core layer structure according to another embodiment, which includes an embedded resistive layer or element to electrically insulate the conductive element. In the cross-sectional view shown in fig. 2E, first conductive layer 210 is coated with insulating material 232. The layer of VSD material 230 is disposed over the insulating layer 234. The second conductive layer 220 is formed and patterned to provide trace elements. Resistive material (or layer) 252 may be patterned or selectively formed between some or all of the elements formed by second conductive layer 220. The vias 242 (and their surface contact elements 243) can electrically connect the VSD layer 230 and the conductive layer 210 to ground 236. As described above, the resistive material 252 electrically insulates the electrical element (220B). In the presence of an electrical event, the VSD layer 230 can switch so as to be electrically connected to the via 242. The path of least resistance through VSD material 230 and via 262 to ground 236 is vertical. Thus, by adding resistive elements to the path that would otherwise be available if the VSD material between electrical elements 220A and 220B were laterally switched, the resistive material insulates and protects adjacent electrical elements.

Figure 2F is a representative circuit diagram of how embedded resistive material may be used to insulate and further protect selected devices combined with a layer of VSD material, according to some embodiments. In particular, fig. 2F is a circuit diagram showing how ESD events (or other electrical events) are handled on the core layer structure shown by the embodiment of fig. 2D or fig. 2E. The embedded resistance is provided, for example, by resistive material 252 of fig. 2E, and is positioned to insulate the element to be protected (see 220B of fig. 2E). VSD material 230 switches with the event so that the event can be directed vertically to ground 236 (fig. 2E) because the vertical path has less resistance than the electrical path to element 220B.

Some of the many variations made to the core layer structure and construction described in fig. 2A-2E are described below. For embodiments described below or elsewhere, additional processing steps (such as described in fig. 2B-2E) may be performed to build up the substrate and circuit board device from the core layer structure. For example, the core layer structure described in various embodiments below or elsewhere may be further processed by: (i) patterning to form trace elements and insulating elements or regions; (ii) forming vias and microvias through the core layer structure to electrically connect trace elements or elements on the multiple layers (or to ground using VSD's); and/or (iii) multilayering to add additional layers of VSD material, conductive material, resistive material, or insulating material over the patterned or processed layers.

Fig. 3 is a representative cross-sectional view of a core layer structure according to another embodiment. In the illustrated embodiment, the core layer structure 300 corresponds to a foil or plate of conductive material having a layer of VSD material inserted therein. The core layer structure 300 may be replaced by any of the embodiments described above or elsewhere.

More specifically, the core layer structure 300 utilizes the first conductive material 310 (copper) as the plane that initially receives the layer of VSD material 320. A second conductive material (e.g., silver) 330 is provided on the VSD material 320 to form a composite structure. A second layer of conductive material 330 is formed, deposited, or otherwise provided on the VSD layer 320 to form a pair of distinct conductive layers within the foil 300.

There may be different techniques for providing the first or second conductive layers 310, 330 to the layer of VSD material 320. For example, in one embodiment, the VSD layer 320 is pressed between metal sheets (e.g., two copper sheets). In another embodiment, the VSD material 320 is cured simultaneously between the two conductive layers 310, 330 (or between different types of conductive layers 112, 202).

The embodiment of fig. 3 shows that a different type of conductive material is used to form the core layer structure, and this embodiment can be applied to other embodiments described herein. For example, the core layer structures shown in the embodiments of fig. 2B-2E may include different types of conductive materials on different layers of the core layer structure.

Formation of core layer Structure

Still further, the embodiments of fig. 4A-4C illustrate a method for forming a core layer structure according to one or more embodiments. In fig. 4A, a first layer 410 of a core layer structure is formed. The first layer 410 may be formed of a conductive material, such as copper or silver.

In fig. 4B, a second layer 420 including VSD material is formed on the first layer 410. In the embodiment provided, the VSD material is formed directly on the first layer 410 so as to contact the first layer. There are many methods and techniques for forming VSD material 420 on a first material. In one embodiment, the layer of VSD material 420 is deposited in liquid form on the first layer 410 and then cured in place. In another embodiment, the layer of VSD material 420 is B-staged on the first layer 410. The layer of VSD material 420 on the first conductive layer 410 provides an intermediate stage in the formation of the core.

Fig. 4C shows that after an intermediate stage of bonding the first and second layers 410, 420 together, a third conductive layer 430 is formed or deposited over the combination of the first layer 410 and the second layer 420. There are many methods and techniques for forming the third layer 430 of conductive material on the intermediate structure. As described below, for example, in some embodiments, the third layer 430 is formed or deposited by a process including electrolytic plating, electroless plating (electro-less plating). Thus, both the first and third layers 410, 430 can be formed of the same conductive material with the VSD material sandwiched therebetween. Still further, a third layer 430 of conductive material may be coated over the intermediate structure. For example, the third layer 430 may be comprised of a conductive ink that may be applied directly to the intermediate structure.

Alternatively, one of the first or third layers 410, 430 is formed of a non-conductive or resistive material, as described in one or more of the embodiments below. Still further, one of the first or third layers may be formed of a conductive material and separated from the VSD material of the second layer 420 by a resistive or insulating material (e.g., prepreg).

Forming a conductive layer on a VSD

Fig. 5A-5C illustrate a method for forming a core layer structure, such as described in various embodiments herein. More specifically, fig. 5A to 5C show embodiments in which: (i) forming an intermediate structure comprising a first layer of conductive material and VSD material; and (ii) forming a second conductive layer on the layer of VSD material of the intermediate structure. According to some embodiments, the second conductive layer is formed on the intermediate structure, for example, by an electroplated metal formation process. Embodiments such as those depicted in fig. 5A-5C may be used to produce core layer structures as described in the above embodiments (including fig. 2A-2F).

In fig. 5A, an intermediate structure 510 is formed. The intermediate structure includes a layer of VSD material 530 formed on the conductive layer 520. The intermediate structure 510 is connected to the voltage source 502. The voltage from voltage source 502 is used to switch the layer of VSD material 530 into a conductive state. The intermediate structure 510 is processed in an electrolytic solution 540 (fig. 5B) while the layer of VSD material is switched into a conductive state. A second conductive layer 550 begins to be formed over the VSD material. The composition of the second conductive layer may be selected in the electrolytic solution 540. In this way, the layer of VSD material 530 is processed in solution 540 such that a second conductive layer 550 is formed on top of the layer of VSD material (fig. 5C). The final formation completes the formation of the core layer structure 500.

As described elsewhere, in one embodiment, the metal in solution 540 may be different from the metal in first conductive layer 520. This results in the core layer structure 500 having a first conductive layer 510 that is different from the second conductive layer 550.

As an alternative to an electroplating process, the layer of VSD material 520 may be switched to a conductive state (using a voltage applied by the voltage source 502) and subjected to an electroless plating process for metal formation.

As another alternative or variation, the same metal formation or deposition process as described for second conductive layer 550 (see fig. 5C) may be used to form first conductive layer 520. For example, the first conductive layer 520 can be formed by subjecting the VSD material 530 to an electrolytic solution 540 that simultaneously forms the first and second conductive layers 520, 550.

As an alternative to the embodiment, the electrolytic plating process may be implemented as a double reel (reel-to-reel) process.

Seed layer embodiments

Fig. 6A and 6B illustrate another embodiment that uses a seed layer to form one of the conductive layers of the core layer described herein. As depicted, the seed layer 602 is used in the process of forming one of the conductive layers of the core layer structure 600. Referring to the embodiment of fig. 6A, a seed layer 602 is formed on an intermediate structure 600 that includes a first conductive layer 610 and a layer of VSD material 620. More specifically, seed layer 602 is formed on VSD layer 620. Seed layer 602 serves as an alternative to the following methods: the VSD material is "switched" to plate the second conductive layer 630 over the intermediate structure. Seed layer 602 can be provided as a thin layer of material deposited or otherwise formed on layer of VSD material 620 to enable subsequent formation of second conductive layer 620 using, for example, an electroless or electrolytic plating process. In one embodiment, the seed layer 602 is formed by vacuum deposition after the VSD layer 620 is formed on the first conductive layer 610. For example, the VSD layer 620 can be deposited in liquid form on the first conductive layer 610 and then dried. Next, a vacuum deposition process may be used to form seed layer 602. Next, a second conductive layer 630 is formed by subjecting the seed layer 602 to an electroplating or electroless plating process. As an alternative to vacuum deposition, other techniques may be used to form seed layer 602, such as Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), sputtering, or Atomic Layer Deposition (ALD). In an alternative embodiment or in variation, seed layer 602 may be formed by a process comprising: (i) capturing particles of seed layer 602 in place (i.e., on cured layer of VSD material 620); (ii) the seed layer particles are deposited by precipitation.

In some embodiments, the seed layer 602 is conductive, such as a metal. Alternatively, seed layer 602 may be semi-conductive for some embodiments. For example, semiconductive particles can be captured on the cured VSD material layer 102 to form a seed layer 602.

Still further, seed layer 602 may be formed from a conductive polymer or deposit. The polymer may be conductive itself or may be loaded with metal particles and/or other conductive elements to make it conductive.

Variants

In some embodiments, varistor particles without a binder (i.e., without a binder) formulation may constitute one or more of the layers of the core layer structure as an alternative to the VSD material described in figure 1. In particular, varistor materials may be selected that have an inherent ability to "switch" to a conductive state in the event of a voltage, for example, caused by an ESD or EOS event.

With respect to some embodiments described (e.g., the core layer structure of fig. 2A-2E or the core layer structure formed using the method of fig. 5A-5C), an electrolytic process may be performed to add thickness to one or both of the conductive layers forming the core layer structure. For example, after forming or providing an initial thickness on the layer of VSD material, an electrolytic process can be performed to increase the thickness of the second conductive layer.

For some embodiments, one or both of the conductive layers comprising the core layer structure may be replaced with a semiconductor material. Still further, one layer may be replaced by a resistive material.

As another embodiment, an adhesion promoter may be used at the interfacial surface of the conductive material layer.

Conclusion

Although illustrative embodiments of the present invention have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments. As such, many modifications and variations will be apparent to practitioners skilled in the art. It is therefore intended that the scope of the invention be defined by the following claims and their equivalents. In addition, it is contemplated that a particular feature described either individually or as an integral part of an embodiment may be combined with other individually described features or integral parts of other embodiments, even if the other features and embodiments do not mention the particular feature. Thus, failure to describe such a combination should not preclude the inventors from claiming such a combination.

Claims (22)

1. A core layer structure for a substrate and a packaged device, the core layer structure comprising:

a first layer;

a second layer bonded to the first layer;

wherein at least one of the first layer or the second layer comprises a conductive material;

a layer of Voltage Switchable Dielectric (VSD) material disposed between the first layer and the second layer.

2. The core layer structure of claim 1, wherein the first layer and the second layer are each formed of the same conductive material.

3. The core layer structure of claim 1, wherein the layer of VSD material is disposed in contact with the at least one of the first layer or the second layer, the first layer or the second layer including a conductive material.

4. The core layer structure of claim 1, wherein the first layer comprises a conductive material and the second layer comprises an insulating material.

5. The core layer structure of claim 1, wherein the first layer comprises a conductive material and the second layer comprises a resistive material.

6. The core layer structure of claim 1, wherein the first layer and the second layer each comprise a conductive material, wherein the VSD material is disposed in contact with one of the first layer and the second layer, and wherein the core layer structure comprises one or more additional layers of a conductive material, an insulating material, or a resistive material.

7. The core layer structure of claim 1, wherein the VSD material comprises a combination of conductive and/or semiconductive particles dispersed in a binder.

8. The core layer structure of claim 1, wherein the VSD material comprises varistor particles.

9. The core layer structure of claim 1, wherein the VSD material comprises varistor particles without a binder.

10. A core layer structure for a substrate and a packaged device, the core layer structure comprising:

a plurality of layers, the plurality of layers comprising:

a first layer comprising a conductive material;

a layer of Voltage Switchable Dielectric (VSD) material formed on the first layer;

a second layer formed on the layer of VSD material, the second layer including one of a conductive material, an insulating material, or a resistive material.

11. The core layer structure of claim 10, further comprising a third layer formed on the second layer, the third layer comprising one of a conductive material, an insulating material, or a resistive material.

12. The core layer structure of claim 9, wherein at least one of the second layer or the third layer is patterned.

13. A method for forming a core layer structure, the method comprising the steps of:

creating an intermediate structure comprising (i) a first layer and (ii) a layer of Voltage Switchable Dielectric (VSD) material formed on the first layer; and

a second layer is formed on the intermediate structure.

14. The method of claim 13, wherein at least one of the first layer or the second layer is comprised of an electrically conductive material.

15. The method of claim 13, wherein at least the first layer is comprised of a conductive material, and wherein creating an intermediate structure comprises B-staging the layer of VSD material on the first layer.

16. The method of claim 13, wherein generating an intermediate structure comprises: coating the layer of VSD material on the first layer.

17. The method of claim 13, wherein forming a second layer comprises: forming a thickness of conductive material corresponding to the second layer by subjecting the intermediate structure to an electrolytic plating process.

18. The method of claim 17, wherein forming the thickness comprises: applying a sufficient voltage to the intermediate structure to switch the layer of VSD material to a conductive state, wherein the voltage is applied while the intermediate structure is immersed in an electrolytic solution.

19. The method of claim 17, wherein forming a conductive material thickness comprises: using a seed layer to form the thickness when subjecting the intermediate structure to the electrolytic plating process.

20. A core layer structure for a substrate and a packaged device, the core layer structure comprising:

a surface layer comprising a conductive material, the conductive material being patterned to provide a plurality of discrete elements;

a layer of Voltage Switchable Dielectric (VSD) material located below the surface layer;

a conductive element electrically connecting the layer of VSD material to ground;

wherein the surface layer comprises a resistive material that occupies a space between two or more of the discrete elements.

21. The core layer structure of claim 20, wherein the conductive element corresponds to a via that extends from at least the layer of VSD material to ground via a vertical path through a thickness of the core layer structure.

22. The core layer structure of claim 21, further comprising a layer of insulating material disposed above and/or below the layer of VSD material.