HK1006877B - Numerical insulation tester for power system - Google Patents

Description

The invention relates to an insulation controller comprising: an injection circuit of an alternating reference signal between the network and the ground,an electronic detection circuit providing a measurement signal image of the network isolation,the said isolation corresponding to an impedance Zd formed by a leak resistor Rf electrically connected in parallel on a Cf parasite capacitor,the capacity of which depends on the characteristics of the network,the means of discriminating between the resistive and capacitive components of the measurement signal,and the means of calculating and signalling the modules of these components to visualize the values of the Rf leak resistor and the Cf parasite capacitor on display and alarm means.

FR-A 2.616.228 describes an isolation controller comprising a generator that injects a low frequency alternating reference voltage into a network, and an analog synchronous detector having a pair of static inverters that process the resistive and capacitive components of the measuring signal proportional to the isolation impedance. A converter is connected to the generator to deliver two control signals in square format to drive the inverters, one of the control signals being in phase with the alternating reference signal injected into the network by a generator. The accuracy of the controller depends on the phase stability of the measuring chain. Using an analog generator with a synchronous distortor may cause the phase characterization rate of the electronic components to vary, depending on the characteristics of the measuring components that are introduced.

The purpose of the invention is to improve the measurement accuracy of an insulation controller.

The insulation control according to the invention is characterised by the insulation control having: a digital signal processor P1 designed to synthesize in real time a sine wave per table stored in memory and to send the numerical values of this sine wave to an analogue/digital CNA converter in an injection chain to generate the reference alternate signal, a supply chain with a low-pass analogue filter connected via a blocking sampling circuit to an analogue/digital CAN converter delivering a filtered digital measurement signal which is processed by synchronous demodulation in said processor P1 and then transmitted to a microcontroller P2, a dual supply chain measurement circuit comprising a first supply circuit delivering a first S1 signal representing the voltage injected into the network, and a second supply circuit delivering a second S2 signal from the first leakage current function flowing through the impedance Zd, and a switching medium controlled by the P1 processor to inject the first or second signal into the supply chain.

The frequency of the alternating reference signal injected into the network by the injection chain is a sub-multiple of the network frequency. $\text{sinus (A+b) = sin A cos b + sin b . cos A,}$ - What? where the first parameter A varies from 0 to 90 degrees in predetermined steps m1 equal to 90/n, and the second parameter b varies from 0 to m1 degrees in predetermined steps m2 equal to m1/n.

The processor's digital generation of the alternating reference signal allows for a very low and stable phase distortion rate. The measurement chain then introduces a minimum phase error into the processor for synchronous demodulation processing. This phase stability favors the controller's accuracy.

The acquisition chain cooperates with a dual measuring circuit delivering a first signal S1 and a second signal S2 representing, respectively, the voltage injected into the network, and the leakage current flowing through the impedance Zd, and is equipped with a switch formed by an analogue multiplexer to alternately take into account the first signal S1 from a resistance bridge R1-R2 of the first measuring circuit connected to the network, and the second signal S2 taken from the terminals of a measuring resistance R3 of the second measuring circuit connected to the earth, the switching override control being controlled by the signal processor P1.

After numerical filtering and synchronous demodulation processing, the processor transmits the data to a microcontroller which calculates in time-deferred the values of the leakage resistance, the parasite capacitor, and the ground resistance.

The P2 microcontroller is associated with: a control keypad for data entry and scrolling of the display,a first alphanumeric display for displaying the values of the leak resistance Rf, the parasite capacitor Cf, and the ground resistance Rt,a second bar graph display for continuous indication of the level of isolation from alarm and pre-alarm thresholds,an alarm device with powered signal relays in case of exceeding these thresholds,and a communication interface with a bus for transmitting or receiving data from an external transmitter/receiver device.

A secret code digital seal is programmed inside the P2 microcontroller, and the keyboard only allows parameters to be changed if the code entered is compliant.

Other advantages and characteristics will be more clearly seen in the following description of a method of realization of the invention, given as a non-limiting example and shown in the attached drawing, in which: Figure 1 is a synoptic diagram of the numerical insulation controller according to the invention;Figure 2 is a partial view of Figure 1, representing the equivalent diagram of the injection filter and the double measuring circuit.

In Figure 1, a digital isolation controller 10 is formed by the combination of three functional blocks 12, 14, 16 arranged to form an injection circuit of an alternating low frequency reference signal between the network and the earth, and a detection and processing circuit providing an image signal of the network isolation.

The network 22 shown in Figure 1 is an isolated neutral three-phase alternating network (IT neutral mode), but it is clear that the network configuration may be different (TN neutral mode or TT). In the case of the IT regime in Figure 1, the injection terminal 18 is connected either to the neutral of the medium-voltage/low-voltage power transformer 24 or directly to one of the phase conductors (dotted connection). Network 22 supplies at least one R receiver located opposite the power transformer.

The first functional block 12 (see Figures 1 and 2) consists of an injection filter 26 with a plug circuit 28 tuned to a network frequency. A head capacitor 30 inserted between the plug circuit 28 and the terminal 18 is intended to cut off the continuous component of the AC 22 network, or to cut off the DC if used on a continuous network. The plug circuit 28 consists of the parallel placement of a capacitor 32, a self 34 and a resistor 36, the function of the latter being to avoid the phenomenon of ferro-resonance.

To calculate the level of network isolation, it is necessary to know the value of the injected voltage and the current flowing in the fault impedance Zd between the network and the ground.

The first voltage measuring circuit 38 including a resistor bridge (R1-R2) is connected to the injection filter 26 in parallel to the mains side for measuring the injected voltage. A capacitor 40 series allows the continuous component of the mains 22 to be cut off, and a capacitor 42 in parallel to the resistor R2 attenuates the alternating component of the mains. The resistor R2 is connected to the load, and the image of the injected voltage is taken at the interconnection point of the resistors of the resistor bridge R1-R2.

A measuring resistor R3 of a second voltage measuring circuit 44 is connected between the terminal 20 and the mass, so that it is in series with the fault impedance Zd of the network.

The principle of calculating the insulation level follows from the double measurement of the output signals S1 and S2 of the first and second voltage measurement circuits 38.44 of the first block 12:

If the voltage U measured at the resistance limits R2 is the image of the voltage injected, the actual voltage U1 injected into this network is given approximately by the relation: $\text{(1) U1 = U (R1+R2/R2)}$ - What? The resistance of the capacitors is not affected by the resistance of the capacitors 40, 42.

On the other hand, if V is the voltage measured at the terminals of the resistor R3, the current Id flowing in the fault is given by the relation: $\text{(2) Id = V/R3}$

The voltage U2 at the terminals of the fault impedance Zd has the value U2 = U1-V. The fault impedance Zd is represented by the relation:

It is noted that the fault impedance Zd depends on the values of the resistors R1, R2, R3 of the two measuring circuits 38, 44, and the values of the voltages U and V, which are proportional respectively to the voltage injected into the network and to the leakage current Id flowing in the fault impedance Zd.

Since all these values are known by design and measurement, the determination of the fault impedance Zd is possible without the characteristics of the injection filter being involved.26 The process of double measurement of the U and V voltages for the calculation of the impedance Zd makes it possible to release the manufacturing tolerances of the components, in particular the self 34 and the capacitors 30, 32 of the injection filter.26

The second functional block 14 (Fig. 1) has a P1 signal processor associated with:an injection chain 48 connected to the plug circuit 28;an acquisition chain 50 of the output signals S1 and S2 of the first and second measurement circuits 38, 44 representing respectively the values of the voltage injected into the network, and the fault current in the impedance Zd;a communication link 53 with a microcontroller P2.

The P1 signal processor is a very fast specific digital microprocessor that allows multiplication and division of 16-bit numbers in one instruction.

The switch command is generated by the P1 processor and sent to the switch 52 by a link driver. The output of the switch 52 is connected to a first variable gain A1 amplifier, which amplifies the S1 or S2 signal. The resulting signal then passes through a 56-bass analog filter to avoid spectrum folding during scanning. The filtered signal is sent through a sample-blocker circuit. The 58s are then converted by means of an analog/digital converter. The sample-blocker converter is unlocked by the P1 processor and the data generated by the P1 signal is sent to the P1 processor.

Injection chain 48 has a CNA digital/analog converter connected to the P1 signal processor and a second A2 amplifier inserted between the CNA converter and the plug circuit 28. Injection chain 48 of second block 14 uses some of the resources of the P1 signal processor to digitally synthesize the low frequency injected sinusoidal signal in real time.

The P1 processor generates the sine wave signal injected at 1024 points. Since this is a numerical component, the generation of the sine wave is performed by calculation using the following formula: $\text{sinus (A+b) = sinus (A)cos(b)+sin(b)cos(A)}$

Err1:Expecting ',' delimiter: line 1 column 83 (char 82)

Four tables of 16 data are stored in a memory of the P1 processor: A table of sines (A) a table of cosines (A) a table of sines (B) a table of cosines (B)

To generate a sinusoid, we first make A = 0 and we vary b from 0 to 5.625, then A = 5.625 and we vary b from 0 to 5.625 then A = 11.25 and b varies from 0 to 5.625 etc. The generation of 0 to 90 degrees of the sinusoid is therefore made of 256 points.

Above 90 degrees, simply walk the tables in reverse to obtain the sinusoid decrease. When one exceeds 180 degrees, simply reverse the result sign by following the same method (with change of table reading direction to 270 degrees). Note that only a quarter of a sine wave is in memory, which results in a saving of memory space in the P1 processor.

The synchronous demodulation processing in the P1 processor also requires the cosine of the injected signal. $\text{cosinus (A+b) = cos(A)cos(b)-sin(b)sin(A)}$

We use the same tables.

The resulting numerical values of the sinusoid are sent to the digital/analog converter CNA which converts them into an analog voltage. The sine function is used because it starts at 0 at t = 0. The amplifier A2 provides the current needed for the injection over the network, after passing through the injection filter 28.

After the 56-pass filter has previously eliminated HF parasite signals and noise, especially frequencies above 100 Hz, which could be brought back into the useful band of the injection frequency after sampling, the P1 signal processor performs a first digital filtering by cutting the spectrum at 264 Hz and then decimating the samples by taking one sample out of eight. This is equivalent to sampling at a frequency eight times lower. The P1 processor then performs a digital filtering, eliminating the 50 Hz frequency on the digitized signals images of the injected voltage and leakage current.

The P1 signal processor then performs synchronous demodulation, which is the process of multiplying the digital signal filtered by the sine of the phase shift, and then integrating it to obtain the actual portion of the output signal S1 or S2.

The synchronous demodulation has the particularity of rejecting all harmonic frequencies of the injection signal frequency. For this reason, the injection frequency will be a sub-multiple of 50 Hz, notably 10, 5, 2.5 or 1 Hz. To improve measurement accuracy, it is necessary to work at low frequency.

The digital generation of the injection signal by the injection chain 48 provides a very low and very stable phase distortion rate, which benefits from the synchronous demodulation principle implemented in the P1 processor, which requires a minimum of phase error in the acquisition chain 50.

It is also noted that the ground resistance Rt (shown in dots in Figure 1) electrically inserted between the fault impedance Zd and the terminal 20 of the insulation controller 10 affects the accuracy of the insulation measurement, because the ground resistance Rt is in series with the leakage resistance Rf. Intermittent operation at two different frequencies, e.g. 10 Hz and 5 Hz of the signal processor P1 will allow the value of the ground resistance Rt in the microcontroller P2 to be calculated.

The gain order for the A1 amplifier in the supply chain 50 shall be as follows:

The signal processor P1 calculates the square of the filtered digital signal module S1 or S2 corresponding to the injected voltage and insulation current. If this module exceeds Vmax/2 (Vmax being for example 10 volts), there is a risk of saturation at the level of the amplifier A1. The signal processor P1 then adjusts the gain of the amplifier to the gain immediately below. If this module is less than Vmax/4, the processor P1 adjusts the gain of the amplifier A1 to the gain immediately above. The result is that the signal received by the processor P1 always has the maximum dynamics.

At the end of each measurement sequence corresponding to an amplitude setting, a digital filter stabilization time and a measurement time, the P1 processor sends to the P2 microcontroller four types of measurement for each working frequency of 10 Hz and 5 Hz: The actual part of the current signal and the associated imaginary part of the current signal gain and the associated imaginary part of the voltage signal gain.

In the third functional block 16, the P2 microcontroller uses data transmitted by the P1 signal processor to calculate the values of the Rf isolation resistor, the Cf capacity of the network and the Rt earth resistor. It manages a keyboard 61, the 62, 64 displays, the controls of an alarm device 66 and a communication interface 68 with a data transmission bus 69. The P2 microcontroller, thanks to a backup power supply from memory area 70, allows to remember fugitive defects and to save the configuration of the device in case of power failure. The P2 microcontroller uses the previous relation (4) to calculate the R, R, and C values. The P2 microcontroller works at a slower rate and is processed faster than the P2 microcontroller which works by switching the signal back to the input of the P1 microcontroller each time the signal arrives. a bar-graph display device 64

Err1:Expecting ',' delimiter: line 1 column 231 (char 230)

The bar-graph 64 display continuously indicates the insulation level relative to an alarm threshold and a pre-alarm threshold. A green color indicates insulation above the pre-alarm threshold (high insulation threshold), and a yellow color indicates insulation below the pre-alarm threshold but above the alarm threshold. A red color indicates insulation below the pre-alarm and pre-alarm thresholds. The lit segment situates the insulation relative to the thresholds.

The keyboard 61 has a limited number of non-specific keys: the bottom line of the alphanumeric display of the display 62 defines the function of each key.

The alarm system 66 has 72 relays which are controlled when the thresholds are passed, one of 72 relays which is controlled when the pre-alarm threshold is passed and two other relays 72 which are controlled when the alarm threshold is passed.

The communication interface 68 with bus 69 allows data to be transmitted or received from an external transmitter/receiver device. The data transmitted may be the value of the isolation resistance, line capacity, value of the fugitive defects, etc. The data received are changes in threshold values, requests to send information, etc.

A controller 10 test device has a test circuit 73 with a test resistance R4 at one end connected to terminal 20 and the other end capable of cooperating with a bistable contact 74 of a control relay 76. When the relay 76 is not excited, contact 74 opens the test circuit 73 but closes the injection filter circuit 26, allowing the BF sine wave signal produced by the P1 signal processor to be injected into the network.

The test mode is performed by pressing the test key on keyboard 61 causing the driver 78 of the microcontroller P2 to issue an excitation order to the relay 76. The contact 74 is then switched to the position shown in dotted lines, so as to close the test circuit 73 and to prohibit the injection of the sinusoidal BF signal into the network. The insertion of the test resistor R4 simulates an insulation defect appearing at the input of the controller 10 between terminals 18, 20. This defect is taken into account by the acquisition chain 50 and the processor of P1, and is then displayed on the signal display by the controller P2.

A secret code digital seal is programmed inside the P2 microcontroller, and a code key is accessed on the 61 keyboard to allow new parameters to be entered if the code is compliant.

Claims (10)

1. An isolation monitor comprising :

   - a circuit for input of a reference AC signal between the power system and earth,

   - an electronic detection circuit supplying a measurement signal which is the image of the power system isolation, said isolation corresponding to an impedance Zd formed by a leakage resistance Rf electrically connected in parallel with a stray capacitor Cf, the capacitance of which depends on the characteristics of the power system,

   - means for discriminating the resistive and capacitive components of the measurement signal,

   - and means for computing and indicating the modules of said components to display the values of the leakage resistance Rf and of the stray capacitor Cf on display and alarm means, characterized in that the isolation monitor (10) comprises :

   - a signal processor P1 with digital processing designed to synthesize in real time a sine wave by table stored in a memory, and to send the digital values of this sine wave to a digital-to-analog converter CNA of an input channel (48) to generate the reference AC signal,

   - an acquisition channel (50) having a low-pass analog filter (56) connected by means of a sample-and-hold circuit (58) to an analog-to-digital converter CAN delivering a filtered digital measurement signal which is processed by synchronous demodulation in said processor P1, then transmitted to a microcontroller P2,

   - a dual measuring circuit of said acquisition channel comprising a first measuring circuit (38) delivering a first signal S1 representing the voltage input to the power system, and a second measuring circuit (44) supplying a second signal S2 representative of the leakage current flowing in the impedance Zd,

   - and a switching means (52) controlled by the processor P1 to input the first or the second signal to the acquisition channel (50).
2. The isolation monitor according to claim 1, characterized in that the frequency of the reference AC signal input to the power system by the input channel (48) is a sub-multiple of the power system frequency, and that the processor P1 synthesizes the sine wave by points using the formula : $\text{sin (A + b) = sin (A) cos (b) + sin (b) cos (A),}$ in which the first parameter A is scaled from 0 to 90 degrees in predetermined steps m1 equal to 90/n, and the second parameter b is scaled from 0 to m1 degrees in predetermined steps m2 equal to m1/n.
3. The isolation monitor according to claim 1 or 2, characterized in that the output of the digital-to-analog converter CNA is connected by means of a first amplifier A2 to an input filter (26) with a trap circuit (28) tuned to the frequency of the power system.
4. The isolation monitor according to claim 3, characterized in that the switching means (52) is formed by an analog multiplexer designed to accept alternately the first signal S1 from a resistance bridge R1-R2 of the first measurement circuit (38) connected to the power system, and the second signal S2 taken at the terminals of a measurement resistor R3 of the earthed second measurement circuit (44), switching of the switching means (52) being connected to the signal processor P1.
5. The isolation monitor according to claim 4, characterized in that a second variable gain amplifier A1 is connected between the multiplexer of the switching means (52) and the analog filter (56) to amplify said first and second signals S1 and S2, adjustment of the gain of the second amplifier A1 being performed by the processor P1 according to the value of the module of the filtered digital signal at the output of the analog-to-digital converter CAN.
6. The isolation monitor according to claim 5, characterized in that the processor P1 performs digital filtering eliminating the stray frequencies in the digitalized signals which are images of the voltage input and of the leakage current, followed by processing by synchronous demodulation consisting in multiplying said digitalized signals by the sine and cosine of the phase shift, and that at the end of each measurement and integration sequence, the processor P1 sends data concerning the real and imaginary parts of the voltage input and leakage current signals to the microcontroller P2 via a link (53).
7. The isolation monitor according to claim 6, characterized in that the microcontroller P2 computes in deferred time the values of the leakase resistance Rf, the stray capacitor Cf, and the earth resistance Rt located between the impedance Zd and the measurement resistor R3, following intermittent operation of the processor P1 at two different frequencies.
8. The isolation monitor according to claim 7, characterized in that the microcontroller P2 is associated with:

   - a keyboard (61) with control keys to enter the data and scroll the display,

   - a first alphanumeric read-out (62) to display the values of the leakage resistance Rf, the stray capacitor Cf, and the earth resistance Rt,

   - a second bar graph read-out (64) to give permanent indication of the isolation level with respect to alarm and pre-alarm thresholds,

   - an alarm device (66) with signalling relays supplied in the event of said thresholds being exceeded,

   - and a communication interface (68) with a bus (69) to transmit or receive data from an external transceiver device.
9. The isolation monitor according to claim 8, characterized in that digital sealing with a secret code is programmed inside the microcontroller P2, and that a code key is accessible on the keyboard (61) to enable the parameters to be modified if the code complies.
10. The isolation monitor according to claim 8 or 9, characterized in- that the keyboard (61) comprises a test key designed to send an excitation order via the microcontroller P2 to a control relay (76) arranged to connect a test resistor R4, and to disconnect the input filter (26) from the power system.