HK1099614A1 - Method and apparatus for processing spread spectrum signals, and receiver for receiving spread spectrum signals - Google Patents

Abstract

This invention provides a method and a device for applying separate integration to realize parallel correlators in frequency-spread communication, in which, a device for processing frequency-spread signals includes an IF signal pre-process unit and multiple parallel separate integrators, the IF signal pre-process unit can generate a pre-integrated result based on the input signal and local reference signals in a preset rate to divide it into multiple groups and each of which includes a pre-integrated result with preset numbers,the multiple parallel separate integrators communicate with said IF signal pre-process unit and each one can receive multiple sets of results continuously and operates the pre-integrated results of the preset numbers of the set relatively with multiple segments of offset false random noise codes so as to get multiple partial relative operation results till to receive the results of preset number of the next group.

Description

Method and apparatus for processing spread spectrum signal and receiver for receiving spread spectrum signal

Technical Field

The present invention relates to spread spectrum digital receivers, and more particularly to the implementation of parallel correlators in Global Positioning System (GPS) receivers.

Background

Spread spectrum communication has its advantages in communication applications where high reliability is required in noisy environments. According to shannon's theorem, the need for high signal-to-noise ratios can be reduced by broadening the spectrum, which indicates that weak signals can be transmitted and detected using spread spectrum communication techniques. To spread the spectrum, high-speed pseudorandom noise codes (PRNs) are often used to modulate a narrowband signal to produce a wideband signal. The wideband signal is modulated by an information data stream to carry data. The information data rate is typically much lower than the symbol (chip) rate of the PRN code, and the data is typically synchronized with the edges of the chip signal.

Information data from a spread spectrum signal, such as a GPS signal, may be searched by multiplying a locally generated carrier signal to convert the received signal to a lower frequency signal. The local carrier signal may be generated by a suitably tuned local oscillator. If the frequency and phase of the local carrier signal are the same as the received original narrowband carrier, the multiplier output signal obtained by multiplying the received signal and the local carrier signal is the bipolar wideband data stream. The bipolar wideband data stream is the product of a bipolar PRN code and an information data sequence. The received P RN code is then removed by multiplying the wideband data by a locally generated PRN code that is in timing alignment with the received PRN code. This enables data information to be obtained. The above is the signal despreading process.

The GPS signals are spread spectrum signals transmitted by GPS satellites at the L1, L2, and L5 frequencies. Current commercial GPS receivers typically use the L1 frequency (1575.42 MHZ). Several signals transmitted on the L1 carrier are: coarse acquisition code (C/a code), P code, and navigation data. Detailed data of the satellite orbit is contained in the navigation data. C/a codes are mainly used for positioning purposes in civilian receivers. The C/a code is used to determine a pseudorange (the apparent distance of the satellite), which is then used by the GPS receiver to determine the position of the satellite. The C/A code is one of the PRN codes, and its function has been described previously. The radio frequency signal after C/A code coding becomes a spread spectrum signal. Each satellite has a unique C/a code and the C/a code is iteratively cycled. The C/a code is a sequence of 0's and 1's (binary). Each 0 or 1 is considered to be a "chip". The C/a code is 1023 chips long and is transmitted at a rate of 1.023 mega chips per second, e.g., one cycle of the C/a code lasts one thousandth of a second. Each chip can also be considered to have two states: +1 and-1.

One set of data collected by a GPS receiver contains signals from several satellites. Signals from different satellites propagate through different frequency channels. Typically, a GPS receiver processes signals from several frequency channels simultaneously. Each signal has a C/a code with a different start time and a different amount of doppler shift. Thus, to search for a certain satellite signal, a GPS receiver typically performs a two-dimensional search, searching for each C/a code at a different starting time at each possible frequency. The "different start times" here can be understood as the result of the C/a code phase delay. In a GPS receiver, an acquisition method is used to search for the starting point of the C/a code and the frequency of the carrier, in particular the doppler shift of the signal. To search for the presence of a signal at a particular frequency point and a particular C/a code delay, the GPS receiver is tuned to that frequency and the input signal is correlated with a known PRN code, the amount of delay of which is related to the time of arrival of the input signal. If no signal is searched, the search continues for the C/a code with the next possible delay. Generally, each possible delay of the C/A code is obtained by shifting the 1/2 chips of the C/A code. Since the C/a code consists of 1023 chips, searching for a fixed frequency requires 2046 possible delays to be detected. After all possible delays have been detected, the search continues for the next possible frequency. The speed of the acquisition process is very important since thousands of frequencies and code delays are searched.

Fig. 1 illustrates a block diagram of a prior art GPS receiver 100. In general, a GPS receiver includes two parts: an RF (radio frequency) front end module 101 and a baseband signal processing module 103. GPS signals from GPS satellites are received by antenna 102, and the received signal (also referred to as an input signal) converts the GPS signals (radio frequency signals) into signals having a desired output frequency via RF tuner 104 and frequency synthesizer 105. Then, the analog/digital converter (ADC)106 digitizes the converted signal at a predetermined sampling frequency. The converted and digitized signal is considered an Intermediate Frequency (IF) signal. The intermediate frequency signal is then passed to a baseband signal processing module 103 comprising several signal processing stages. The IF signal is passed to the acquisition module 110. as previously described, a doppler shift search and a C/a code phase shift search are performed in the acquisition module 110. In the acquisition stage, the IF signal is integrated by performing a correlation operation based on the IF signal and the C/A code. The tracking module 112 tracks the GPS signal through the IF signal using the carrier tracking loop and the code tracking loop, thereby acquiring navigation data contained in the GPS signal. Next, the navigation data calculation module 114 and the location calculation module 116 calculate the location of the user using the navigation data.

To achieve higher performance, parallel correlators are typically used for parallel searching. However, the use of a large number of parallel correlators requires a large amount of logic resources and requires a high frequency of correlation operations, and the acquisition process is difficult to implement on an ASIC without optimization. The invention is therefore based primarily on the optimization of the acquisition module implementing the parallel correlator.

Disclosure of Invention

The present invention provides a method and apparatus for implementing the equivalent parallel correlator function using the I F signal preprocessing technique and the block integration technique. Therefore, the spread spectrum receiver has the advantages of lower correlation operation frequency, less gate operation and lower power consumption in the acquisition stage.

The present invention provides a method of processing a spread spectrum signal in a circuit having a plurality of block integrators, wherein the circuit uses an input signal, a local carrier signal and a pseudo random noise code, the input signal being digitized at a predetermined sampling frequency. The method comprises the following steps: a) generating pre-integration results at a predetermined rate based on an input signal and a local carrier signal, b) sending a set of a predetermined number of pre-integration results to each block integrator, c) receiving a pseudorandom noise code with a respective code phase in each block integrator, d) performing a partial correlation operation in each block integrator based on the set of predetermined number of pre-integration results and a segment of the pseudorandom noise code, e) obtaining the result of the partial correlation operation in each block integrator, f) adding the result of the partial correlation operation to the previous partial integration result, g) shifting the pseudorandom noise code sent to each block integrator by a predetermined position. The method repeats steps d) through g) until the next set of a predetermined number of pre-integration results is sent to each block integrator. The method further repeats steps b) to h) until a plurality of complete correlation results are obtained in each block integrator; wherein the partial correlation operation comprises a multiplication and an addition operation, the multiplication operation being a sign operation.

The invention also provides an apparatus for processing a spread spectrum signal digitized at a predetermined sampling frequency. The apparatus includes an intermediate frequency signal pre-processing unit and a plurality of parallel block integrators in communication with the intermediate frequency signal pre-processing unit. The intermediate frequency signal preprocessing unit generates a pre-integration result at a predetermined rate according to an input signal and a local carrier signal. Each block integrator continuously receives a plurality of groups of pre-integration results with preset quantity, and for each group of pre-integration results with preset quantity, each block integrator respectively carries out partial correlation operation on the group of pre-integration results with a plurality of sections of pseudo random noise codes after offset so as to obtain a plurality of partial correlation operation results until the next group of pre-integration results with preset quantity is sent to each block integrator; wherein the partial correlation operation comprises a multiplication and an addition operation, the multiplication operation being a sign operation.

The invention also provides a receiver for receiving the spread spectrum signal. The receiver comprises a tuner, an analog-to-digital converter, a device for processing a spread spectrum signal and a memory unit. The tuner converts the received spread spectrum signal from an original frequency to an intermediate frequency. An analog-to-digital converter connected to the tuner converts the intermediate frequency signal to a digital output signal at a predetermined sampling frequency. The device for processing the spread spectrum signal is connected to an analog-to-digital converter. The apparatus includes an intermediate frequency signal pre-processing unit and a plurality of parallel block integrators in communication with the intermediate frequency signal pre-processing unit. The intermediate frequency signal preprocessing unit generates a pre-integration result at a predetermined rate according to the digital input signal and the local carrier signal. Each block integrator continuously receives a plurality of groups of pre-integration results with preset quantity, and for each group of pre-integration results with preset quantity, each block integrator respectively carries out partial correlation operation on the group of pre-integration results with a plurality of sections of pseudo random noise codes after offset so as to obtain a plurality of partial correlation operation results until the next group of pre-integration results with preset quantity is sent to each block integrator. The apparatus also includes a control logic coupled to the memory unit and the plurality of block integrators. The control logic reads a previous partial correlation result from the memory cell, adds the current partial correlation result to the previous partial correlation result, and writes the modified previous partial correlation result to the memory cell. The storage unit is connected to the control logic and stores the calculation result. Wherein the partial correlation operation comprises a multiplication and an addition operation, the multiplication operation being a sign operation.

Drawings

Other features and advantages of the present invention will become more apparent in the following detailed description when taken in conjunction with the drawings, in which like numerals represent like elements, and in which:

fig. 1 shows a prior art block diagram of a spread spectrum receiver.

Fig. 2 is a block diagram of a conventional capture module.

Fig. 3 is an exemplary block diagram of a capture module according to one embodiment of the invention.

FIG. 4 is a detailed exemplary block diagram of the capture module shown in FIG. 3.

Fig. 5 is an exemplary flow chart for processing a spread spectrum signal according to one embodiment of the present invention.

Detailed Description

Fig. 2 illustrates a block diagram of an existing acquisition module for a particular channel. The acquisition module shown in fig. 2 includes 1023 parallel kernels numbered consecutively from the kernel 200-0 to the kernel 200-1022, a channel-N C/a code generator 202 that generates a C/a code, a local oscillator 204 that generates a carrier signal, and a search engine module 206. Each of the integrating kernels 200 takes the IF signal, the local carrier signal, and the C/a code as inputs to perform a correlation operation. At the integrating kernel 200-0, the correlation operation includes multiplying the IF signal by the local carrier signal and the C/A code. The results of the correlation operation are then sent to the search engine module 206. The search engine module 206 determines whether the correlation result exceeds a predetermined threshold and determines whether a particular doppler shift and C/a code phase shift is found. To find the starting point of the C/a code, it is common to shift the C/a code by 1/2 chips for each search of the C/a code. At the integrating kernel 200-1, a similar correlation operation is performed, except that the C/A code sent to the integrating kernel 200-1 is shifted 1/2 chips. The 1/2 chip offset block 208 is used to shift the C/A code by 1/2 chips. As previously described, one C/a code period includes 1023 chips. Therefore, for a certain frequency, 2046 correlation operations are required to complete the C/a code phase search for the entire cycle. Fig. 2 illustrates 1023 integral kernels covering half the period of the C/a code phase search. Therefore, to cover the entire cycle of the C/a code phase search, the IF signal needs to be acquired twice to complete the entire acquisition.

Although a parallel correlator provides a relatively high speed acquisition process, in practice 1023 parallel integrators are difficult to implement in hardware. To achieve equivalent parallel integration, some prior art techniques either increase the hardware size or select a high correlation frequency. The invention provides an advantageous method for realizing the functions of a large number of equivalent parallel integrators, and the required correlation operation frequency is low and the hardware scale is small. For simplicity, we mainly focus here on the implementation of 1023 equivalent parallel integrators or parallel correlators. However, those skilled in the art will recognize that any number of parallel integrators may be implemented using the methods detailed herein.

FIG. 3 illustrates an exemplary block diagram of the capture module of the present invention. An Intermediate Frequency (IF) signal pre-processing unit 302 receives at least three signals: an input signal (IF signal) 304, a local reference signal (carrier signal) 306 from a signal generator (local oscillator) 310, and a clock signal 308 from a code clock generator (PRN code numerically controlled oscillator, also known as PRN code NCO) 312. The IF signal pre-processing unit 302 is used to pre-integrate the IF signal to convert the rate of the input IF signal 304 from the sampling rate to a lower rate.

As previously described, the IF signal needs to be multiplied by the local carrier signal and the PRN code at the acquisition module. Since the C/a code does not change during the 1/2 chip period, the IF signal 304 may be multiplied by the local carrier signal 306 to obtain a pre-integration result, and then the pre-integration result may be multiplied by the PRN code during the 1/2 chip period. IF the sampling frequency of the input IF signal 304 is 16.368MHZ, since one period of the C/a code is 1 millisecond, the IF signal 304 contains 8 data samples in one data length of 1/2 chips. The IF signal pre-processing unit 302 is configured to multiply 8 sampled data points of the IF signal 304 with 8 corresponding sampled data points of the carrier signal 306 and to sum the products to obtain a pre-integration result. Thus, the 8-dot product operation is performed at 1/2 chip rate, i.e., the frequency of generation of the pre-integration result is 2.046 MHZ. Since the PRN code digitally controlled oscillator 312 generates the C/a code clock at 1/2 chip rate, the PRN code digitally controlled oscillator 312 can be used to control the generation of the pre-integration results at a predetermined rate, such as 1/2 chip rate. One advantage of the present invention is that the IF signal processing unit 302 can convert an input signal into a signal with a lower frequency. When the pre-processed input signal is generated at a lower frequency, each block integrator has enough time to perform multiple correlation operations in a time-division manner, rather than performing only one correlation operation as in fig. 2, so that multiple correlation operations share the same logic resource, as will be described in detail below.

The pre-integration results generated by the IF signal preprocessing unit 302 are divided into a plurality of groups, each group containing a predetermined number of pre-integration results. The IF signal processing unit 302 sends a plurality of sets of a predetermined number of pre-integration results to all the block integrators [ 314-0.., 314-7] connected in parallel to each other at predetermined intervals. For each set of the predetermined number of pre-integration results, each block integrator receives the set of the predetermined number of pre-integration results and the corresponding code segment of the PRN code generated by the code generator 316 simultaneously and performs a plurality of partial correlation operations. The correlation operation of the present invention is an inner product operation that generates an inner product value by multiplying each pre-integration result by each 1/2 chips and adding the product results. In one embodiment, IF signal pre-processing unit 302 may send each group, e.g., 33 pre-integration results, to block integrator [ 314-0. Each block integrator has a time period of 33 x (1/2 chip time length) to perform a partial correlation operation on the 33 received pre-integration results before the next set of 33 pre-integration results is ready. If each partial correlation is performed at the same frequency as the sampling frequency, e.g., 16.368MHZ, each block integrator completes at least 256 partial correlations during a time period of 33 x (1/2 chip time length). Therefore, 4 block integrators are sufficient to perform 1023 correlation operations. Since each pre-integration result includes two components: one path of in-phase signals (I signals) and one path of quadrature signals (Q signals), wherein 1023 groups of block integrators are needed for performing correlation operation of the I signals and the Q signals, and one group of block integrators process one path of signals. Thus, in this embodiment 8 block integrators are given.

Advantageously, the frequency of correlation operations used here is much lower than that used by conventional correlators. Of course, the present invention may also employ a higher correlation operation frequency. In addition, IF signal pre-processing unit 302 and parallel block integrator [ 314-0., 314-7] may operate in pipeline mode, i.e., block integrator [ 314-0., 314-7] processes a current set of a predetermined number of pre-integration results while IF signal pre-processing unit 302 produces a next set of a predetermined number of pre-integration results.

It should be appreciated, however, that the sampling frequency, the frequency of generation of the pre-integration results, the frequency of correlation operations, the number of pre-integration results sent to the block integrator at a time, and the number of block integrators are all related. Those skilled in the art will appreciate that these parameters may be set to different values in addition to those described herein. For example, the correlation operation frequency may be higher than 16.368MHZ, and the generation frequency of the pre-integration result may be set to 1/4 chip rate. The PRN code is not limited to the C/a code, and other types of PRN codes may be used.

Control logic 318, as shown in FIG. 3, may also be included in the capture module. The control logic 318 is used to control the computation of the overall correlation result. For example, after the block integrator 314-0 generates a partial correlation result, the control logic 318 reads the previous partial correlation result from a first storage unit (dual-ported SRAM)320 coupled to the control logic 318, adds the current partial correlation result to the previous partial correlation result generated by the same block integrator, and writes the sum to the first storage unit 320. After a plurality of sets of a predetermined number of pre-integration results are provided to the block integrator 314-0, a complete correlation result of the IF signal 304 over the entire period is obtained. In implementation, control logic 318 receives partial correlation results in parallel from parallel block integrators [ 314-0., 314-7] and performs the same operations as described previously for block-splitting integrator 314-0. The "previous partial correlation result" refers to the result of a correlation operation performed on a previous set of a predetermined number of pre-integration results and a corresponding segment of the PRN code.

A first storage unit (dual port SRAM)320 is connected between the control logic 318 and the control and coding module 322, as shown in fig. 3, for storing the results of the partial correlation operation and the continuous integration. Continuous integration is an operation in which similar results of a single correlation operation are accumulated over a period of time to improve the signal-to-noise ratio and enhance the detection capability of a weak signal of a receiver. Each block integrator may perform successive integrations over a predetermined data length.

The control and coding module 322 connected between the first storage unit 320 and the second storage unit 324 processes the continuous integration result from the first storage unit 320 and transmits the processed result to the second storage unit 324. The control and encoding module 322 may perform the following operations: and coding the continuous integration result, further processing the signal and performing discontinuous integration operation for enhancing the strength of the weak signal.

Fig. 4 illustrates a detailed block diagram of the capture block of fig. 3, and considers the I signal and the Q signal. Signal generator 410 generates two orthogonal carrier signals: a sine signal and a cosine signal. The cosine signal is obtained by phase shifting the sine signal. The phase shift operation is performed by the ii/2 phase shift module 434. The IF signal pre-processing module 402 includes two multiplier-adder (MAC) units 430 and 432. A first multiplier-adder (MAC) unit 430 performs a pre-integration operation based on the sinusoidal signal and the input IF signal and generates a pre-integration operation result having an in-phase component. A second multiplier-adder (MAC) unit 432 performs a pre-integration operation based on the cosine signal and the same input IF signal and generates a pre-integration operation result having quadrature components. Each MAC receives a clock signal generated by a code clock generator (PRN code NCO)412 such that the MACs 430 and 432 generate pre-integration results at 2 times the PRN code rate, i.e., at 1/2 chip rate.

Considering the I and Q signals, two sets of block integrators are used to process the I and Q signals, respectively. The block integrators 414-4, 414-5, 414-6 and 414-7 process the I-path signals to complete 1023 correlation operations in total, and each block integrator executes 256 correlation operations; and the Q signals are processed by block integrators 414-0, 414-1, 414-2, and 414-3 for a total of 1023 correlations, each of which performs 256 correlations. For the I or Q signals, since each block integrator operates in substantially the same manner, the only difference is that the phase shift of the C/a code sent to each block integrator is 256 × (1/2 code offsets).

The following description will be based on a block integrator. Block integrator 414-0 receives a set of a predetermined number of pre-integration results (e.g., 33 pre-integration results) and a segment of the C/a code containing 33 1/2 chips. The parallel multiply-add (parallel MAC) unit 436 in the block integrator 414-0 is capable of calculating an inner product (also referred to as a partial correlation) between 33 pre-integration results and 33 1/2C/a codes in one clock cycle (i.e., the inverse of the correlation operation frequency), and is also capable of adding the partial correlation operation result to the previous partial correlation operation result. The previous partial correlation result is an inner product between the previous 33 pre-integration results and 33 1/2C/a chips, 33 1/2C/a chips differing in phase from the current C/a code by (256+33) × 1/2 chips, respectively. The clock frequency may be the same as the sampling frequency, e.g., 16.368mhz or higher as previously described. The inner product calculation is also referred to as a partial correlation operation because each of the two input signals is a fraction of the signal period. As used herein, "parallel multiply-and-add" refers to a MAC that is capable of performing multiplication operations in parallel and summing the product results each time, and also accumulating the partial correlation operation results. The block integrator 414-0 also includes at least two memory registers R0438 and R1440 connected between the parallel MAC unit 436 and the control logic 418. Advantageously, the two storage registers may operate in a pipelined manner to alternately store the previous partial correlation result from the first storage unit 420 and the current partial correlation result of the parallel MAC unit 436. The operation of the two memory registers is controlled by control logic 418.

After the partial correlation results are generated, the code generator 416 offsets the C/A code by 1/2 chips. After the C/a code offset of 1/2 chips, the block integrator 414-0 begins the next partial correlation operation, taking the same 33 pre-integration results and offset C/a code as inputs and adding the current partial correlation operation result to the corresponding previous correlation operation result. The block integrator 414-0 repeats the above steps until the next set of 33 pre-integration results is received. Since the time interval between the arrival of two consecutive sets of 33 pre-integration results is 264 clock cycles, i.e. 33 × 8, each block integrator has enough time to calculate 256 partial correlation operations for the fixed 33 pre-integration results. The block integrator 414-0 receives multiple sets of 33 pre-integration results in succession until 256 complete correlation results are obtained.

256 correlation operations are performed in a block integrator in a time-division manner, so that 256 correlation operations can share a parallel MAC unit. Thus, one block integrator can be considered equivalent to 256 correlators, thereby reducing the required logic resources. In addition, the multiplication operation in the correlation operation calculated by the parallel MAC units is only a sign operation, because the C/A code has only two states of +1 and-1. It will be appreciated that these advantages are due to the pre-integration process performed by the IF signal pre-integration unit 402 and the division of these pre-integration results into blocks by the IF signal pre-integration unit 402.

The code generator 416 includes a PRN code generator 442 that generates parallel C/a codes at twice the C/a chip rate. The rate of generation is controlled by a clock signal issued by the PRN code NCO 412. Each C/a code sent to a different block integrator of the I or Q path has a different starting point. However, the block integrator of the I-way and the block integrator of the Q-way corresponding thereto receive the C/a code having the same code phase. For example, block integrators 414-0 and 414-4 receive the same C/A code without a phase shift. The block integrators 414-1 and 414-5 receive the same C/a code phase shifted 256 × (1/2 chip offsets). The block integrators 414-2 and 414-6 receive the same C/a code phase shifted by 2 x 256 x (1/2 chip offset). The block integrators 414-3 and 414-7 receive the same C/a code phase shifted by 3 x 256 x (1/2 chip offset).

The control logic 418, first memory cell (dual port SRAM)420, control and encoding module 422, and second memory cell (dual port SRAM)424 in fig. 4 are similar to the corresponding components in fig. 3. Therefore, for the sake of brevity, a detailed description thereof will be omitted.

Fig. 5 illustrates a flow chart 500 for processing a spread spectrum signal in a circuit having a plurality of block integrators, wherein the circuit employs an input signal digitized at a predetermined sampling frequency, a local reference signal, and a pseudorandom noise code. After the IF signal preprocessing unit receives a digitized signal, step 502, the IF signal preprocessing unit generates a pre-integration result at a predetermined rate (e.g., twice the PRN chip rate) based on the received signal and the local reference signal, step 504. When the pre-integration result is generated, the IF signal pre-processing unit sends a set of a predetermined number (e.g., 33) of pre-integration results to each block integrator in step 506. When each block integrator receives the set of predetermined number of pre-integration results, each block integrator also receives a pseudorandom noise code having a respective code phase at step 508. Each block integrator performs a partial correlation operation using as input a received segment of a pseudorandom noise code and the set of a predetermined number (e.g., 33) of pre-integration results, step 510. After the partial correlation results are obtained in each block integrator at step 512, the partial correlation results are added to previous partial correlation results at step 514, where the previous partial correlation results are obtained from a previous set of a predetermined number of pre-integration results and a corresponding pseudorandom noise code. After each block integrator completes the partial correlation operation, the pseudorandom noise code sent into each block integrator is shifted by a predetermined position in step 516. After the pseudorandom noise code shift, it is checked in step 518 whether each block integrator receives the next set of predetermined number of pre-integration results. If the next set of pre-integration results is not received in each block integrator, steps 510 to 516 are repeated, otherwise, step 520 is executed, i.e. it is detected whether a plurality of complete correlation results are obtained in each block integrator. If not, repeating steps 506 to 518, otherwise, executing step 522, i.e. further signal processing the complete correlation results.

In implementation, the GPS signal is received by an antenna 102 connected to the receiver 100 and converted from an original frequency to an intermediate frequency by a tuner 104. The intermediate frequency signal is then converted to a digital signal by the analog-to-digital converter 106 at a predetermined sampling frequency. The digitized digital IF signal is sent to the IF signal preprocessing unit 103. The IF signal preprocessing unit 103 performs a pre-integration operation with the IF signal and the local carrier signal as inputs and generates a pre-integration result at a predetermined rate. The plurality of sets of a predetermined number of pre-integration results generated by the IF signal preprocessing unit 103 are successively received by the plurality of parallel block integrators 314. For a set of pre-integration results with a predetermined number, each block integrator 314 performs partial correlation on the set of pre-integration results with multiple segments of the shifted PRN codes to obtain multiple partial correlation results until the block integrator 314 receives the next set of pre-integration results with the predetermined number. Each block integrator 314 continues to receive a plurality of sets of a predetermined number of pre-integration results and accumulate partial correlation results until a plurality of complete correlation results are obtained. The intermediate calculation result is stored in the first storage unit 320. To obtain multiple complete correlation results in each block integrator, control logic 318 is configured to read a previous partial correlation result from first storage unit 320, add the current partial correlation result to the previous partial correlation result, and rewrite the modified previous partial correlation result to first storage unit 320. In addition, the block integrator 314 also performs successive integration operations to improve the signal-to-noise ratio. The continuous integration results are sent to the control and coding module 322 for further processing, such as coding the continuous integration results, further processing the signal, and performing non-continuous integration operations. The second storage unit 324 is used to store the processed results from the control and encoding unit 322.

The method in the context of fig. 5 may also be implemented by, for example, execution of a series of machine-readable instructions by an arithmetic portion of a computing device. Although the steps are listed sequentially, the method may be performed in a different order or as an event-driven process. These instructions may be stored on various types of primary, secondary, or tertiary media with signal or data storage. The media includes, for example, RAM (not shown) accessible by, or stored in, the elements of the computing device. The instructions, whether contained in RAM, a diskette, or other secondary storage media, may be stored on a variety of machine-readable data storage media, such as DASD storage (e.g., a conventional "hard drive" or a RAID array), magnetic tape, electronic read-only memory (e.g., ROM, EPROM, or EEPROM), flash memory cards, an optical storage device (e.g., CD-ROM, WORM, DVD, digital optical tape), paper-tape punch cards, or other suitable data storage media including digital and analog transmission media.

The terms and expressions which have been employed herein are used as terms of description and not of limitation. The use of such terms and expressions is not intended to exclude any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications may be made within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims should be looked to in order to cover all such equivalents.

Claims (43)

1. A method of processing a spread spectrum signal, characterized by: the processing method is performed in a circuit having a plurality of block integrators using an input signal digitized at a predetermined sampling frequency, a local carrier signal and a pseudorandom noise code, said method comprising the steps of:

a) generating a pre-integration result at a predetermined rate based on the input signal and the local carrier signal;

b) sending a set of a predetermined number of pre-integration results to each block integrator;

c) receiving in each block integrator a pseudo-random noise code having a respective code phase;

d) performing a partial correlation operation in each block integrator based on the set of a predetermined number of pre-integration results and a segment of the pseudorandom noise code;

e) in each block integrator, obtaining a partial correlation operation result from the partial correlation operation;

f) if there is a previous correlation result, adding a partial correlation result to the previous partial correlation result, wherein the previous correlation result is obtained from a previous set of a predetermined number of pre-integration results and a corresponding segment of pseudorandom noise code;

g) shifting the pseudo-random noise code by a predetermined position;

h) repeating steps d) to g) until the next set of a predetermined number of pre-integration results is sent to each block integrator; and

i) repeating steps b) to h) until a plurality of complete correlation operation results are obtained in each block integrator, wherein the complete correlation operation results are used for further signal processing;

wherein the partial correlation operation comprises a multiplication and an addition operation, the multiplication operation being a sign operation.

2. The method of processing a spread spectrum signal according to claim 1, wherein: the method further comprises:

dividing the pre-integration result into an in-phase component and a quadrature component; and performing steps b) to i), respectively.

3. The method of processing a spread spectrum signal according to claim 1, wherein: the frequency of performing the partial correlation operation is equal to or greater than the sampling frequency.

4. The method of processing a spread spectrum signal according to claim 1, wherein: the input signal is an intermediate frequency signal converted from a spread spectrum signal.

5. The method of processing a spread spectrum signal according to claim 1, wherein: the pseudo-random noise code is a coarse acquisition code comprising 1023 chips, the period of the coarse acquisition code being 1 millisecond.

6. The method of processing a spread spectrum signal according to claim 1, wherein: the predetermined rate is twice the pseudo random chip rate.

7. The method of processing a spread spectrum signal according to claim 6, wherein: the pseudo-random chip rate is a coarse acquisition chip rate.

8. The method of processing a spread spectrum signal according to claim 1, wherein: the step of generating a pre-integration result comprises the steps of:

multiplying each data point of the input signal by each respective data point of the local carrier signal; and

within a data length, each product result is added to produce a pre-integration result.

9. The method of processing a spread spectrum signal according to claim 8, wherein: the data length is half of the pseudorandom chip length, the data length includes a number of data points, the number of data points depends on the predetermined sampling frequency.

10. The method of processing a spread spectrum signal according to claim 1, wherein: the predetermined position is a phase offset of half of the pseudorandom chip.

11. An apparatus for processing a spread spectrum signal digitized at a predetermined sampling frequency, characterized by: the apparatus comprises:

an intermediate frequency signal preprocessing unit for generating a pre-integration result at a predetermined rate based on the input signal and the local carrier signal; and

each block integrator continuously receives a plurality of groups of pre-integration results with preset quantity, and for each group of pre-integration results, each block integrator performs partial correlation operation on the pre-integration results with preset quantity and a plurality of shifted pseudo-random noise codes respectively to obtain a plurality of partial correlation operation results until the next group of pre-integration results with preset quantity is sent to the block integrator;

wherein the partial correlation operation comprises a multiplication and an addition operation, the multiplication operation being a sign operation.

12. The apparatus for processing a spread spectrum signal digitized at a predetermined sampling frequency according to claim 11 wherein: the apparatus further comprises:

a control logic coupled to said plurality of block integrators and a memory location, wherein said control logic reads a previous partial correlation result from said memory location, adds a current partial correlation result to the previous partial correlation result, and writes a modified previous partial correlation result to said memory location.

13. The apparatus for processing a spread spectrum signal digitized at a predetermined sampling frequency according to claim 11 wherein: the apparatus also includes a signal generator that generates two orthogonal local carrier signals, the signal generator being in communication with the intermediate frequency signal pre-processing unit.

14. The apparatus for processing a spread spectrum signal digitized at a predetermined sampling frequency according to claim 13 wherein: the intermediate frequency signal preprocessing unit further includes:

a first multiplier-adder unit that calculates a pre-integration result having an in-phase component, the first multiplier-adder unit multiplying each data point of the input signal by each corresponding data point of one of the two quadrature local carrier signals for a data length, and adding each product result to produce a pre-integration result having an in-phase component;

a second multiplier-adder unit for calculating a pre-integration result having a quadrature component, the second multiplier-adder unit multiplying each data point of the input signal by each corresponding data point of the other local carrier signal over a data length and adding each product result to produce a pre-integration result having a quadrature component.

15. The apparatus for processing a spread spectrum signal digitized at a predetermined sampling frequency according to claim 14 wherein: the data length is half of the pseudo random chip length, the data length includes a number of data points, the number of data points depends on the predetermined sampling frequency.

16. The apparatus for processing a spread spectrum signal digitized at a predetermined sampling frequency according to claim 14 wherein: the plurality of block integrators are divided into two groups, a first group receiving the pre-integration result containing the in-phase component, and a second group receiving the pre-integration result containing the quadrature component.

17. The apparatus for processing a spread spectrum signal digitized at a predetermined sampling frequency according to claim 11 wherein: the apparatus further includes a code clock generator coupled to the intermediate frequency signal preprocessing unit, the code clock generator controlling the pre-integration result to be generated at a predetermined rate.

18. The apparatus for processing a spread spectrum signal digitized at a predetermined sampling frequency according to claim 17 wherein: the apparatus further includes a code generator coupled to the code clock generator, the code generator generating a plurality of pseudorandom noise codes having respective code phases in parallel and transmitting each pseudorandom noise code having a respective code phase to a respective block integrator.

19. The apparatus for processing a spread spectrum signal digitized at a predetermined sampling frequency according to claim 18 wherein: the code generator is capable of shifting the pseudo random noise code by a predetermined position, and for each shift of the pseudo random noise code, the corresponding block integrator performs a partial correlation operation on the set of a predetermined number of pre-integration results and the shifted pseudo random noise code to obtain one of the plurality of partial correlation operation results.

20. The apparatus for processing a spread spectrum signal digitized at a predetermined sampling frequency according to claim 19 wherein: the predetermined position is a phase offset of half of the pseudorandom chip.

21. The apparatus for processing a spread spectrum signal digitized at a predetermined sampling frequency according to claim 11 wherein: the input signal is converted into a digital signal by an analog-digital converter at the preset sampling frequency.

22. The apparatus for processing a spread spectrum signal digitized at a predetermined sampling frequency according to claim 11 wherein: the frequency of performing the partial correlation operation is equal to or greater than the sampling frequency.

23. The apparatus for processing a spread spectrum signal digitized at a predetermined sampling frequency according to claim 11 wherein: the pseudo-random noise code is a coarse acquisition code comprising 1023 chips, the period of the coarse acquisition code being 1 millisecond.

24. The apparatus for processing a spread spectrum signal digitized at a predetermined sampling frequency according to claim 11 wherein: the predetermined rate is twice the pseudo random chip rate.

25. The apparatus for processing a spread spectrum signal digitized at a predetermined sampling frequency according to claim 11 wherein: each block integrator further comprises a parallel multiply-add unit that performs a partial correlation operation based on a set of predetermined numbers of pre-integration results and a corresponding segment of pseudorandom noise code.

26. The apparatus for processing a spread spectrum signal digitized at a predetermined sampling frequency according to claim 12 wherein: each of the block integrators further comprises at least two storage registers connected between the parallel multiply-add unit and the control logic, the two storage registers alternately storing previous partial correlation results from the storage unit and storing current partial correlation results, the control logic controls the operation of the at least two storage registers of each block integrator, and the at least two memories are connected in series.

27. The apparatus for processing a spread spectrum signal digitized at a predetermined sampling frequency according to claim 12 wherein: the storage unit is capable of storing the calculation result.

28. The apparatus for processing a spread spectrum signal digitized at a predetermined sampling frequency according to claim 11 wherein: the previous correlation result is obtained according to a previous set of a predetermined number of pre-integration results and a corresponding segment of pseudorandom noise code.

29. A receiver for receiving a spread spectrum signal, characterized by: the receiver includes:

a tuner for converting the spread spectrum signal from an original frequency to an intermediate frequency;

an analog-to-digital converter connected to the tuner, the analog-to-digital converter converting the intermediate frequency signal into a digital input signal at a predetermined sampling frequency;

a memory cell;

an apparatus for processing a spread spectrum signal connected to an analog to digital converter, comprising:

an intermediate frequency signal preprocessing unit for generating a pre-integration result at a predetermined rate based on the digital input signal and a local carrier signal;

a plurality of parallel block integrators which are communicated with the intermediate frequency signal preprocessing unit, wherein each block integrator continuously receives a plurality of groups of pre-integration results with preset quantity, and for each group of pre-integration results with preset quantity, each block integrator carries out partial correlation operation on the group of pre-integration results with a plurality of sections of pseudo random noise codes after offset so as to obtain a plurality of partial correlation operation results until the next group of pre-integration results with preset quantity is sent to the block integrator; and

a control logic coupled to said storage unit and said plurality of block integrators, wherein the control logic reads a previous partial correlation result from said storage unit, adds a current partial correlation result to the previous partial correlation result, and writes a modified previous partial correlation result to said storage unit;

wherein the partial correlation operation comprises a multiplication and an addition operation, the multiplication operation being a sign operation.

30. A receiver for receiving a spread spectrum signal as set forth in claim 29, wherein: the apparatus further includes a signal generator that generates two orthogonal local carrier signals, the signal generator being in communication with the intermediate frequency signal pre-processing unit.

31. A receiver for receiving a spread spectrum signal as set forth in claim 30, wherein: the intermediate frequency signal preprocessing unit further includes:

a first multiplier-adder unit that calculates a pre-integration result having an in-phase component, the first multiplier-adder unit multiplying each data point of the input signal by each corresponding data point of one of the two quadrature local carrier signals for a data length, and adding each product result to produce a pre-integration result having an in-phase component;

a second multiplier-adder unit for calculating a pre-integration result having a quadrature component, the second multiplier-adder unit multiplying each data point of the input signal by each corresponding data point of the other local carrier signal over a data length and adding each product result to produce a pre-integration result having a quadrature component.

32. A receiver for receiving a spread spectrum signal as set forth in claim 31, wherein: the data length is half of the pseudo random chip length, the data length includes a number of data points, the number of data points depends on the predetermined sampling frequency.

33. A receiver for receiving a spread spectrum signal as set forth in claim 31, wherein: the plurality of block integrators are divided into two groups, a first group receiving the pre-integration result containing the in-phase component, and a second group receiving the pre-integration result containing the quadrature component.

34. A receiver for receiving a spread spectrum signal as set forth in claim 29, wherein: the apparatus further includes a code clock generator coupled to the intermediate frequency signal preprocessing unit, the code clock generator controlling the pre-integration result to be generated at a predetermined rate.

35. The receiver for receiving a spread spectrum signal of claim 34, wherein: the apparatus further includes a code generator coupled to the code clock generator, the code generator generating a plurality of pseudorandom noise codes having respective code phases in parallel and transmitting each pseudorandom noise code having a respective code phase to a respective block integrator.

36. A receiver for receiving a spread spectrum signal as set forth in claim 35, wherein: the code generator is capable of shifting the pseudo random noise code by a predetermined position, and for each shift of the pseudo random noise code, the corresponding block integrator performs a partial correlation operation on the set of a predetermined number of pre-integration results and the shifted pseudo random noise code to obtain one of the plurality of partial correlation operation results.

37. A receiver for receiving a spread spectrum signal as set forth in claim 36, wherein: the predetermined position is a phase offset of half of the pseudorandom chip.

38. A receiver for receiving a spread spectrum signal as set forth in claim 29, wherein: the frequency of performing the partial correlation operation is equal to or greater than the sampling frequency.

39. A receiver for receiving a spread spectrum signal as set forth in claim 29, wherein: the pseudo-random noise code is a coarse acquisition code comprising 1023 chips, the period of the coarse acquisition code being 1 millisecond.

40. A receiver for receiving a spread spectrum signal as set forth in claim 29, wherein: the predetermined rate is twice the pseudo random chip rate.

41. A receiver for receiving a spread spectrum signal as set forth in claim 29, wherein: each block integrator further comprises a parallel multiply-add unit that performs a partial correlation operation based on a set of predetermined numbers of pre-integration results and a corresponding segment of pseudorandom noise code.

42. A receiver for receiving a spread spectrum signal as defined by claim 41, wherein: each of the block integrators further comprises at least two storage registers connected between the parallel multiply-add unit and the control logic, the two storage registers alternately storing previous partial correlation results from the storage unit and storing current partial correlation results, the control logic controls the operation of the at least two storage registers of each block integrator, and the at least two memories are connected in series.

43. A receiver for receiving a spread spectrum signal as set forth in claim 29, wherein: the previous correlation result is obtained from a previous set of a predetermined number of pre-integration results and a corresponding pseudorandom noise code.