HK1078395A - Frequency-timing control loop for wireless communication systems - Google Patents

Description

Frequency timing control loop for wireless communication system

Background

FIELD

The present invention relates generally to data communications, and more particularly to frequency timing control loops for wireless (e.g., CDMA) communication systems.

Background

In a wireless communication system, an RF modulated signal emitted from a source may reach a receiver at a destination via a plurality of propagation paths (e.g., straight paths and/or reflected/scattered paths). In a multipath environment, the signal at a given receiver may thus comprise multiple instances of the transmitted signal. Each signal instance (i.e., multipath component) may be associated with a different doppler shift resulting from movement of the receiver (or more accurately from relative movement between the receiver and the transmitter/reflector/scattering source associated with the signal instance). Each signal instance may further be associated with a different arrival time determined by the propagation path.

At the receiver, the received signal is conditioned and digitized to provide digital samples. Typically, a rake receiver is used to process data samples for multiple signal instances of a received signal. The rake receiver includes a plurality of finger processors, each assigned to process a respective signal instance based on the data samples. Each finger processor may include a rotator and interpolator to provide frequency and time tracking of the assigned signal instance accordingly. In particular, the frequency error of the signal instance may be estimated with a frequency control loop, and a rotator may be used to remove the estimated frequency error from the data samples to provide frequency-translated data samples. Also, the timing error of the signal instance may be estimated with a timing control loop, and an interpolator may be used to resample the frequency-shifted data samples (i.e., the sample timing associated with the highest signal-to-interference-and-noise ratio (SINR) of the signal instance) at the sample timing at which the signal instance is optimal or near optimal to provide on-time samples. The on-time samples in each finger processor may have frequency and timing errors associated with the removed assigned signal instances.

Using separate frequency and timing controls to individually track the frequency and timing of a given signal instance provides better performance when the SINR of the received signal IS low (e.g., for IS-95 CDMA systems). When this is the case, the SINR of the processed data samples (i.e., after rotation and interpolation) is not as sensitive to the rotation and interpolation of the data samples to remove frequency and timing errors. However, for systems that operate at high SINR (such as IS-856 CDMA systems), rotation and/or interpolation may result in significant degradation in SINR of the processed data samples, which may degrade performance.

There is therefore a need in the art for a technique to acquire and track the frequency and timing of a given signal instance that is optimized for high SINR operating environments.

SUMMARY

Techniques are provided herein to acquire and track the frequency and timing of a given signal instance such that resampling of the signal instance is not required. This may provide improved performance, particularly in higher SINR operating environments.

In one aspect, a frequency-timing control loop is provided that includes a frequency control loop and a timing control loop. The frequency control loop is used to acquire and track the frequency of a given signal instance (e.g., the strongest signal instance) within the received signal. The timing control loop is used to acquire and track the timing of the same signal instance and to adjust the phase of the ADC sampling clock so that the beats of the clock are approximately aligned with the "optimal" sampling instants of the signal instance.

In a particular embodiment, the timing control loop includes a timing discriminator, a first loop filter, and a transfer gain element. A timing discriminator (which may be implemented as an early-late detector) processes the data samples for the received signal to provide a timing error metric. The first loop filter then filters the timing error metric (e.g., based on a second order loop filter). In one embodiment, the transfer gain element applies a non-linear function to the first loop filter to provide a first control (phase adjustment term) indicative of a timing error within the data samples for the given signal instance.

In a particular embodiment, the frequency control loop includes a frequency discriminator and a second loop filter. The frequency discriminator derives a second control (frequency error metric) indicative of a frequency error within the data samples for the signal instance. The second loop filter then filters the first and second controls (based on the first order loop filter) to provide a third control. The third control may be used to adjust (1) a Local Oscillator (LO) signal frequency used to downconvert the received signal from RF to baseband, and (2) a clock signal phase used to digitize the downconverted signal to provide data samples. In a typical implementation, the clock signal is derived by dividing down the LO signal, in which case (1) and (2) are equivalent.

Various aspects and embodiments of the invention are described in further detail below. The present invention also provides control loops, methods, program codes, Digital Signal Processors (DSPs), receiver units, base stations, terminals, systems and other devices and elements that implement various aspects, embodiments and features of the invention, as described in further detail below.

Brief description of the drawings

The features, nature, and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout and wherein:

FIG. 1 is a block diagram of an embodiment of a receiver unit capable of implementing various aspects and embodiments of the invention;

FIG. 2 is a block diagram of an embodiment of a DSP that may be used to acquire and track frequency and timing for a given signal instance using a frequency-timing control loop;

FIG. 3 is a model diagram of a frequency-timing control loop (i.e., of a frequency control loop coupled to an outer/inner timing control loop) that can acquire and track the frequency and timing of a given signal instance; and

fig. 4 is a block diagram of a specific design for a frequency-timing control loop.

Detailed Description

Fig. 1 is a block diagram of an embodiment of a receiver unit 100 capable of implementing various aspects and embodiments of the invention. Receiver unit 100 may be implemented within a terminal (e.g., a cellular telephone) or a base station. A terminal may also be called a mobile station, a remote terminal, an access terminal, or some other terminology, and a base station may also be called an access point, a UTRAN, or some other terminology. Receiver unit 100 may also be used for various wireless communication systems such as, for example, IS-95, CDMA2000, IS-856, W-CDMA, TS-CDMA, and GPS systems.

In fig. 1, one or more RF modulated signals transmitted from one or more transmitters (e.g., base stations, GPS satellites, broadcast stations, etc.) are received by an antenna 112 and provided to a front-end unit, i.e., front-end circuitry. In this embodiment, the front end unit includes amplifiers/filters 114 and 118, a down-converter 116, and an analog-to-digital converter (ADC) 120. Amplifier/filter 114 amplifies the received signal with one or more Low Noise Amplifier (LNA) stages and further filters the amplified RF signal to remove noise and spurious signals. Downconverter 116 then performs quadrature downconversion of the filtered RF signal from RF to baseband (e.g., based on a heterodyne or direct downconversion receiver design). Downconversion may be achieved by multiplying (i.e., mixing) a filtered RF signal with a complex Local Oscillation (LO) signal to provide a complex baseband signal including an in-phase (I) component and a quadrature (Q) component.

Amplifier/filter 118 then amplifies the I and Q baseband components to obtain the appropriate signal amplitude for quantization, and further filters the amplified components to remove spurious signals and out-of-band noise. ADC120 then digitizes the filtered I and Q components to provide corresponding I and Q samples. In a particular embodiment, the ADC120 provides I and Q samples at a rate of 2 times the chip rate (i.e., chipx2), which for some CDMA systems is 1.2288 Mcps. The I and Q sample pairs for each chipx2 sample period are referred to herein as ADC samples or data samples. The data samples are provided to a Digital Signal Processor (DSP)130 for processing and/or may be stored to a sample buffer (not shown in fig. 1).

DSP 130 may perform a variety of functions such as filtering, rotating, resampling, demodulating, decoding, etc. DSP 130 may also implement various control loops to provide appropriate sampling timing and frequency control for each signal instance being processed, as described below. DSP 130 also implements a rake receiver that can concurrently process multiple signal instances within the received signal.

The signal generator 122 provides the LO signal used by the downconverter 116 and a reference signal (e.g., the chipx16 signal) to the chip clock generator 124. The signal generator 122 may include a frequency accurate signal source, such as a voltage controlled temperature compensated crystal oscillator (VC-TCXO), a frequency divider, and an integer/fractional N Phase Locked Loop (PLL) (for frequency synthesis). The chip clock generator 124 may divide and/or buffer the reference signal to provide the sampling clock for the ADC 120.

Controller 140 directs the various operations of receiver unit 100 and may provide various controls to DSP 130 and signal generator 122. For example, controller 140 may provide a first set of controls to direct DSP 130 to acquire the frequency and timing of one or more signal instances, a second set of controls to direct signal generator 122 to move to another carrier frequency, and so on. Memory 142 provides storage for data and program codes for controller 140 and DSP 130.

In a typical RF receiver design, the conditioning of the received signal is typically accomplished by one or more amplifiers, filters, mixers, and the like. In addition, the stages may be arranged in various configurations. For simplicity, the various signal conditioning stages are collectively placed into blocks in the illustration of FIG. 1. Other RF receiver designs may also be used and are within the scope of the invention.

As described above, in a multipath environment, each transmitted signal may be received over multiple propagation paths, and the received signal may thus include multiple instances of each transmitted signal. The signal received at the receiver unit may thus comprise a plurality of signal instances of one or more transmitted signals. Each signal instance is associated with a respective amplitude, frequency and arrival time of the receiver unit.

Fig. 2 is a block diagram of an embodiment of DSP 130a that may be used to acquire the frequency and timing of a given signal instance using the techniques described above. DSP 130a may implement a rake receiver that is capable of concurrently processing multiple signal instances. A rake receiver typically includes a searcher and a plurality of finger processors. The searcher is typically used to search for stronger signal instances within the received signal. Each finger processor may then be assigned to process a particular signal instance, as determined by the searcher. Each finger processor may include a pilot processor 210 to process the data samples to obtain pilots for the assigned signal instances. Each finger processor typically also includes other elements for data demodulation, which are not shown in fig. 2 for simplicity.

Fig. 2 shows pilot processor 210 within DSP 130 a. Within pilot processor 210, the data samples from ADC120 are provided to rotator 212, which implements a complex multiplication of the data samples with a complex sinusoidal signal to provide frequency-translated (or rotated) data samples. The frequency of the complex sinusoidal signal is determined by a frequency control Fctrl 2. Rotator 212 may be used to remove phase rotation within the data samples due to down-conversion frequency error and/or doppler shift within the processed signal instance. The complex sinusoidal signal frequency used by rotator 212 is an estimate of the frequency error of the assigned signal instance, as determined by frequency control loop 230.

Returning to fig. 1, the baseband signal from amplifier/filter 118 is first sampled at a suitable rate (e.g., chipx2) and then quantized to a finite number of amplitude levels. The combination of sampling and quantization is referred to as analog-to-digital (AD) conversion and is implemented by the ADC 120. In general, the sampling timing used by the ADC may not be aligned with the optimal sampling timing for a given signal instance. Thus, the ADC output is then subjected to (linear) interpolation and decimation. The effect of interpolation and decimation is to change the "apparent" sampling time of the original baseband signal. This process may be referred to as "resampling" or "virtual" sampling. Interpolation-based resampling should be different from "actual" sampling and implemented by the ADC prior to quantization. The pre-quantized samples at the ADC are referred to below as "ADC samples". In general, the resampling instants may be offset by some discrete value (e.g., a multiple of chipx8 time period) from the ADC sampling instants.

The timing control loop is used to track the timing of the processed signal instance. The timing control loop can be conceptually broken down into an "inner" loop and an "outer" loop. The inner timing control loop attempts to adjust the resampling instants (i.e., resampler timings) to match the true signal delays of the selected signal instances. The outer timing control loop attempts to change the ADC sampling instant (i.e., ADC sampling timing) to match the true signal delay, thereby removing the need to resample for this signal instance. Conventional designs may use only an inner loop, as described below.

Interpolator 214 may resample the frequency-translated data samples to provide interpolated samples for the processed signal instance. The resampling is implemented based on a resampler control, Tctrl, which is provided by a timing loop filter 240. The resampler timing control indicates a particular time offset t_adjFor resampling frequency-translated data samples, and are typically provided with a particular time resolution (e.g., chipx8 or T)_c8 resolution). For each chip period, interpolator 214 provides "early" interpolated samples to the despread and integrate-dump (I)&D) Element 222a, providing "late" interpolated samples to the despread I&D-element 222 c. On-time interpolated samples are numbers provided by the ADC120 if the ADC sample clock is aligned to the "optimal" sample timingBy approximation of the sampling, the "optimal" sampling timing is the timing that would produce the highest signal-to-interference-and-noise ratio (SINR) of the signal instance. The early-late interpolated samples are correspondingly at-T from the on-time sampling time_c(ii)/2 and + T_cApproximation of data samples at/2.

PN generator 216 provides each despread I&The D-element 222 is a PN sequence with a particular PN state (or PN phase) corresponding to the time of arrival of the processed signal instance. The PN state may be determined by its searcher in its search for the strongest signal instance within the received signal and provided to PN generator 216. Each despreading I&D element 222 despreads its received interpolated samples with the PN sequence to provide despread samples, and further covers the decoded samples with the channelization code used for the pilot. For many CDMA systems, the channelization code for the pilot is a sequence of zeros (e.g., Walsh code zero), in which case decovering may be omitted. Each despread I&The D element 222 further accumulates (i.e., integrates) the despread samples over a particular duration to provide complex pilot symbols P_I+jP_Q. For continuous pilot structures such as those used in IS-95 and cdma2000, the accumulation duration may be an integer multiple of the channelization code length (i.e., 64 · N, where N IS any integer). And for a gated pilot structure such as that used in IS-856 and W-CDMA, the accumulation duration may correspond to each pilot burst or a portion of a pilot burst. For IS-856, each pilot burst covers 96 chip periods every 1024 chip half-slot.

The pilot symbols derived from the on-time interpolated samples are used by frequency control loop 230 to derive frequency control Fctrl1 for signal generator 122 and/or Fctrl2 for rotator 212. In particular, within the frequency control loop 230, the pilot symbols from the despread I & D element 222c are provided to a frequency discriminator and used to derive a frequency error metric, Ferr, which is the instantaneous error in the frequency of the signal instance being processed. The loop filter then filters the frequency error metric to provide frequency controls Fctrl1 and/or Fctrl2, which are provided to rotator 212. The frequency control loop 230 is described in detail below.

The pilot symbols derived from the real-time compensated samples are also provided to a pilot filter 228 and a Received Signal Strength Indicator (RSSI) 232. Pilot filter 228 filters the pilot symbols based on the response of a particular low pass filter to provide filtered pilots, which may be used for data demodulation as well as other purposes. The RSSI 232 processes the pilot symbols to provide signal strength estimates of the pilots (which also indicates the pilot SINR since the total noise is known or can be determined). The pilot strength estimate is provided to the controller 140 and may be used to select a particular signal instance for frequency and time tracking based on the frequency-timing control loop.

The pilot symbols derived from the early-late interpolated samples are used by the timing control loop to derive the resampler timing control Tctrl for interpolator 214. The timing control loop may implement a Delay Locked Loop (DLL) or some other design. The pilot symbols from the despread I & D elements 222a and 222b are provided to a timing discriminator (e.g., an early/late detector) and used to derive a timing error metric Terr, which is an estimate of the instantaneous error (relative to the optimal sampler timing) in the resampler timing for the signal instance being processed. Timing loop filter 240 then filters the timing error metric and further quantizes the loop filter output to provide an updated resampler timing control, Tctrl.

For the embodiment shown in fig. 2, the timing discriminator includes amplitude squarers 224a and 224b and an adder 226. Amplitude squarers 224a and 224b correspondingly despread I from&D-elements 222a and 222 b. Each amplitude squarer 224 calculates the energy E of each pilot symbol_PIs composed ofAmplitude squarer 224a then provides a derived early pilot energy E based on the early interpolated samples_P，earlyAnd amplitude squarer 224b provides a derived late pilot energy E based on the late interpolated samples_P，late. Summer 226 then subtracts the late pilot energy from the early pilot energy and subtracts the difference (i.e., E)_P，early-E_P，late) And provided to timing loop filter 240. Other types of timing discriminators may also be used for the timing control loop, as is known in the art.

The output from the timing discriminator (which is the timing error metric Terr from the adder 226) is then filtered by the timing loop filter 240 to provide a fine precision timing error t indicative of the ADC sample time and the "optimum" sample time for that signal instance_diff. Timing loop filter 240 then quantizes the fine precision timing error t_diffTo provide a coarse precision time offset t_adjThis is used to resample the frequency converted data samples. Timing loop filter 240 then provides a resampler timing control, Tctrl, to interpolator 214 that indicates the time offset, t_adj。

Returning to FIG. 1, with f_inWith a given signal instance in the received signal of the carrier frequency of f_outIs downconverted (this is the "effective" downconversion frequency for a heterodyne receiver with multiple frequency downconversion stages). This signal instance produces a baseband signal with a residual frequency offset (i.e., frequency error) of Δ f. Each signal instance may have a different Doppler shift, and thus may correspond to a different input frequency f_inAnd (4) associating. Since the same LO frequency f is used for all signal instances_outEach signal instance then has a different frequency error deltaf. The rotator in the finger processor is then used to remove the frequency error af of the assigned signal instance.

Each signal instance is also associated with a respective time of arrival at the receiver unit. The optimal sampling instant for a given signal instance may be denoted as τ_in. The received signal is sampled at specific ADC sampling instants, denoted tau_outAnd may or may not be time aligned with the optimal sampling instant for any given signal instance. Difference τ between ADC sampling instant and optimal sampling instant for a given signal instance_diffCan be prepared fromThe timing control loop estimate used by the signal instance, and the difference may be quantized to provide a time offset τ_adj. The interpolator within the finger processor assigned to the processed signal instance is then used to resample the data samples from the ADC (or the frequency converted data samples from the rotator) based on the time offset τ_adjTo provide an estimate of the samples that can be obtained at the optimal sampling instant. However, due to the timing difference τ_diffThe interpolated samples have a timing error of delta tau.

In conventional designs, a frequency control loop may be used to lock the LO signal frequency to the frequency of one of the signal instances in the received signal (e.g., the strongest signal instance). The frequency error for each individual signal instance to be processed is then estimated and removed by the corresponding frequency control loop operating with the rotator of the assigned finger processor. In addition, a delay locked loop (timing tracking loop) is used to derive and track the timing for each signal instance to be processed.

Conventional designs (using only the inner loop for time tracking) provide better performance when the SINR of the received signal is low, which is generally true for CDMA systems designed to transmit concurrently to multiple terminals. For systems designed to operate at high SINR (e.g., greater than 0dB), such as IS-856 systems, resampling can result in severe degradation of signal SINR, which can degrade demodulation and decoding performance. If the difference t between the fine-precision timing of the ADC sample and the optimal sampling instant_diffQuantized to a coarse (e.g., chipx8) time resolution to obtain a time offset t for resampling_adjThe deterioration is aggravated. In fact, it can be shown that quantization of the re-sampling timing is a major cause of jitter within the sampling timing and resulting performance degradation.

Techniques are provided herein to acquire and track the frequency and timing of a given signal instance such that resampling of the selected signal instance is not required. This may provide improved performance, especially in high SINR operating environments. In an aspect, the frequency-timing control loop includes a frequency control loop and provides an outer timing control loop. The frequency control loop is used to acquire and track the frequency of the signal instance (e.g., the strongest signal instance) within the selected received signal. The outer timing control loop is used to adjust the ADC sampling clock phase so that it can be aligned with the "optimal" sampling instant of the selected signal instance. In addition, each finger processor may run its own inner timing control loop and rotator, which determines the resampler timing and frequency shift of the signal instance associated with that finger processor.

Fig. 3 is a model diagram of a frequency-timing control loop 300 that can acquire and track the frequency and timing of a given signal instance. The frequency-timing control loop 300 couples the frequency control loop 310 with the inner time tracking loop 350 through the outer time tracking loop 380.

The frequency control loop 310 includes a frequency discriminator 320, a loop filter 330, and a VCO 340. Within the frequency discriminator 320, the carrier frequency f of the signal instance_inFrom the LO frequency f may be derived by a summer 322_outAnd (4) subtracting. The frequency difference (i.e., the frequency error Δ f) is scaled by a gain G by the scaler 324_f. Summer 322 models the downconverter in FIG. 1, and scaler 324 provides the gain of the frequency discriminator. The frequency discriminator 320 provides an output that is approximately proportional to the instantaneous frequency error Δ f. Switch 328 models the sampling of the frequency discriminator output (e.g., for gated pilots where the frequency discriminator output is valid only for each pilot burst.

Loop filter 330 receives and filters the frequency discriminator output. In one embodiment, loop filter 330 is implemented as a first order loop and includes a loop accumulator that includes a register 338 and an adder 336. The frequency discriminator output is initially scaled by a gain K by multiplier 332_LAnd the scaled value is further accumulated by a loop accumulator. Adder 334 adds the accumulator output to the phase correction term θ_corIn combination, the correction term is derived from the outer timing control loop and provides an output from adder 334 for accumulation with the scaled value from multiplier 332. Gain K_LCan be used for adjusting the heel of a frequency control loopThe bandwidth is tracked.

VCO 340 includes a multiplier 342 that receives and scales the output from loop filter 330 to provide the LO frequency f_outWith a gain of K_v. Gain K_vRepresenting the transfer gain (e.g., output frequency versus input voltage) of the actual VCO used within signal generator 122 to generate the LO signal used to downconvert the received signal from RF to baseband.

In the embodiment shown in fig. 3, outer timing control loop 380 includes a divider 348, an ADC sampler 352, a modulo (Mod) element 382, and a transfer gain element 390. For a CDMA system in which the carrier frequency is selected to be an integer multiple of the chip rate, divider 348 may be used to divide the LO signal by K_tIn which K is_t＝f_chip/f_carrierTo obtain a belt with f_chipChip rate clock of frequency.

The ADC sampler 352 derives chipx2 based on the chip rate clock, and the chipx2 clock is used as the sampling clock for the ADC. The sampling clock and the receiver time reference t_outCorrelation, which may be in chip periods T_cScaled to obtain a normalized time reference τ_out. ADC120 samples the baseband signal with a sampling clock to provide a time reference t at the receiver_outThe data samples at (c). Since the sampling clock is twice the chip rate, the baseband signal can be assumed at any time t_outIs T_cInteger multiple of/2, or τ_outAre sampled at integer multiples of 1/2.

Each signal instance within the received signal has a specific arrival time at the receiver unit and is further correlated with an optimal sequence of sample instants, one per chip period, which provides the highest SINR to the demodulator. Thus, each signal instance is associated with an optimal time reference f_chipOr normalizing the optimal time reference τ_in＝t_in/T_cIs correlated so that when t_inIs T_cInteger multiple of or when τ_inWhen integer, the optimal sampling instants correspond to these instants.

Each finger processor of the rake receiver maintains an internal timing control loop that estimates a normalized receiver time reference τ for the signal instance being processed by the finger processor_outAnd normalizing the optimal sampling time reference tau_inTiming difference τ between_diff. Normalizing receiver time reference τ for a given signal instance_outMay or may not correspond to the optimal sampling time reference τ_in. Thus, an interpolator is included in each finger processor and is used to resample the output of the ADC to derive interpolated samples that are estimates of the data samples obtained at the optimal sampling instants. For a linear interpolator, at time τ_out＝n(T_c/2) the ADC sample pairs obtained are used for interpolation to obtain interpolated samples, which are the optimal time instants τ_in＝n(T_c) The data sample estimates of (a). The interpolator is designed with a specific time resolution, which may be a quarter of a chip period, T_c/8. In this case, the timing difference τ_diffQuantized to the resolution of chipx8 to provide time offset τ_adjAnd is used for determining the weight of interpolation.

As shown in fig. 3, the inner timing control loop 350 includes a timing discriminator 360, a loop filter 370, and other elements that together implement the inner timing control loop. Within the timing discriminator 360, the optimal sampling time reference τ for the signal instance_inFrom the receiver time reference tau by an adder_outAnd a time offset τ_adjSubtracted to provide the instantaneous time error Δ τ. The timing error Δ τ is scaled by a gain G by a scaler 364_d. Adder 362 samples clock and timing difference τ from ADC_diffQuantization models the timing error and the sealer 364 models the gain of the timing discriminator. The timing discriminator 360 provides an output that is approximately proportional to the instantaneous timing error Δ τ. Switch 368 is a model for timing discriminator output samples.

Loop filter 370 receives and filters the timing discriminator output. In one embodiment, loop filter 370 is implemented as a second order loop and includes two loop accumulators. First stage of the exerciseThe adder includes a register 376a and an adder 374a, and the second accumulator includes a register 376a and an adder 374 b. The timing discriminator output is initially scaled by multipliers 372a and 372b, respectively, by c₀And c₁The gain of (c). The scaled value from multiplier 372b and the output from the first accumulator are then accumulated by a second loop accumulator. Loop filter 370 provides an indication of the timing difference τ_diffIs output from the loop.

For an internally timed control loop, the output from loop filter 320 is used to adjust the re-sampling time of the signal instance. Quantizer 378 quantizes the timing difference τ_diffTo chipx8 resolution to provide time offset τ_adjThis is used by interpolator 214 to implement the interpolation.

The inner timing control loop is a coarse loop because (1) the timing difference τ_diffQuantization to chipx8 resolution (which in effect results in the optimal sampling instant being quantized to the same chipx8 resolution) and (2) interpolation being used to derive the data sample estimate at the optimal sampling instant. This coarse inner timing control loop provides better performance at low SINR, but this may result in some performance degradation at high SINR.

The outer timing control loop can be used to minimize performance loss at high SINR by adjusting the received reference τ for a given signal instance_outNear optimal sampling time reference tau_in. This can be achieved by providing appropriate sampler timing using an outer timing control loop so that the received signal is sampled directly by the ADC at the optimum sampling instant, which avoids resampling.

If only one set of ADCs is used to sample the received signal, the receiver time reference may be synchronized with the optimal sampling time reference for a single signal instance. In an embodiment, the receiver time reference is steered closer to the optimal sampling time reference for the optimal signal instance. Since conventional designs with separate frequency and timing control loops may provide better performance at lower SINRs, the outer timing control loop may be enabled only if the SINR of the strongest signal instance exceeds a certain threshold (e.g., 4.5 dB).

In one embodiment, the frequency-timing control loop is implemented by extending the frequency control loop to include timing error estimates obtained by the outer timing control loop. The loop provides a timing difference τ between the ADC sample and the optimal time reference_diffIs estimated. If the received signal is sampled at chipx2, then the ADC sampling instant coincides with the optimal sampling instant if

τ_out＝τ_in(modulo 1/2)，

Or equivalently if

τ_diff＝0(modulo 1/2)

Normalized timing error tau_errCan be defined as follows:

τ_err＝τ_diff mod 1/2

the timing error tau_errMay be generated by a modulo element 382 within the outer timing control loop 380 of fig. 3 and may be represented as a signed number between-1/4 and + 1/4. External timing control loop using normalized timing error tau_errTo generate a phase adjustment term theta_corThis can be combined with a correction term from the frequency discriminator. These two terms are then filtered by loop filter 330 and used to update the frequency and phase of the LO signal.

The frequency control loop uses the frequency adjustment term from the frequency discriminator to frequency lock the LO signal to the carrier signal of a given signal instance within the received signal. After frequency lock is achieved, the frequency control loop maintains an average LO frequency that is equal to the frequency of the incoming signal instance, but the phase offset between the signal instance and the LO signal varies in time in an unbiased manner. Without the phase adjustment term (conventional time tracking), the behavior of the phase offset is brownian motion. Phase adjustment term θ with external time tracking loop enabled_corManipulating residual phase offset between signal instances and LO signal such that ADC sampler time reference τ_outAnd optimizationSampling time reference tau_inAnd (6) conforming to the standard. Therefore, the signal instance does not require interpolation, and thus an improved SINR may be obtained for the signal instance.

As shown in FIG. 3, a transfer gain element 390 within the outer timing control loop 380 receives the normalized timing error τ from the timing loop filter_errAnd providing a timing based phase adjustment term θ_cor. In one embodiment, element 390 implements the nonlinear transfer function Ψ (τ)_err) Several design objectives are made possible, as described below.

Phase adjustment term theta_corAn instantaneous frequency offset is introduced between the LO signal and the signal instance because it drives the residual phase offset to a desired value. The outer timing control loop can be designed so that it does not introduce too much frequency error at any given time, especially when the outer timing control loop has just been turned on. If the timing error is tau_errToo large, this can be achieved by adjusting the phase by the term θ_corIs limited (or saturated) to a certain maximum value. This may avoid large frequency errors, especially during transient states, which may deteriorate demodulation performance. Conversely, if the timing error is too small and the effect on SINR is negligible, the phase adjustment term θ_corMay be set to zero. This may minimize or reduce steady state frequency jitter on the LO signal due to the phase adjustment term.

In one embodiment, the phase adjustment term θ_corCan be expressed as:

in one embodiment, the timing error τ_errIs a transfer functionSeveral psi (τ)_err) Given by the following expression:

as equation (2) shows, the function Ψ (τ) when the magnitude of the timing error is neither too large nor too small_err) At timing error tau_errThe above is linear. In particular embodiments, the following values may be used for the parameters of equation (2): tau is_min1/16 and G_P|τ_err20. Other designs may also be used and are within the scope of the invention.

The performance of the frequency-timing control loop can be analyzed and performance metrics such as tracking bandwidth and steady-state jitter can be determined in a manner known to those skilled in the art.

In many receiver implementations, the ADC sampling clock is tied to the LO frequency. Thus, changing the ADC sampler timing introduces transient transition frequency errors in the RF/IF down-conversion mixer. Furthermore, a common local oscillator and a common sampler are shared by all finger processors of the rake receiver. Thus, the outer timing control loop affects the sampling instants of all finger processors. Thus, the outer loop may be activated (i.e., one path/signal instance) on a particular finger processor, while the inner loop may be independently activated/deactivated on each signal instance. In other words, the inner timing control loop may operate independently for each finger processor. Since the outer timing control loop produces performance gain mainly at high SINR, the loop can be operated such that the ADC sampler is optimized for the signal instance with the highest SINR.

While the inner timing control loop is almost independent of the frequency control loop, the outer timing control loop is tightly coupled to the frequency control loop and the inner loop where the single finger processor operates. Unwanted interactions (positive feedback) between these different control loops, which can lead to instability, must be avoided.

In one embodiment, only one of them is presentStability can be guaranteed by enabling the outer timing control loop in case the SINR of the finger processor is reasonably high (to demonstrate high performance gain). To ensure loop stability, the phase adjustment term theta_corTracking bandwidth f of related frequency timing control loop_TR，outCan be designed to be smaller than (1) the tracking bandwidth f of the frequency control loop_TR，fAnd (2) a tracking bandwidth f of the inner timing control loop_TR，in. If the tracking bandwidth f_TR，outLess than tracking bandwidth f_TR，fAnd f_TR，inTwice or more, stability can be ensured. In a particular design, the tracking bandwidth f_TR，outCan be designed to be specific to the tracking bandwidth f_TR，fAnd f_TR，inThe amplitude is several orders of magnitude smaller.

For the forward link in an IS-856 system with a gated pilot transmission scheme, the frequency control loop may be designed to track bandwidth on the order of 100Hz at high SINR, with steady state frequency jitter below the standard deviation of 10 Hz.

In the case where conflicting design requirements need to be balanced, as shown in FIG. 2, the timing error τ_errAnd phase adjustment term theta_corThe choice of the non-linear function Ψ () of the transfer function between is derived from the need to reduce frequency jitter. When receiver time reference tau_outIs near optimum, τ_errA dead zone (i.e., Ψ (τ)) within the function Ψ () of smaller value_err) For | τ, | 0_err|≤τ_min) Ensure gamma_P0. When receiver time reference tau_outAway from the optimal time reference τ_inTime (i.e., during the transition period of the outer timing loop operation), τ_err() Of a larger value of (i.e. Ψ (τ))_err)＝sign(τ_err)·G_P|τ_errFor | τ_err|≥τ_max) For limiting the peak value of the frequency error due to steady-state jitter at the output of the timing loop filter and a large phase adjustment term.

The frequency-timing control loop may be implemented based on various designs. One specific design is described below.

Fig. 4 is a block diagram of a frequency-timing control loop 400 that may be used to acquire and track the frequency and timing of a given signal instance. Frequency-timing control loop 400 includes a frequency control loop 230a and a timing loop filter 240a, which are embodiments of the corresponding frequency control loop 230 and timing loop filter 240 of fig. 2.

The frequency control loop 230a includes a frequency discriminator 420 coupled to a loop filter 430. Frequency discriminator 420 despreads I&D element 222c receives the pair of consecutive complex pilot symbols P_I(i)+jP_Q(i) And P_I(i-1)+jP_Q(i-1), which is derived based on the on-time interpolated samples. The frequency discriminator 420 then derives a frequency error metric, Ferr, for these pilot symbols. In particular, within the frequency discriminator 420, a multiplier 422a receives and combines the previous pilot symbol P_QMultiplying the imaginary part of (i-1) by the current pilot symbol P_Q(i) To provide the product to adder 424. Multiplier 422b also receives and combines the real part P of the previous pilot symbol_I(i-1) multiplied by the current pilot symbol P_Q(i) And provides the product to adder 424. Adder 424 then subtracts the product of multiplier 422a from the product of multiplier 422b and provides a frequency error metric, Ferr. Other types of frequency discriminators may also be used and are within the scope of the present invention.

In the embodiment shown in fig. 4, the loop filter 430 implements a first order loop filter for the frequency control loop. Loop filter 430 includes a single accumulator including adder 436 and register 438. The first loop filter input (which is the frequency error metric, Ferr, from the frequency discriminator 420) is initially scaled by the multiplier 432 by the scaling factor K_LScaled. The scaled value from multiplier 432 is then combined with the second loop filter input (which is the phase correction term Pcor or θ from timing loop filter 240 a) by adder 434_cor). The output from the accumulator, including the frequency control loop output Fctrl1, is provided to signal generator 122 a. The loop output is an estimate of the frequency error Δ f of the data samplesAnd (6) counting.

Signal generator 122a is an embodiment of signal generator 122 in fig. 1. Within signal generator 122a, a signal converter 442 receives and adjusts the frequency control loop output Fctrl1 to provide a control signal (e.g., a voltage or current) with an appropriate form. The control signal is then used to adjust the frequency and phase of the VCO 444. VCO 444 provides the LO signal to downconverter 116 and (although not shown in fig. 4) may provide a reference signal to clock generator 124 for deriving a sampling clock for ADC 120. The reference signal may be a divided version of the LO signal. VCO 444 may be implemented with various designs (e.g., as a single VCO, a VCI phase locked to a VCXO, or based on some other design), as is known in the art.

In general, the frequency control loop output Fctrl1 is used to adjust the frequency and phase of a "periodic" signal that directly or indirectly determines (1) the LO signal frequency used to downconvert the received signal, and (2) the clock signal phase used to digitize the downconverted signal. The periodic signal may be the LO signal itself, or may be an intermediate frequency signal to which the LO and clock signals may be locked by one or more Phase Locked Loops (PLLs), as is known in the art. The reference signal provided by the signal generator to the clock generator may be the ADC sampling clock itself. Alternatively, the ADC sampling clock may be derived based on the reference signal (e.g., by dividing the reference signal or locking another VCO to the reference signal).

In the embodiment shown in fig. 4, timing loop filter 240a implements a second order loop filter for the timing control loop. Timing loop filter 240a includes a first accumulator that includes adder 474a and register 476a, and a second adder that includes adder 476a and register 476 b. The timing loop filter input (which is the timing error metric Terr from the timing discriminator shown in fig. 2) is initially scaled by a multiplier 472a by a scaling factor c₀Scaled and scaled by a scaling factor c by a multiplier 472b₁Scaled. The scaled value from multiplier 472b is then accumulated by a first accumulator.The output from the first accumulator is combined with the scaled value from multiplier 472a by adder 474b, and the combined value is further accumulated by a second accumulator.

For the inner timing control loop, quantizer 478 quantizes the output from the second accumulator (this corresponds to the timing difference τ in the outer timing control loop model in FIG. 3)_diff) To a particular desired resolution (e.g. T)_c8) as required by the interpolator used to resample the data samples from the ADC. After a frequency and timing lock of a given signal instance with the outer timing control loop is achieved, the signal instance is sampled at the optimal (or near optimal) sampling instant and no interpolation is required for the signal instance. However, if the outer timing control loop is not enabled, or is not available for signal instances, quantizer 478 (within the inner timing control loop) provides a resampling timing control, Tctrl, for interpolation. The output from quantizer 478 corresponds to the time offset τ in the frequency-timing control loop model in FIG. 3_adj。

For the outer timing control loop, the output from the second accumulator is provided to a modulo element 482, which implements a modulo M operation, where M ═ T_s/T_cAnd T is_sIs the sampling period, T_cIs the chip period. If the sampling rate is chipx2, T_s＝T_cAnd M is 1/2. If M is a power of two, the modulo M operation may be implemented by omitting some of the More Significant Bits (MSBs) from the second accumulator and transmitting the remaining Less Significant Bits (LSBs). The output from modulo element 482 corresponds to the timing error τ in the frequency-timing control loop model in FIG. 3_err。

Transfer gain element 490 receives the timing error from modulus element 482 and provides a phase correction term Pcor based on a particular transfer function, such as that shown in equation (1). In one embodiment, the transfer function comprises a non-linear function such as that shown in equation (2). The transfer gain element 490 also receives an enable signal indicating whether the outer timing control loop is enabled. Transfer gain element 490 provides the effective phase correction term Pcor if the outer timing control loop is enabled (e.g., the enable signal is at logic high), and zero otherwise.

Fig. 4 shows a specific design of each component of the frequency-timing control loop. Other designs that can be used for the frequency discriminator and the loop filter are described in various references within the field. One such reference is the book by A.J. Viterbi, entitled "primers of Spread Spectrum Multiple Access communications", second edition, McGraw Hill, 1977, which is incorporated herein by reference.

As described above, DSP 130 may implement a rake receiver that includes multiple finger processors, each of which may include a frequency control loop and a timing control loop to correspondingly acquire and track the frequency and timing of signal instances assigned to the finger processors. Since the downconversion and a-to-D conversion (ADC) are the same for all multipath instances within the received signal, the frequency of the LO signal used for downconversion and the phase of the clock signal used for ADC sampling may be adjusted for one signal instance within the received signal. The signal instance may be selected as the strongest signal instance (e.g., 4.5dB) that exceeds a particular threshold.

The outer timing control loop may be enabled for one signal instance. For this signal example. Rotation and interpolation of the data samples is not required because their frequency and timing are adjusted accordingly based on the LO signal and the ADC sampling clock. For each other signal instance that may be concurrently processed along with the signal instance, rotator 212 may also be used to correct the residual frequency error of the signal instance, and interpolator 214 may be used to correct the residual timing error of the signal instance.

The techniques described herein may be implemented by various means. For example, the frequency-timing control loop may be implemented in hardware, software, or a combination thereof. For a hardware implementation, the elements of the frequency-timing control loop may be implemented in: one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, other electronic units designed to perform the functions described herein, or a combination thereof.

For a software implementation, all or portions of the frequency-timing control loop may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. The software codes may reside in a memory unit (e.g., memory 142 in fig. 1) and be executed by a processor (e.g., DSP 130 or controller 140). The memory unit may be implemented within the processor or external to the processor, in which case it can be communicatively coupled to the processor via various means as is known in the art.

The frequency-timing control loop may also be implemented in a combination of hardware and software. For example, hardware may be used to derive the pilot symbols, and software may be used to implement the frequency discriminator, the frequency loop filter, and the timing loop filter.

Headings are included herein for reference and to help locate the sections. These headings are not intended to limit the concepts described below and these concepts may apply to other subsections of the entire specification.

The previous description of the preferred embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of the inventive faculty. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (37)

1. A frequency-timing control loop, comprising:

a timing control loop for processing the data samples for the received signal to derive a first control indicative of timing error within the data samples for a particular signal instance within the received signal; and

a frequency control loop coupled to the timing control loop and including

A frequency discriminator for deriving a second control indicative of a frequency error in the data samples for the signal instance, an

A first loop filter for filtering the first and second controls to provide a third control for adjusting the frequency and phase of a periodic signal used to process the received signal to provide data samples.

2. The frequency-timing control loop of claim 1, wherein the third control is for adjusting a frequency of a Local Oscillator (LO) signal used to downconvert the received signal from RF to baseband.

3. The frequency-timing control loop of claim 2, wherein the third control is further configured to adjust a phase of a clock signal used to digitize the downconverted signal to provide the data samples.

4. The frequency-timing control loop of claim 3, wherein the clock signal is derived by dividing the LO signal

5. The frequency-timing control loop of claim 3, wherein the phase of the clock signal is adjusted to maximize a signal-to-interference-and-noise ratio (SINR) of the data samples of the signal instance.

6. The frequency-timing control loop of claim 1, wherein the first control from the timing control loop is enabled if the signal instance has a signal strength that exceeds a particular threshold.

7. The frequency-timing control loop of claim 1, wherein the first control from the timing control loop is derived based on a non-linear function.

8. The frequency-timing control loop of claim 7, wherein the first control is set to zero if the timing error is less than a first threshold.

9. The frequency-timing control loop of claim 7, wherein the first control is set to a particular maximum value if the timing error exceeds the second threshold.

10. The frequency-timing control loop of claim 7, wherein the first control is set to zero if the timing error is less than a first threshold, the first control is set to a specified maximum value if the timing error exceeds a second threshold, and the timing error is linearly related to the timing error if the timing error is between the first and second thresholds.

11. The frequency-timing control loop of claim 1, wherein the timing control loop comprises:

a timing discriminator for processing the data samples to provide a timing error metric; and

a second loop filter for filtering the timing error metric.

12. The frequency-timing control loop of claim 11, wherein the timing discriminator is implemented as an early-late detector.

13. The frequency-timing control loop of claim 11, wherein the timing control loop further comprises

A transfer gain element for applying a non-linear function to the output of the second loop filter to provide a first control.

14. The frequency-timing control loop of claim 11, wherein the second loop filter is implemented as a second order loop filter.

15. The frequency-timing control loop of claim 1, wherein the first loop filter is implemented as a first order loop filter.

16. The frequency-timing control loop of claim 1, wherein the tracking bandwidth of the first control is at least two times smaller than the tracking bandwidth of the first control.

17. A frequency-timing control loop, comprising:

the timing control loop comprises

A timing discriminator for processing data samples for a received signal to provide a timing error metric;

a first loop filter for filtering the timing error metric, an

A transfer gain element for applying a non-linear function to an output of the first loop filter to provide a first control indicative of a timing error in the data samples for a particular signal instance in the received signal; and

a frequency control loop coupled to the timing control loop and including

A frequency discriminator for deriving a second control indicative of a frequency error within the data samples for the signal instance; and

a second loop filter for filtering the first and second controls to provide a third control to adjust the frequency and phase of a periodic signal used to process the received signal to provide data samples.

18. In a wireless communication system, a method for acquiring and tracking frequency and timing of signal instances within a received signal, comprising:

first processing data samples of the received signal to provide a first control indicative of a timing error within the data samples for the signal instance;

second processing the data samples to provide a second control indicative of a frequency error within the data samples for the signal instance; and

the first and second controls are filtered to provide a third control for adjusting the frequency and phase of a periodic signal used to process the received signal to provide data samples.

19. The method of claim 18, wherein the second processing comprises

The data samples are processed with a frequency discriminator to provide a second control.

20. The method of claim 18, wherein the first processing comprises

Processing the data samples with a timing discriminator to provide a timing error metric; and

the timing error metric is filtered with a first loop filter.

21. The method of claim 20, wherein the first processing further comprises:

a non-linear function is applied to the output of the first loop filter to provide a first control.

22. The method of claim 18, further comprising:

estimating a signal strength of the signal instance; and

if the estimated signal strength exceeds a certain threshold, the first control is enabled.

23. The method of claim 18, wherein multiple signal instances within the received signal are concurrently processed, and wherein the frequency and phase of the periodic signal are adjusted to obtain frequency and timing lock on a single selected signal instance.

24. The method of claim 23, wherein the selected signal instance has a highest signal strength among a plurality of signal instances.

25. The method of claim 18, further comprising:

adjusting a frequency of a Local Oscillator (LO) signal based on a third control, wherein the LO signal is used to downconvert a received signal from RF to baseband.

26. The method of claim 25, further comprising:

adjusting a phase of a clock signal based on a third control, wherein the clock signal is used to digitize the downconverted signal to provide data samples.

27. The method of claim 26, further comprising:

the LO signal is divided to provide a clock signal.

28. A frequency-timing control loop, comprising:

means for deriving a first control indicative of a timing error within the data samples for a particular signal instance within the received signal;

means for deriving a second control indicative of a frequency error within the data samples for the signal instance; and

means for filtering the first and second controls to provide a third control for adjusting the frequency and phase of a periodic signal used to process the received signal to provide data samples.

29. An integrated circuit, comprising:

a timing control loop for processing the data samples for the received signal to derive first controls indicative of timing errors in the data samples for specific signal instances within the received signal; and

a frequency control loop coupled to the timing control loop and including

A frequency discriminator for deriving a second control indicative of a frequency error within the data samples for the signal instance; and

a first loop filter for filtering the first and second controls to provide a third control for adjusting the frequency and phase of a periodic signal used to process the received signal to provide data samples.

30. The integrated circuit of claim 29, further comprising:

a detector for estimating a signal strength of the signal instance, and wherein the first control is enabled if the estimated signal strength exceeds a particular threshold.

31. A receiver unit in a wireless communication system, comprising:

a front end unit for processing the received signal to provide data samples; and

a digital signal processor including a frequency-timing control loop for deriving a first control indicative of a timing error within data samples for a particular signal instance within a received signal, deriving a second control indicative of a frequency error within data samples for the signal instance, and filtering the first and second controls to provide a third control for adjusting the frequency and phase of a periodic signal used to process the received signal to provide the data samples.

32. The receiver unit of claim 31, further comprising:

a signal generator to adjust a frequency of a Local Oscillator (LO) signal based on a third control, wherein the LO signal is used by a front-end unit to downconvert a received signal from RF to baseband.

33. The receiver unit of claim 32, wherein the signal generator is further operative to adjust a phase of a reference signal based on a third control, wherein the reference signal is operative to derive a clock signal used by the front end unit to digitize the downconverted signal to provide the data samples.

34. A terminal comprising the receiver unit of claim 31.

35. A base station comprising the base station of claim 31.

36. Receiver apparatus in a wireless communication system, comprising:

means for downconverting a received signal with a Local Oscillator (LO) signal to provide a downconverted signal;

means for digitizing the down-converted signal with a clock signal to provide data samples;

means for deriving a first control indicative of a timing error within the data samples for a particular signal instance within the received signal;

means for deriving a second control indicative of a frequency error within the data samples for said signal instance;

means for filtering the first and second controls to provide a third control;

means for adjusting the frequency of the LO signal based on a third control; and

and means for adjusting the phase of the clock signal based on a third control.

37. A terminal, comprising:

a signal generator for providing a Local Oscillator (LO) signal and a reference signal;

a clock generator for providing a clock signal based on a reference signal;

a front-end unit to downconvert a received signal based on an LO signal and to digitize the downconverted signal based on a clock signal to provide data samples; and

a digital signal processor comprising a frequency-timing control loop for deriving a first control indicative of timing error within data samples for a particular signal instance within a received signal, deriving a second control indicative of frequency error within data samples for the signal instance, and filtering the first and second controls to provide a third control for adjusting the frequency and phase of a periodic signal used to process the received signal to provide the data samples.