HK1078179B - Transceiver using a harmonic rejection mixer - Google Patents

Description

Transceiver using harmonic rejection mixer

Background

RELATED APPLICATIONS

This application has priority to U.S. provisional application serial No. 60/651869, filed on 25/1/2002.

FIELD

The disclosed methods and apparatus relate generally to wireless communications and, more particularly, to wireless communication transceivers.

Description of the related Art

Wireless communication devices are increasingly being manufactured to meet the wide public. There is also increasing pressure on manufacturers to reduce costs by providing highly integrated transceiver circuits. It is desirable to minimize circuit complexity not only to reduce the size and thus cost of the integrated circuit chip, but also to reduce power consumption. Power consumption is particularly important for small handheld devices such as mobile phones. It would also be desirable to provide a highly integrated circuit capable of operating in two or more frequency bands, such as the respective frequency bands used for EGSM (global system for mobile communications), DCS (digital cellular system) and PCS (personal communications service).

Wireless communication devices typically use digital phase modulation. EGSM, DCS and PCS in particular may use a minimum frequency shift keying modulation format with a substantially constant amplitude envelope. Typically, modulated FR (radio frequency) signals are generated from in-phase and quadrature-phase baseband signals. For example, to generate an envelope of approximately constant amplitude, the in-phase and quadrature-phase baseband signals are band-limited binary data streams that are mutually offset in time by half a bit period and are amplitude modulated such that the sum of the squares of the in-phase amplitude and the quadrature-phase amplitude is constant. In effect, the desired in-phase and quadrature-phase baseband signals are synthesized as a function of the data to be transmitted. A pair of digital-to-analog converters convert the digitally combined in-phase and quadrature-phase signals into corresponding analog signals for application to a quadrature modulator capable of generating a modulated RF signal.

Although the quadrature modulator may directly generate the modulated RF signal at the frequency to be transmitted, it is advantageous to generate the modulated RF signal at a lower frequency for up-conversion to the frequency to be transmitted. This two-step up-conversion process enables the quadrature modulator to meet desired performance requirements at lower frequencies, such as tolerable deviations from ideal phase balance and quadrature phase offset. For example, the integrated digital circuit can easily generate a quadrature-phase carrier at lower frequencies, and the quadrature modulator can be configured as a harmonic rejection mixer to reduce the parasitic effects of the digitally generated quadrature-phase carrier.

Two-step up-conversion of a wireless transmitter is shown in us patent 6240142 to Kaufman et al. The use of harmonic Rejection Mixers within this structure is shown in the Weldon et al paper entitled "A1.75GHz high-Integrated Narrow Band CMOS Transmitter with harmonic-Rejection Mixers", 2001 IEEE International Solid-State computers Conference, 2.6.2001, pp.160-161, 442. While these circuits provide improvements in highly integrated direct conversion transmitter architectures, there is still a need to reduce circuit complexity to reduce power consumption of handheld communication devices. The two-step upconversion architecture of Kaufman et al uses multiplication by a high frequency balanced modulator, comprising two balanced modulators operating at the RF transmit frequency. Balanced modulators consume significant power consumption.

SUMMARY

Methods and apparatus disclosed herein include a transmitter circuit. The transmitter circuit includes a local oscillator for generating a signal at a multiple of the intermediate frequency, and a quadrature modulator harmonic rejection mixer for modulating the in-phase baseband signal and the quadrature-phase baseband signal to generate an intermediate frequency signal based on the signal at the multiple of the intermediate frequency. The transmitter circuit further includes a filter for generating a filtered intermediate frequency signal based on the intermediate frequency signal, and an RF output offset phase-locked loop for generating an RF transmit signal based on the filtered intermediate frequency signal and a signal at a multiple of the intermediate frequency.

According to another embodiment, the transmitter circuit includes a local oscillator for generating a signal at a multiple of the intermediate frequency, and a quadrature modulator for modulating the in-phase baseband signal and the quadrature-phase baseband signal to generate the intermediate frequency signal based on the signal at the multiple of the intermediate frequency. The transmitter circuit further includes a filter for generating a filtered intermediate frequency signal based on the intermediate frequency signal, and an RF output offset phase-locked loop for generating an RF transmit signal based on the filtered intermediate frequency signal and a signal at a multiple of the intermediate frequency. The local oscillator includes a phase-locked loop digital synthesizer with digital circuitry for channel selection, and the local oscillator generates a frequency equal to the frequency of the RF transmit signal when the phase-locked loop digital synthesizer achieves a phase-locked condition multiplied by a factor equal to a multiple divided by a sum of one plus a multiple.

In accordance with another aspect, the disclosed methods and apparatus provide multi-band wireless communication transceiver circuits for use in EGSM (global system for mobile communications), DCS (digital cellular system), and PCS (personal communications service). The transceiver circuit includes a channel selection voltage controlled oscillator, a two-step up-conversion multiband wireless transmitter for EGSM transmission and DCS or PCS transmission on a transmission channel selected by the channel selection voltage controlled oscillator, and a direct conversion multiband wireless receiver for EGSM reception and DCS or PCS reception of a reception channel selected by the channel selection voltage controlled oscillator.

Brief description of the drawings

The features, nature, and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout and wherein:

FIG. 1 is a block diagram of a first embodiment of the disclosed method and apparatus, in which an image reject offset mixer operating at an RF transmit frequency within an RF output offset phase locked loop downconverts the RF transmit signal to an intermediate frequency using a local oscillator signal;

FIG. 2 is a block diagram of a second embodiment of the disclosed method and apparatus, in which an image reject offset mixer operating at an RF transmit frequency within an RF output offset phase locked loop uses an intermediate frequency signal to down-convert the RF transmit signal to a 4 times intermediate frequency;

FIG. 3 is a schematic diagram of a conventional balanced modulator Gilbert cell for the quadrature modulator harmonic rejection mixer of FIG. 5;

FIG. 4 is a schematic diagram of a gated latch cell for use within the quadrature modulator harmonic rejection mixer of FIG. 5;

FIG. 5 is a block diagram of a quadrature modulator harmonic rejection mixer, as used in FIGS. 1 and 2;

fig. 6 is a block diagram showing how the RF local oscillator signal of a direct conversion receiver is generated from the VC0 signal of the transmitter local oscillator of fig. 1 or fig. 2 to provide a wireless telecommunications transceiver;

FIG. 7 is a schematic diagram of a single sideband mixer used in FIG. 6;

FIG. 8 is a schematic diagram of the digital mixing and multiplexing device introduced in FIG. 6; and

fig. 9 is a block diagram of another construction of a local oscillator that includes a fractional-N phase locked loop.

While the disclosed method and apparatus are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that there is no intention to limit the form of the invention to the specific forms shown, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.

Detailed Description

Fig. 1 illustrates a first embodiment of a wireless communication transmitter using a two-step upconversion architecture in accordance with the disclosed method and apparatus. The transmitter comprises a local oscillator 10, a quadrature modulator harmonic rejection mixer 11, a switchable Intermediate Frequency (IF) filter 12 and an RF output offset phase locked loop 13.

The local oscillator 10 generates a digital signal at four times the intermediate frequency local oscillator frequency. The digital signal is supplied to a quadrature modulator harmonic rejection mixer 11 and an RF output offset phase locked loop 13. The resulting output from the local oscillator 10 is one fifth the RF transmit frequency output by the RF output offset phase locked loop 13.

The local oscillator 10 includes a conventional channel selection integer or fractional-N phase-locked loop 14. The phase locked loop 14 includes a Voltage Controlled Oscillator (VCO) 15. (the fractional-N phase-locked loop circuit is shown in fig. 9, which will be described further below). The local oscillator 10 is used to generate a frequency equal to the RF transmit signal frequency multiplied by a factor equal to the multiple divided by the sum of one plus the multiple when the phase-locked loop digital synthesizer reaches a phase-locked condition.

The transmitter architecture of fig. 1 ensures that the RF output offset phase-locked loop 13 generates an RF transmission frequency that is 5/4 times the frequency of the EGSM and the local oscillator 10 in the DCS or PCS bands. Thus, the channel selection phase locked loop 14 controls the RF transmission channel selection, which is 160kHz channel steps when using a 19.2MHz crystal 16. The channel selection phase-locked loop 14 controls the RF transmission channel selection in a similar manner for the lower frequency EGSM band, although the step size would be twice that for the higher frequency band.

The transmitter circuitry in fig. 1 is capable of electronic switching over three RF transmit bands, including the 880-915MHz band of relatively lower EGSM services and two relatively higher bands, including the 1.710-1.785GHz band of DCS services and the 1.850-1.910GHz band of PCS services. To switch between the high and low bands, multiplexer 22 selects either the output of VCO15 for operation in the high band or the output of flip-flop 20 for operation in the lower band. When switching between bands, the upper cut-off frequency of the switchable IF filter 12 is also switched to be just above the upper intermediate frequency operating within the selected band. For EGSM services, the intermediate LO frequency ranges from 176 to 183 MHz. For DCS services, the intermediate frequency LO ranges from 342 to 357 MHz. For PCS service, the intermediate LO frequency is from 370 to 382 MHz. Thus, for EGSM services, the VCO15 generates frequencies from 1.408 to 1.464 GHz. For DCS services, the VCO15 generates frequencies from 1.368 to 1.428 GHz. For PCS service, VCO15 generates frequencies from 1.480 to 1.528 GHz.

As shown in fig. 1, the quadrature modulator harmonic rejection mixer 11 includes a divide-by-four circuit 23, an in-phase balanced modulator 24, a quadrature-phase balanced modulator 25, and a summer 26. These components 23, 24, 25 and 26 are constructed for harmonic rejection, as described below with reference to fig. 3 to 5, in order to reduce the requirements on the switchable IF filter 12. The harmonic rejection characteristics of the quadrature modulator 11 and the third order low pass characteristic of the switchable IF filter 12 ensure that the harmonics of the intermediate frequency signal are at least 65dB below the fundamental amplitude after reaching the RF output offset phase locked loop 13.

The reduced requirements for the switchable IF filter 12 enable the IF filter to be fully integrated into a single monolithic silicon integrated circuit chip which also contains the quadrature modulator 11 and other active components of the transmitter in fig. 1. For example, the switchable IF filter 12 is simply a third or fourth order low pass R-C active filter with a switchable upper cut-off frequency. For example, for the lower frequency EGSM band, the upper cutoff frequency is reduced by electrically switching the additional capacitance to the IF filter 12.

The RF output offset phase locked loop 13 includes a conventional VCO 27, a conventional Phase Detector (PD) and Frequency Phase Detector (FPD)28, and a conventional low pass loop filter 29 that generate the RF transmit signal. The RF output offset phase locked loop 13 further comprises an automatic level control amplifier 30, an image reject offset mixer 21 and a switchable IF filter 32. (the construction of the image reject offset mixer is similar to the construction of the single sideband mixer 122 shown in FIG. 6, described further below).

The automatic level control amplifier 30 ensures that the image reject offset mixer 31 will achieve linear mixing of the RF signal fed back from the VCO 27 over the input range of the image reject offset mixer, although there is some variation in the amplitude generated by the VCO. If an automatic level control amplifier is not used, the signal applied to the modulator is preferably pre-distorted according to an arctangent transfer function to avoid overdriving the modulator. The image reject offset mixer 31 mixes the RF signal with the 4X IFLO signal from the multiplexer 22 of the local oscillator 10 to generate sum and difference frequency signals at 9/5 of the RF transmit frequency at one stage intermediate LO frequency.

The switchable IF filter 32 selects the difference frequency signal from the image reject offset mixer 31. The switchable IF filter 32 has a cut-off frequency that can be switched between the relatively low EGSM band and the relatively high DCS and PCS bands. The switchable IF filter 32 may be similar to the switchable IF filter 12. Furthermore, the center frequency of VCO 27 is switched as a function of the selected frequency band so that the RF transmit frequency is greater than the frequency of the 4 XIF LO signal, ensuring that the RF output offset phase-locked loop quickly becomes locked to an RF transmit frequency five times the intermediate LO frequency.

In the transmitter of fig. 1, an RF output offset phase-locked loop 13 locks the signal frequency from the IF filter 12 and the 4X IF LO signal from the multiplexer 22 of the local oscillator 10. This may be accomplished by applying the signal from IF filter 12 to a conventional phase detector as well as frequency-phase detector 28, and applying a 4X LO signal to balanced modulator 31 operating at the RF transmit frequency.

In other embodiments, as shown in fig. 2, the 4X LO signal is applied to a conventional phase detector and frequency-phase detector 45, and the signal from the switchable IF filter 42 is applied to an image reject offset mixer operating at the RF transmit frequency. The transmitter circuit of fig. 2 further comprises a local oscillator 40 having the same construction as the local oscillator 10 in fig. 1, and a quadrature modulator harmonic rejection mixer 41 having the same construction as the quadrature modulator of fig. 1. The switchable IF filter 42 has the same construction as the switchable IF filter 12 of fig. 1. However, the transmitter circuit of fig. 2 includes an RF output offset phase-locked loop 43 that is different from the RF output offset phase-locked loop 13 of fig. 1.

The RF output offset phase locked loop 43 in fig. 2 includes a conventional VCO 44 operating at the RF transmit frequency, a conventional Phase Detector (PD) and Frequency Phase Detector (FPD)45 and a conventional low pass loop filter 46. The RF output offset phase locked loop 43 further comprises an automatic level control amplifier 47 with the same construction as the automatic level control amplifier 30 of fig. 1 and an image reject offset mixer 48 with the same construction as the balanced modulator 31 in fig. 1. However, the image rejection offset mixer 48 mixes the IF signal from the IF filter 42 with the RF transmit signal to generate a sum signal at a frequency of six fifths of the RF transmit frequency and a difference signal at four fifths of the RF transmit frequency. Preferably, the image reject offset mixer provides linear mixing of the IF signal and the RF transmission signal to reduce in-channel spurs (spurs) and inter-modulation distortion product terms and improve image rejection.

A Band Pass Filter (BPF)49 selects the difference signal at four fifths of the RF transmit frequency. At least the upper cut-off frequency of the band-pass filter can be switched between at least the lower frequency EGSM band and the higher frequency DCS and PCS bands. The selected difference signal from the band pass filter 49 is limited to a substantially constant amplitude within the limiter 50 and applied to the conventional phase detector as well as to the frequency phase detector 45. Phase detector and frequency-to-phase detector 45 compares the clipped difference signal frequency or phase with the frequency or phase of the 4 XLO signal from local oscillator 40.

In the most preferred form of construction, the balanced modulator and image reject offset mixers (24, 25, 31, 48) in fig. 1 and 2 use conventional bipolar transistor Gilbert cells. One such Gilbert cell designated 60 is shown in fig. 3 in order to identify the various inputs and outputs of the six Gilbert cells shown in fig. 5. In other words, each of the Gilbert cells shown in FIG. 5 has an output pair at the top of the cell, two digital inputs at the upper left of the cell, two analog inputs at the lower left of the cell, a current collector connection at the bottom of the cell, and the internal configuration shown in FIG. 3.

When conventional bipolar transistor Gilbert cells are used, it is convenient to integrate the Gilbert cells with polar logic circuits (ECLs) that couple current-mode emission on a common single-crystal silicon integrated circuit chip. The ECL circuit may use the same bias level as the Gilbert cell. For example, fig. 4 shows a schematic diagram of a gated latch cell designated 70. The data outputs (Q and Q) of the gated latch cell 70 are at the upper bias level for driving the digital inputs of the Gilbert cell. The set (S) and reset (R) inputs of the gated latch cell 70 operate at the upper bias level. The clock inputs (C and C-bar) operate at a lower bias level that is about one volt or more below the upper bias level. The lower bias level is also the bias level of the analog input of the Gilbert cell.

Fig. 5 shows how the Gilbert cell of fig. 3 and the gated latch cell of fig. 4 combine to form the quadrature modulator harmonic rejection mixer 11 of fig. 1. Four gated latch units 81, 82, 83 and 84 are cascaded in series to form a divide-by-four shift register counter 23. The gated latch cells 81 and 82 together comprise one master-slave delay flip-flop and the gated latch cells 83 and 84 comprise the other master-slave delay flip-flop. The logic inversion occurs on the feedback path from the Q and Q outputs of the fourth gated latch cell 84 to the S and R inputs of the first gated latch cell 81. During operation, divide-by-four shift register counter 23 provides four phases of the digital clock signal at the intermediate LO frequency. Each of the gated latch cells 81, 82, 83 and 84 provides one of the four phases of the corresponding digital clock signal at the intermediate LO frequency.

The in-phase modulator 24 includes three Gilbert cells 85, 86 and 87 driven by phases 1, 2 and 3, respectively, of the LO digital clock signal. The Gilbert cell 86 has a current collector weighted by a factor of the square root of two relative to the current collectors of the Gilbert cells 85 and 87. The weighting of the current collectors is done in a conventional manner using current mirroring techniques. The use of more than one Gilbert cell for the in-phase modulator 24, along with the Gilbert cells 85, 86, and 87 weighted by the corresponding digital clock phases and current collectors, provides the desired harmonic rejection.

The quadrature phase modulator 25 is constructed in a similar manner to the in-phase modulator 24 except that the Gilbert cells 88, 89 and 90 are driven by respective clock phases that are delayed by 90 degrees from the LO clock signal as compared to the Gilbert cells 85, 86 and 87.

The summer 26 is provided by a parallel connection of the outputs of the Gilbert cells 85 to 90 to a pair of shared load resistors 91 and 92. The load resistors 91 and 92 generate a differential voltage proportional to the sum of the differential currents collected by the Gilbert cell.

As described above, a two-step up-conversion wireless communication transmitter is described that allows for high integration on a single crystal silicon integrated circuit chip. The quadrature modulator uses a harmonic rejection mixer to reduce IF filtering requirements. Furthermore, the quadrature modulator operates at an intermediate frequency that enables multiple local oscillator signal phases to be digitally generated to reduce quadrature modulator phase errors. The local oscillator includes a phase locked loop that allows the use of conventional channel selection digital circuitry, reduces LO integrated phase noise and reduces switching time.

It will be obvious that the circuit shown in the figure can be modified in various ways. For example, an N-channel enhancement mode field effect transistor may be directly replaced by an NPN transistor as shown in fig. 3 and 4. It is desirable to use gallium arsenide field effect transistors in order to be able to operate at higher RF transmission frequencies. Alternatively, it is desirable to use silicon field effect transistors to integrate the wireless transmitter with CMOS digital circuits using standard CMOS processing. If standard CMOS processing is used, conventional CMOS gated latch cells can be replaced with the gated latch cells shown in FIG. 4.

Fig. 1 and 2 show multi-band circuits, which may be simplified for operation only on the lower EGSM band or the higher DCS and PCS bands. In this case the multiplexer (22 in fig. 1) may be eliminated, the IF filter (12 in fig. 1 or 42 in fig. 2) need not be switchable, and the RF output VCO (44 in fig. 1 or 2) need not be switched at its center frequency between the lower and upper bands.

Figure 6 shows how it is possible to generate a local oscillator signal from a receive local oscillator generator circuit for a direct conversion receiver through a channel selective phase locked loop to provide a wireless telecommunications transceiver. As shown in fig. 6, the receive local oscillator generator circuit includes a divide-by-four circuit 121 that divides the signal from the VCO15 at frequency Fs by four in frequency. The single sideband mixer 122 mixes the VCO signal with the output of the divide-by-four circuit to generate a signal at a frequency of 5/4Fs, as described further below with reference to fig. 7. The divide-by-2 digital hybrid circuit 123, further shown and described below with reference to fig. 8, divides the output frequency of the single sideband mixer 122 by two. A multiplexer 124 is further shown and described below with reference to fig. 8, selecting either the output of the single sideband mixer (for the DCS or PCS case) or the output of the divider 123 (for the EGSM case) to generate the receiver local oscillator signal. The PCS or DCS receives the local oscillator signal and excites the analog hybrid circuit 125 to generate respective in-phase (0 degree) and quadrature-phase (90 degree) signals that are applied to respective in-phase demodulator 126 and quadrature-phase demodulator 127. Suitable analog hybrids are discussed further below with reference to fig. 7. The in-phase (0 degree) and quadrature phase (90 degree) signals of the GSM receive local oscillator signal circuit are applied from divider 123 through multiplexer 124 to respective in-phase demodulator 128 and quadrature-phase demodulator 129. Each demodulator 126, 127, 128, and 129 may be a single Gilbert cell as shown in fig. 3. The in-phase demodulator 126 demodulates the DCS or PCS RF receive signal to generate an in-phase baseband signal I ', and the quadrature-phase demodulator 127 demodulates the DCS or PCS RF receive signal to generate a quadrature-phase baseband signal Q'. The in-phase demodulator 128 demodulates the EGSM RF receive signal to generate an in-phase baseband signal I ', and the quadrature-phase demodulator 129 may demodulate the EGSM RF receive signal to generate a quadrature-phase baseband signal Q'.

In the general operation of the transceiver in fig. 6, the receiver and transmitter provide duplex telephone operation, but the receiver and transmitter do not operate simultaneously. Also, the transmitter and the receiver operate in a time-sharing manner transparent to the user. This allows the frequency Fs of the VCO to be changed at the time of transmission and reception switching. For example, the operating frequencies (in MHz) are shown in the following table:

transmission of

	RF low	RF high	Fs is low	Fs is high	IF low	IF high
							EGSM	880	915	1408	1464	176	183
DCS	1710	1785	1368	1428	342	357
							PCS	1850	1910	1480	1528	370	382

Receiving

	RF low	RF high	Fs is low	Fs is high
					EGSM	925	960	1480	1536
DCS	1805	1880	1444	1504
					PCS	1930	1990	1544	1592

Fig. 7 shows a schematic diagram of the single sideband mixer 122. The VCO (15 of fig. 6) output at frequency Fs is applied to the pair of buffers 131 and 132. The buffer 132 supplies a clock signal to the divide-by-four circuit 121, which is a register similar to the shift register 23 in fig. 5. The divide-by-four circuit provides a complementary pair of in-phase clocks to a first Gilbert cell 134 and a complementary pair of quadrature-phase clocks at a frequency of Fs/4 to a second Gilbert cell 135. The buffer 131 drives an analog hybrid circuit 136 that provides transistor/capacitance lead/lag connections to the Gi lbert cell 135. Each lead/lag connection provides a phase shift of more or less than 45 degrees such that a first Gilbert cell receives an in-phase signal at a frequency Fs and a second Gilbert cell receives a quadrature-phase signal at the frequency Fs. The outputs of the two Gilbert cells 134, 135 are connected in parallel so that the lower single sideband signals at 3/4Fs from the Gilbert cells cancel and the upper sideband signals at 5/4Fs from the Gilbert cells add constructively.

Although the single sideband modulator 122 shows an analog hybrid circuit 136 for generating complementary in-phase and quadrature-phase signals at a frequency Fs, the VCO (15 in fig. 6) may also be constructed to generate such in-phase and quadrature-phase signals. For example, the frequency selective element within the VCO may be an analog or digital delay line within the feedback circuit, and the analog or digital delay line may be tapped at a zero degree phase position to provide an in-phase signal and a quadrature-phase signal at a 90 degree phase position. For example, such a digital delay line may be constructed with four ECL inverters in series, in a manner similar to shift register 23 of fig. 5, by replacing each gated latch within the shift register with a corresponding ECL inverter.

Fig. 8 shows the divide-by-two digital mixer 123 and the multiplexer 124 introduced in fig. 6 in more detail. The divide-by-two digital mixer includes a first S-R latch 141 and a second S-R latch 142. Latches 141 and 142 are connected to form a master-slave class D flip-flop with negative feedback as a function of divide-by-two. The first S-R latch provides an in-phase output and the second S-R latch provides a quadrature-phase output. Multiplexer 124 includes a first transmission gate 143 enabled by a logic low control signal, a second transmission gate 144 enabled by a logic high control signal, and a third transmission gate 145 enabled by a logic high control signal.

Fig. 9 shows a local oscillator including a fractional-N phase locked loop. In this example, the fractional-N phase locked loop includes channel selection digital circuitry 144, which was originally used to generate the RF transmission frequency. To generate the desired 4 IF LO frequency, a multiplier 149 is inserted in the feedback path from the VCO142 to the input of the digital circuit 144. The frequency (Fs) of VCO142 is divided by two by first flip-flop 146 and then likewise divided by two in second flip-flop 147, so that second flip-flop 147 outputs a digital signal at one-quarter the frequency (Fs) of VCO 142. The digital signal is applied to a multiplier 149 which acts as an exclusive or gate implementing fractional multiplication. The total delay through the two toggle flip-flops 146 and 147 is one quarter of the frequency (Fs) period of the VCO 142. Thus, the multiplier 149 adds one additional logic transfer for every four transfers within the VCO signal, and the signal fed back from the multiplier 149 to the digital circuitry 144 of the phase locked loop 141 increases in instantaneous frequency by a factor of 5/4.

The signal fed back from the multiplier to the phase locked loop is divided low by digital circuits 144 and these digital circuits are responsive to the number of transitions in the signal from multiplier 149. Thus, when the phase locked loop 141 is phase locked, the VCO142 generates a signal at a frequency (Fs) that is less than 4/5 times the frequency that the phase locked loop would have generated. Multiplexer 148 provides the 4 IF LO signals. The multiplexer 148 selects the signal Fs for the DSC and PCS bands and selects the output of the first toggle flip-flop 146 for the EGSM band.

Claims (36)

1. A wireless communication transmitter circuit comprising, in combination:

a local oscillator for generating a signal at a multiple of the intermediate frequency;

a quadrature modulator harmonic rejection mixer that modulates an in-phase baseband signal and a quadrature-phase baseband signal to generate an intermediate frequency signal according to a signal at the frequency multiplication of the intermediate frequency;

a filter for generating a filtered intermediate frequency signal from the intermediate frequency signal; and

an RF output offset phase-locked loop which generates an RF transmission signal according to the filtered intermediate frequency signal and the signal at the frequency multiplication position of the intermediate frequency;

wherein the local oscillator generates a frequency equal to the frequency of the RF transmit signal multiplied by a multiple of the frequency multiplier and divided by a sum of one plus the multiple.

2. The wireless communication transmitter circuit of claim 1, wherein the local oscillator comprises a phase locked loop and a voltage controlled oscillator.

3. The wireless communication transmitter circuit of claim 2, wherein the phase-locked loop is an integer-N phase-locked loop.

4. The wireless communication transmitter circuit of claim 2, wherein the phase-locked loop is a fractional-N phase-locked loop.

5. The wireless communication transmitter circuit of claim 1, wherein the local oscillator is switchable to vary the intermediate frequency by a factor of 2, and the filter is switchable to generate a filtered intermediate frequency signal when the intermediate frequency is varied by a factor of 2.

6. The wireless communication transmitter circuit of claim 1, wherein the filter is a third order low pass filter.

7. The wireless communication transmitter circuit of claim 1, wherein the filter is a fourth order low pass filter.

8. The wireless communication transmitter circuit of claim 1, wherein the quadrature modulator harmonic rejection mixer comprises a shift register counter for generating a plurality of phases of the digital signal at the intermediate frequency, and a plurality of Gilbert cells, each Gilbert cell responsive to a respective phase of the digital signal at the intermediate frequency.

9. The wireless communication transmitter circuit of claim 1, wherein the RF output offset phase-locked loop includes a voltage controlled oscillator that generates the RF transmit signal based on a frequency control signal; the frequency mixer is used for carrying out down-conversion on the RF transmitting signal by using the signal at the frequency multiplication of the intermediate frequency to generate a difference frequency signal; a phase detector is included for comparing the phase of the difference frequency signal with the phase of the filtered intermediate frequency signal to generate a frequency control signal.

10. The wireless communication transmitter circuit of claim 9, wherein the offset mixer is a double balanced mixer.

11. The wireless communication transmitter circuit of claim 10, wherein the offset mixer is an image reject double balanced mixer.

12. The wireless communication transmitter circuit of claim 1, wherein the RF output offset phase-locked loop includes a voltage controlled oscillator that generates the RF transmit signal based on a frequency control signal; comprising an offset mixer for down-converting the RF transmit signal with the filtered intermediate frequency signal to generate a difference frequency signal; a phase detector is included for comparing the phase of the difference signal with the phase of the signal at multiples of the intermediate frequency to generate a frequency control signal.

13. The wireless communication transmitter circuit of claim 12, wherein the offset mixer is a double balanced mixer.

14. The wireless communication transmitter circuit of claim 13, wherein the offset mixer is an image reject double balanced mixer.

15. A wireless communication transmitter circuit comprising, in combination:

a local oscillator for generating a signal at four times an intermediate frequency;

a quadrature modulator harmonic rejection mixer that modulates the in-phase baseband signal and the quadrature-phase baseband signal according to a signal at four times the intermediate frequency to generate an intermediate frequency signal;

a filter for generating a filtered intermediate frequency signal from the intermediate frequency signal; and

an RF output offset phase-locked loop which generates an RF sending signal according to the filtered intermediate frequency signal and the intermediate frequency quadruple signal;

wherein the local oscillator comprises a phase locked loop with digital circuitry for channel selection and the local oscillator generates a frequency equal to the frequency of the RF transmit signal multiplied by a multiple of the frequency multiplication and divided by a sum of one plus the multiple.

16. The wireless communication transmitter circuit as claimed in claim 15, wherein said local oscillator comprises a phase locked loop and a voltage controlled oscillator.

17. The wireless communication transmitter circuit of claim 15, wherein the local oscillator comprises a flip-flop that generates a signal at half the frequency generated by the voltage controlled oscillator; also included is a multiplexer having a first input coupled to the voltage controlled oscillator, a second input coupled to the flip-flop, and an output for providing a signal at four times the intermediate frequency, and the multiplexer selects either the frequency generated by the voltage controlled oscillator or half the frequency generated by the voltage controlled oscillator to be four times the frequency of the IF local oscillator based on a selection signal.

18. The wireless communication transmitter circuit of claim 15, wherein the local oscillator is switchable to vary the intermediate frequency by a factor of 2, and the filter is switchable to generate a filtered intermediate frequency signal when the intermediate frequency is varied by a factor of 2.

19. The wireless communication transmitter circuit of claim 15, wherein the filter is a third order low pass filter.

20. The wireless communication transmitter circuit of claim 15, wherein the filter is a fourth order low pass filter.

21. The wireless communication transmitter circuit of claim 15, wherein the quadrature modulator harmonic mixer comprises a shift register counter with four gated latches, each of the four gated latches generating one of four phases of the digital signal at the intermediate frequency, and six Gilbert cells, each Gilbert cell responsive to a respective phase of the digital signal at the intermediate frequency.

22. The wireless communication transmitter circuit of claim 15, wherein the RF output offset phase-locked loop includes a voltage controlled oscillator that generates the RF transmit signal based on a frequency control signal; an offset mixer for down-converting the RF transmit signal with a signal at four times the intermediate frequency to generate different frequency signals; a phase detector is included for comparing the phase of the difference frequency signal with the phase of the filtered intermediate frequency signal to generate a frequency control signal.

23. The wireless communication transmitter circuit of claim 15, wherein the RF output offset phase-locked loop includes a voltage controlled oscillator that generates the RF transmit signal based on a frequency control signal; an offset mixer for down-converting the RF transmit signal with the filtered intermediate frequency signal to generate a difference frequency signal; a phase detector is included for comparing the difference frequency signal phase with the signal phase at four times the intermediate frequency to generate a frequency control signal.

24. A wireless communication transceiver circuit comprising, in combination:

a local oscillator including a channel selection voltage controlled oscillator for generating a signal at an intermediate frequency multiplication for transmission and for generating a receiver local oscillator signal;

a quadrature modulator for modulating the in-phase baseband signal and the quadrature-phase baseband signal according to the signal at the intermediate frequency multiplication to generate an intermediate frequency signal;

the RF output offset phase-locked loop generates an RF sending signal according to the intermediate frequency signal and a signal at the intermediate frequency doubling position;

the direct conversion receiver is responsive to a receiver local oscillator signal;

wherein the local oscillator comprises a receiver local oscillator generator circuit for generating a receiver local oscillator signal in accordance with a channel selection of the channel selection voltage controlled oscillator, and the local oscillator generates a frequency equal to a frequency of the RF transmit signal multiplied by a multiple of the frequency multiplication and divided by a sum of one and the multiple.

25. The wireless communication transceiver circuit of claim 24, wherein the receiver local oscillator generator circuit includes a divider for dividing the frequency generated by the channel selection voltage controlled oscillator by four, and a single sideband mixer for scaling the frequency generated by the channel selection voltage controlled oscillator by five times by four times based on the divider and the channel selection voltage controlled oscillator.

26. The wireless communication transceiver circuit of claim 25, wherein the receiver local oscillator generator circuit further comprises a flip-flop that generates a signal at half the frequency generated by the single sideband mixer; also included is a multiplexer having a first input coupled to the single sideband mixer, a second input coupled to the flip-flop, and an output for providing a receiver local oscillator signal to the direct conversion receiver, and the multiplexer selects either the frequency generated by the single sideband mixer or half of the frequency generated by the single sideband mixer as the receiver local oscillator frequency signal based on a selection signal.

27. A multi-band wireless communication transceiver circuit for EGSM and DCS or PCS operation, comprising, in combination:

a local oscillator including a channel selection voltage controlled oscillator for generating a signal at a multiple of an intermediate frequency for the transmitter, the intermediate frequency being switchable between EGSM operation and DCS or PCS operation;

a quadrature modulator harmonic rejection mixer that modulates the in-phase baseband signal and the quadrature-phase baseband signal according to a signal at an intermediate frequency multiplication to generate an intermediate frequency signal;

a switchable filter for generating a filtered intermediate frequency signal according to the intermediate frequency signal, the switchable filter being switchable between EGSM transmission and DCS or PCS transmission;

the RF output offset phase-locked loop generates an RF sending signal according to the filtered intermediate frequency signal and the intermediate frequency doubling position signal;

the direct conversion receiver is used for EGSM receiving and DCS or RCS receiving according to the local oscillator signal;

wherein the local oscillator comprises a receiver local oscillator generator circuit for generating a receiver local oscillator signal in accordance with a channel selection of the channel selection voltage controlled oscillator, and the local oscillator generates a frequency equal to a frequency of the RF transmit signal multiplied by a multiple of the frequency multiplication and divided by a sum of one and the multiple.

28. The wireless transceiver circuit of claim 27, wherein the receiver local oscillator generator circuit includes a divider for dividing the frequency generated by the channel selection voltage controlled oscillator by four, and a single sideband mixer for scaling the frequency generated by the channel selection voltage controlled oscillator by five divided by four times based on the divider and the channel selection voltage controlled oscillator.

29. The wireless transceiver circuit of claim 27, wherein the receiver local oscillator generator circuit further comprises a flip-flop that generates a signal at half the frequency generated by the single sideband mixer; also included is a multiplexer having a first input coupled to the single sideband mixer, a second input coupled to the flip-flop, and an output for providing a receiver local oscillator signal to the direct conversion receiver, and the multiplexer selects either the frequency generated by the single sideband mixer or half of the frequency generated by the single sideband mixer as the receiver local oscillator frequency signal based on a selection signal.

30. A multi-band wireless communication transceiver circuit for EGSM and DCS or PCS operation comprising, in combination:

a channel selection voltage controlled oscillator;

the two-step up-conversion multiband wireless transmitter is used for EGSM transmission and DCS or PCS transmission after the channel selection voltage-controlled oscillator selects a transmission channel;

a direct conversion multiband wireless receiver for EGSM reception and DCS or PCS reception of a reception channel selected by a channel selection voltage-controlled oscillator;

a quadrature modulator harmonic rejection mixer for modulating the in-phase baseband signal and the quadrature-phase baseband signal for generating an intermediate frequency signal;

a switchable filter for generating a filtered intermediate frequency signal according to the intermediate frequency signal, the switchable filter being switchable between EGSM transmission and DCS or PCS transmission; and

an RF output offset phase-locked loop for generating an RF transmit signal from the filtered intermediate frequency signal;

wherein the channel selection voltage controlled oscillator generates a frequency equal to the frequency of the RF transmit signal multiplied by the multiple and divided by a sum of one plus the multiple.

31. The wireless transceiver circuit of claim 30, wherein the switchable filter is a third order low pass filter.

32. The wireless transceiver circuit of claim 30, wherein the switchable filter is a fourth order low pass filter.

33. The wireless transceiver circuit of claim 30, wherein for EGSM and DCS or PCS operation the local oscillator generates a signal at four times a local oscillator frequency of a quadrature modulator harmonic rejection mixer, the quadrature modulator harmonic rejection mixer divides the frequency of the signal generated by the channel selection voltage controlled oscillator by four, and the RF offset phase locked loop generates an RF transmit frequency from the signal generated by the channel selection voltage controlled oscillator, the frequency being five quarters of the frequency of the signal generated by the channel selection voltage controlled oscillator.

34. The transceiver circuit of claim 30, wherein the wireless transceiver comprises a receiver local oscillator generator circuit and a direct conversion receiver.

35. The wireless transceiver circuit of claim 34, wherein the receiver local oscillator generator circuit includes a divider for dividing the frequency generated by the channel selection voltage controlled oscillator by four, and a single sideband mixer for scaling the frequency generated by the channel selection voltage controlled oscillator by five divided by four times based on the divider and the channel selection voltage controlled oscillator.

36. The wireless transceiver circuit of claim 35, wherein the receiver local oscillator generator circuit further comprises a flip-flop that generates a signal at half the frequency generated by the single sideband mixer; also included is a multiplexer having a first input coupled to the single sideband mixer, a second input coupled to the flip-flop, and an output for providing a receiver local oscillator signal to the direct conversion receiver, and the multiplexer selects either the frequency generated by the single sideband mixer or half of the frequency generated by the single sideband mixer as the receiver local oscillator frequency signal based on a selection signal.