HK1071477A1 - Controlled prequency power factor correction circuit and method - Google Patents

Abstract

A PFC circuit comprises: a latch having an output end responding to a clock signal jump current along with start coil for generating PPC signal, a control signal received by input end; the current modulation circuit having a first input end used in receiving PFC signal to build the charging time for coil current, a second input end used in checking the coil current to build the duty cycle for coil current at one period of clock signal, and a output end providing a control signal as a function of the charging time and the duty cycle.

Description

Frequency controlled power factor correction circuit and method

Technical Field

The present invention relates generally to integrated circuits and, more particularly, to integrated power factor correction circuits.

Background

An integrated Power Factor Correction (PFC) circuit is a switching circuit that ensures that an Alternating Current (AC) line is loaded with a substantially sinusoidal current in phase. Without PFC correction, many electrical systems can only draw current from ac line voltages that are close to the peak voltage level of the ac line. The aggregate effect of loading the ac line with large currents at voltage peaks and zero current at other times can distort the ac line voltage. Furthermore, systems without PFCs may result in large neutral currents flowing in the three-phase distribution network. In order to avoid these problems and to make the electrical equipment work well, the distribution network of the regional power supply companies must have margins, which require a large capital investment. Some government mandates that PFCs must be incorporated into power supplies used by some or all electrical devices.

PFC circuits typically switch the current from the ac line through an inductor or coil at a frequency substantially higher than the ac line frequency to magnetize or charge the coil. For example, when the ac line frequency is 50Hz, the system may use a switching frequency of at least 100 kHz. The energy stored in the coil is released into a capacitor to produce an intermediate PFC Direct Current (DC) voltage to power an electrical device or system. In order to obtain a substantially sinusoidal alternating current, the average value of the current switched through the coil during a switching cycle is made proportional to the present voltage of the alternating current line. The result is a high effective power factor for the ac line.

Most previous PFC circuits operate in a self-excited mode, in which a current is switched to charge the coil once the stored coil current has been discharged to the capacitor in the previous cycle. As a result, the switching frequency of previous PFC circuits varies with the current ac line voltage and the load current of the system. Such variable switching frequencies are difficult to filter out to suppress or remove electromagnetic interference generated by switching coil currents. Such filtering requires various complex filters that not only consume power, but also substantially increase the manufacturing cost of a system.

Therefore, there is a need for a PFC circuit and method for correcting power factor that operates at or near a fixed frequency to reduce electromagnetic interference of the system while maintaining low manufacturing costs of the PFC circuit.

Disclosure of Invention

According to one aspect of the present invention, a Power Factor Correction (PFC) circuit includes: a first latch having: an input for receiving a control signal; and an output for enabling a coil current in response to a transition edge of the clock signal, wherein the coil current generates the PFC signal; a duty cycle sensor configured to form a sense signal representative of the coil current; and a current modulator having: a first input terminal connected to receive a PFC signal to establish a charging time for the coil current; a second input terminal connected to receive said sense signal to establish a duty cycle of the coil current over a period of the clock signal; and an output for providing said control signal as a function of charging time and duty cycle.

According to another aspect of the present invention, a method for correcting a power factor includes the steps of: starting a coil current at the beginning of a clock cycle to generate a Power Factor Correction (PFC) signal; detecting the coil current to determine a duty cycle of the coil current over the clock period; and terminating the charging portion of the coil current with a control signal that is a function of the PFC signal and the duty cycle.

In accordance with yet another aspect of the present invention, an integrated Power Factor Correction (PFC) circuit comprises: a driver circuit having: a first input for receiving a clock pulse to initiate a coil current; a second input terminal for receiving a control signal to terminate the charging portion of the coil current; and an output for generating a PFC signal from the coil current; and a current modulator having: a first input terminal connected to detect the PFC signal to set the magnitude of the coil current; a second input for monitoring the coil current during a period of the clock pulse to generate a duty cycle signal; and an output for providing said control signal as a function of the magnitude of said coil current and the duty cycle signal.

Drawings

FIG. 1 is a schematic diagram of a Power Factor Correction (PFC) circuit;

FIG. 2 is a timing diagram showing various waveforms of the PFC circuit;

FIG. 3 is a schematic diagram of a duty cycle sensor of the PFC circuit;

FIG. 4 is a schematic diagram of a current modulator of the PFC circuit; and

fig. 5 is a schematic diagram of a current modulator in an alternative embodiment.

Detailed Description

In the drawings, components having the same reference numerals have similar functions.

Fig. 1 is a schematic diagram of a Power Factor Correction (PFC) circuit 100 controlled by PFC control circuit 10, which includes a diode bridge 20, resistors 22-24, an inductor or coil 25, a diode 26, an output capacitor 27, a timing capacitor 28, and a switching transistor 29. PFC circuit 100 receives a sinusoidal voltage VAC from an Alternating Current (AC) line and generates the voltage VAC at a node or output 30A Direct Current (DC) PFC output signal V_OUT. In one embodiment, PFC circuit 100 functions as a boost converter regulator, receiving a value of approximately 220V Root Mean Square (RMS) and a frequency of approximately 50Hz VAC, and generating a PFC output voltage V having a value of approximately 400V DC_OUT. In some regions, the VAC has a frequency of about 110V (RMS) and 60 Hz. The VAC has a typical range of variation of about + -20%.

The diode bridge 20 is a standard full wave bridge rectifier which rectifies the line voltage VAC and outputs a rectified sine wave voltage V at node 32_INThe frequency is twice the frequency of the VAC, i.e., about 100Hz, and the peak is about 310V. A capacitor (not shown) may be connected across the diode bridge 20 to reduce VAC noise spikes.

The coil 25 has an inductance, typically of value L100.0 muh, and a low equivalent series resistance in order to achieve high efficiency operation.

Transistor 29 is a high current n-channel mosfet that turns on and off the coil current I through coil 25_COIL. In one embodiment, transistor 29 is a power transistor capable of switching a coil current I greater than 2A_COILPeak value of (a). These currents are small near the zero-crossing point of the VAC and large near the peak of the VAC voltage. Transistor 29 typically has a large gate capacitance of greater than 500 pF.

Coil current I_COILHaving a charging current component I_CHAnd a discharge current component I_DSCH. When the transistor 29 is turned on, the charging current I_CHFlowing through the coil 25, magnetic energy is stored in the coil 25. When transistor 29 is turned off, it follows the discharge current I_DSCHThe stored magnetic energy is discharged from coil 25 through diode 26 to capacitor 27, producing PFC voltage V at node 30_OUT。

Coil current I_COILHaving a return path through a resistor 22 to a diode bridge 20 at a node31, a current sensing voltage V is generated_ISTo monitor I_COILWhen it is flowing. In one embodiment, resistor 22 has a resistance of about 0.2 Ω, and thus, when I_COILWhen the size of (A) is 1, V_ISThe value of (A) is about-0.2V. Alternatively, I can also be measured using voltage sensing techniques instead of the current sensing technique shown in FIG. 1_COILThe on-time of (c). For example, the coil 25 may form the primary winding of a transformer having a secondary winding with one terminal coupled at node 31 to the input of the duty cycle sensor 12, typically through a resistor, the other terminal of the secondary winding being connected to ground. When I is_COILWhen charging, the current sensing voltage V generated by the secondary winding_ISIs a positive voltage when I_COILDuring discharge, V_ISIs a negative voltage, and when I_COILWhen 0, V_ISSubstantially 0V.

I_COILIs the PFC output voltage V_OUTAnd is fed back V through a voltage divider formed by resistors 23 and 24_OUTTo control I_COILThe size of (2). This voltage divider pair V_OUTSamples are taken and a sense voltage V is provided at node 36_SENSE. The resistors 23 and 24 have respective resistance values R₂₃And R₂₄。

PFC control circuit 10 includes a duty cycle sensor 12, a current modulator 14, a flip-flop or latch 16, and an output buffer 18. The current modulator 14 generates a timing current I_TIMINGWhich charges the external capacitor 28 to establish a timing voltage V_TIMINGFor controlling the charging current I_CHAnd thus the peak amplitude thereof, as will be explained below. In one embodiment, PFC control circuit 10 is formed as an integrated circuit on a semiconductor substrate.

The output buffer 18 is a standard non-inverting amplifier that can drive the large capacitive load provided by transistor 29.

Latch 16 is a standard R-S flip-flop having a Q output that provides a digital switching signal VSW that is set at the transition edge of a CLOCK signal CLOCK and reset at the transition edge of a digital termination signal TERM. To achieve high power factor, CLOCK preferably operates at a voltage much greater than V_INAt the frequency of the frequency. In one embodiment, V_INThe CLOCK pulse is generated with a frequency of about 100Hz, or a period of about 10ms, at a controlled or substantially constant frequency of about 100kHz, or a period of about 10 mus. When VSW is set, transistor 29 is turned on via output buffer 18, thereby initiating coil current I_COILCharging component I of_CHCausing the coil 25 to magnetize or store energy. When VSW is reset, the transistor 29 is turned off by the output buffer 18, thereby terminating the charging component I_CHSimultaneously start I_COILDischarge component I of_DSCHIt flows through diode 26, transferring energy from coil 25 to capacitor 27.

Duty cycle sensor 12 pair coil current I_COILMonitoring and generating a digital coil current sense signal COILON at output terminal 34 when I_COILWhen it is substantially non-zero, it is at a logic high level, and when I is_COILWhen it is 0, it is at a logic low level. A comparator for converting the current sensing signal V_ISWith reference signal V_REF2A comparison is made to produce COILON. In one embodiment, duty cycle sensor 12 includes a preamplifier that increments V_ISTo improve the degree of interference immunity. Since VSW is set at the time of each CLOCK pulse, indicating the beginning of a new cycle, the portion of COILON at a logic high level during a CLOCK cycle indicates I_COILDuty cycle of (d).

The current modulator 14 has an input at node 36 which is fed by the sensor signal V_SENSETo monitor the PFC signal V_OUTSo as to be the coil current I_COILCharging part I of_CHEstablishing a time T_CH. At node 34, an input detects I_COILWhen to flow through to provide the digital signal COILON to establish I_COILDuty cycle over one CLOCK cycle. The current modulator 14 comprises an error amplifier which is coupled between V_SENSEAnd a reference voltage V_REF1The difference between them is amplified to produce a correction signal V_ERRFor setting I_COILSize of (D) and time T_CH. The amplified difference and COILON are integrated over one cycle of CLOCK to generate a termination signal TERM at an output of node 38 to terminate the charging current I_CHAnd starting a discharge current I_DSCH. Thus, TERM is T_CHAnd a function of the duty cycle is generated. In one embodiment, TERM is generated such that T_CHAnd I_COILThe product of the duty cycles of (a) and (b) is kept constant.

The switching cycle of the PFC control circuit 10 is initiated by a CLOCK signal CLOCK that preferably operates at a constant or near constant frequency. Because the period of CLOCK is far less than V_INSo that a substantially constant voltage V appears across the coil 25 when the transistor 29 is turned on_IN. Coil current I_COILAccording to a ratio of about equal to V_INThe slope of/L increases linearly, so that it peaks at I_PEAK＝T_CH＊V_INL, in the formula, T_CHFor charging current I_CHThe duration of (c). Similarly, the discharge current I_DSCHIs approximately equal to (V)_OUT-V_IN) L, and its duration T_DSCH＝L＊I_PEAK/(V_OUT-V_IN). Thus, I_COILThe entire period of non-zero values is given by equation 1,

it can be seen that in one clock cycle T_CLOCKAverage coil current I of_{COIL_CLOCK}As given by the equation 2, it is shown that,

in the formula, D_CYCLE＝(T_CH+T_DSCH)/T_CLOCK. When the average coil current I_{COIL_ CLOCK}Following V_INWhen the rectified sine wave form (if T)_CH＊D_CYCLEThis occurs if kept constant), a high power factor can be achieved.

Referring to fig. 2, the operation of the PFC control circuit 10 can be seen as a timing diagram showing selected waveforms of the PFC control circuit 10. Initially, at time T0, assume that CLOCK signal CLOCK, transition signal VSW, termination signal TERM, and coil current sense signal COILON are all at a low level. Further assume that the coil current I_COILCurrent sensing voltage V_ISTiming current I_TIMINGAnd a timing voltage V_TIMINGEach equal to zero.

At time T1, the low-to-high transition edge of the CLOCK signal causes latch 16 to force the low-to-high transition of VSW through buffer 18 to turn on transistor 29 to enable coil current I_COIL. Note that I flowing at time T1 begins_COILIs the charging current I_CH. Because the period of CLOCK is far less than V_INAnd the voltage drop over transistor 29 is typically small, so a substantially constant voltage V_INIs applied to both ends of the coil 25 so that I_COILLinearly increasing or as shown in the figure by V_INThe slope of/L forms a sawtooth wave. I is_COILFlows through the resistor 22 to generate a current sensing voltage V_ISIt also increases linearly, but in the direction of the negative voltage, as shown. The low-to-high transition of VSW sets COILON high to initiate the timing current I_TIMINGWhich charges a capacitor 28 to establish the timing voltage V in a linear sawtooth fashion_TIMING。

At time T2, V_TIMINGReaching a threshold voltage causes the termination signal TERM to make a low-to-high transition which resets the latch 16. The threshold voltage may be a predetermined voltage or a variable voltage, as will be described in more detail below. High-to-low transition termination I of VSW_COILCharging current I of_CHAnd starting a discharge current I_DSCHTo transfer energy from the coil 25 to the capacitor 27. VSW also closes a switch, discharges capacitor 28, and puts I on_TIMINGShunting to ground to separate V_TIMINGTo 0 as shown. I is_DSCHAccording to the slope (V)_OUT-V_IN) the/L decreases in a linear manner until the magnetic energy stored in the coil 25 is completely released.

At time T3, I_COILIs reduced to 0. Current sensing signal V_ISAnd also linearly increases to 0, which causes the coil current sense signal COILON to make a high-to-low transition. The remainder of the clock cycle, I, before time T4 (at which time the next cycle begins)_COILSubstantially maintaining a zero value.

Fig. 3 shows a schematic diagram of duty cycle sensor 12 connected to resistor 42, including amplifier 44, comparator 45, latch 46, and resistors 42-43. The duty cycle sensor 12 receives a sense signal V at node 31 through resistor 42_ISTo monitor the coil current I_COILThe flow of (c). An output terminal is connected to node 34 for generating a coil current sense signal COILON when I_COILIs substantially 0, the value of COILON is a logic low level, when I is_COILWhen not 0, the value of COILON is logic high.

At time T1, CLOCK signal CLOCK goes fromThe transition from logic low to high sets the switching signal VSW to a logic high value to initiate the coil current I_COIL. Latch 46 is set so that COILON generates a low to high logic level transition at node 34 to represent I_COILIs flowing, i.e., has a value other than 0. At the same time, the sensing signal V_ISLinearly decreasing from 0 to a negative value.

The amplifier 44 and the resistors 42-43 function as a gain stage for V_ISAmplification is performed to increase the interference rejection of the system. In one embodiment, resistor 43 has a value of about 10k Ω and resistor 42 has a value of about 1k Ω, which results in the amplified signal having a value of about (-10V) at node 41_IS). Thus, before time T2, the potential at node 41 increases linearly from 0 to a positive potential, and at time T2, as coil 25 discharges, its value begins to decrease toward 0V. When the potential of the node 41 decreases to a level lower than V_REF2At the value of (3), the comparator 45 makes the reset signal V_RGenerates a transition from a logic low to a high which resets latch 46 to cause COILON to generate a high to low transition, which represents I_COILHas been substantially discharged to 0. In fact, V may be_REF2Is set to a small positive non-zero value to avoid oscillation conditions in comparator 45 that would effectively introduce noise into V_RAmong them. In one embodiment, V_REF2Is set to 0.1V, which corresponds to I_COILA value of 0.05A.

Fig. 4 is a schematic diagram showing current modulator 14 in more detail, including amplifiers 47-48, comparator 49, switches 50-51, resistors 52-53, capacitors 54-55, and current source 56. The resistors 52 and 53 each have a resistance value R₅₂And R₅₃Capacitors 54 and 55 each have a capacitance C₅₄And C₅₅。

The amplifier 47 functions as an error amplifier which converts the sensing signal V_SENSEAnd a reference voltage V_REF1Comparing them and amplifying their differenceThereby producing a correction signal V at node 72_ERR. In fact, the amplifier 47 is between the desired values V_OUT＝V_REF1＊(1+R₂₃/R₂₄) And V_OUTThe difference between the actual current values of (a) is amplified. The PFC control circuit 10 passes the order V_SENSERemains substantially equal to V_REF1To effectively regulate V_OUT. The capacitor 54 and the resistors 23-24 function as an integrator or low-pass filter that filters out signals that may be present in the PFC signal V_OUTIn V_SENSE100Hz or 120Hz, the frequency of the ripple being dependent on the frequency of the local or regional VAC. The capacitor 54 and the resistors 23-24 produce an integration time constant R₂₃＊R₂₄＊C₅₄/(R₂₃+R₂₄) Which can attenuate V with a shorter duration_SENSEIs fluctuating. In one embodiment, the time constant is at least V_IN5 times the period, e.g. when V_INIs 10ms, the time constant is set to at least 50 ms. Thus, at one V_INWithin a period, V_ERRAre considered to be substantially constant.

In the gain stage 70, the signal V is corrected_ERRIs effectively divided by I_COILThe gain stage 70 contains an amplifier 48, resistors 52-53, a capacitor 55 and a switch 50. Gain stage 70 functions as an integrator whose time constant is set by resistors 52-53 and capacitor 55 to filter out transition transients that occur when switch 50 turns on and off at the frequency of CLOCK signal CLOCK. The value of the time constant is preferably equal to or greater than 5 times the period of CLOCK. For example, if the period of CLOCK is 10 μ s, then the time constant of resistors 52-53 and capacitor 55 should preferably be at least 50 μ s. A control or threshold signal V is provided at node 74_TON。

The operation of gain stage 70 is as follows. When COILON is at a high level, for example, from time T1 to time T3 (I)_COILNon-zero value), the switch 50 is in an open state. V_ERRActing as a reference voltage, which is connected to the non-inverting of amplifier 48An input terminal. And V_TONIs connected to the inverting input terminal through resistors 52 and 53, the difference (V) between them_ERR-V_TON) By time constant T_SW0＝C₅₅＊(R₅₂+R₅₃) Integration is performed. When COILON is at a low level, for example, from time T3 to time T4 (I)_COILZero value), the switch 50 is in a closed state and the voltage across the switch 50 is approximately 0. A voltage of substantially 0V at this time is applied to the inverting input of the amplifier 48 through the resistor 52. V_ERRStill applied to the non-inverting input of amplifier 48 as a reference voltage, by the difference (V)_ERR-0.0V) with an integration time constant T_SW1＝C₅₅＊R₅₂Integration is performed. Since resistor 53 is selected to be much smaller than resistor 52, a substantially equal time constant can be generated regardless of the position of switch 50, which can be considered approximately as T_SW0＝T_SW1. Time constant T_SW0And T_SW1Preferably selected to be greater than the period of CLOCK so that a time-weighted average voltage V appears at the inverting input of amplifier 48_TON＊(T3-T1)/(T4-T1)＝V_TON＊D_CYCLEWhere D is_CYCLE(T3-T1)/(T4-T1) is I_COILDuty cycle within one CLOCK period. PFC circuit 100 for V_OUTEnsures that at each input V of the amplifier 48_ERR＝V_TON＊D_CYCLEOr V_TON＝V_ERR/D_CYCLE. Due to V_ERRIs substantially constant during a CLOCK cycle, so that the product V_TON＊D_CYCLEIs also constant, such that I_COILHaving a sinusoidal waveform while allowing PFC circuit 100 to have a high power factor.

V_TIMINGBy using a constant current I_TIMINGCapacitor C28 is charged so that it has a saw-tooth waveform, i.e., I_TIMINGA linear function of (a). V_TONIs connected to the input of a comparator 49 for controlling the trip point at which the timing voltage V is applied_TIMINGWill terminate signal TERM is set to logic high level to terminate the charging current I_CH。

It should be noted that the correction voltage V is now controlled by COILON_ERRMaking adjustments to produce a threshold voltage V_TONWhile, I_TIMINGRemains substantially constant, thereby resulting in a product T_CH＊D_CYCLERemains substantially constant. When the product T is as described above_CH＊D_CYCLEWhen kept constant, I_COILIs a sinusoidal function and is in phase with the ac line voltage VAC, resulting in a high power factor. When the coil current I is switched by the CLOCK signal CLOCK at a constant frequency_COILA high power factor can be achieved to reduce the level of electromagnetic interference or to facilitate attenuation thereof by filtering.

Fig. 5 is a schematic diagram showing the current modulator 14 in an alternative embodiment. In this embodiment, the correction voltage V_ERRIs directly connected to the inverting input of the comparator 49 to control V_TIMINGWhile passing through I_COILDuty cycle of (D) DC pair I_TIMINGAdjustment is made so as to make the product T_CH＊D_CYCLEAnd remain constant.

The amplifier 60 acts as an integrator with an integration time constant T_SW＝C₆₁＊R₆₈Here, C₆₁Is the capacitance of capacitor 61, R₆₈Is the resistance value of resistor 68. Capacitor 61 and resistor 68 are preferably selected such that T_SWThe value of (c) is much greater than the period of CLOCK.

From T1 to T3, when I_COILWhen the reference current is non-zero, COILON is at high level, switch 50 is at open state, and reference current I_REF1Flows through resistor 66 to form a voltage V at node 77₆₆＝I_REF1＊R₆₆Here, R₆₆Is the resistance value of the resistor 66. From T3 to T4, when I_COILAt zero, COILON is low, switch 50 is closed, and voltage V at node 77₆₆0.0V. When integrating over the CLOCK cycle, the voltage V₆₆Has a time-weighted average of I_REF1＊R₆₆＊D_CYCLE＝V₆₆＊D_CYCLE。

The output of amplifier 60 controls the base current of transistor 65, which is connected to resistor 69. Such a configuration generates a collector current I₆₅From a reference current I_REF2Minus the collector current I₆₅To generate a current I_OUTIt produces a voltage V across a resistor R67₆₇. Collector current I₆₅A feedback path is provided which makes V₆₆And V₆₇Maintain the same effective average potential, therefore, I_OUT＝I_REF1＊D_CYCLE＊R₆₆/R₆₇. Establishing a timing current I by means of a current mirror 63_TIMINGMirror image I of_OUTAnd multiplied by a factor K, such that I_TIMING＝K＊I_OUT＝K＊I_REF1＊D_CYCLE＊R₆₆/R₆₇. Thus, I_TIMINGAnd duty cycle D_CYCLEIs in direct proportion.

As described above, I_TIMINGCharging capacitor 28 to produce a sawtooth-shaped timing voltage V_TIMINGIn the comparator 49, the sawtooth voltage is followed by V_ERRA comparison is made to generate the control signal TERM. Due to the fact that at V_INIn one period of (A), I_TIMINGRemains substantially constant, and V_TIMING＝I_TIMING＊T_CH＝K＊I_REF1＊D_CYCLE＊T_CH＊R₆₆/R₆₇So product T_CH＊D_CYCLEAnd also remains substantially constant. Thus, I_COILThere is a sinusoidal average current while PFC circuit 100 has a high power factor.

In summary, the present invention provides a PFC circuit that is capable of operating at a constant or near constant frequency, thereby facilitating the reduction of electromagnetic interference through filtering. The latch has an output responsive to an edge of a transition of the clock signal to enable the coil current to generate the PFC signal. A current modulation circuit detects the PFC signal to establish a charging time of the coil current and detects the coil current to establish a duty cycle of the coil current over one cycle of the clock signal. The output of the current modulation circuit is applied to the input of the latch to provide a control signal that is a function of the charging time and duty cycle.

Claims (10)

1. A power factor correction, PFC, circuit comprising:

a first latch having: an input for receiving a control signal; and an output for enabling a coil current in response to a transition edge of the clock signal, wherein the coil current generates the PFC signal;

a duty cycle sensor configured to form a sense signal representative of the coil current; and

a current modulator having: a first input terminal connected to receive a PFC signal to establish a charging time for the coil current; a second input terminal connected to receive said sense signal to establish a duty cycle of the coil current over a period of the clock signal; and an output for providing said control signal as a function of charging time and duty cycle.

2. The PFC circuit of claim 1 wherein the current modulator further comprises an amplifier and a first switch, the first switch operating in response to the sense signal received by the second input of the current modulator to switch an input of the amplifier from the output of the amplifier to a reference node to establish the duty cycle.

3. The PFC circuit of claim 1, wherein the duty cycle sensor has: an input connected to sense said coil current; and an output for providing the sensing signal.

4. The PFC circuit of claim 3, wherein the duty cycle sensor comprises:

a first amplifier having: a first input connected to the input of the duty cycle sensor; and a second input for establishing a threshold level of the coil current; and

a second latch having: a first input terminal connected to the output terminal of the first latch; a second input terminal connected to an output terminal of the first amplifier; and an output (34) coupled to the second input of the current modulator for generating the sense signal having a first logic state at an edge of a transition of the clock signal and a second logic state when the coil current drops below a threshold level.

5. The PFC circuit of claim 4, wherein the current modulator comprises:

a comparator having: a first input terminal connected to receive a saw-tooth signal; and an output for providing said control signal;

a second amplifier having: a first input terminal for receiving a PFC signal; a second input for receiving a reference signal; and an output connected to the second input of the comparator; and

an averaging circuit having an input coupled to the output of the second latch for averaging the first reference current over a period of the clock signal to produce an average current representing the duty cycle.

6. The PFC circuit of claim 5, wherein the averaging circuit comprises:

a switch for switching a first reference current in response to said sensing signal to generate a duty cycle signal; and

an integrator having: a first input terminal coupled to receive a second reference signal; a second input for receiving said duty cycle signal; and an output for providing the average current.

7. A method for correcting power factor, comprising the steps of:

starting a coil current at the beginning of a clock cycle to generate a PFC signal;

detecting the coil current to determine a duty cycle of the coil current over the clock period; and

the charging portion of the coil current is terminated with a control signal that is a function of the PFC signal and the duty cycle.

8. The method of claim 7, wherein the step of terminating the charging portion of the coil current comprises the steps of:

amplifying the difference between the PFC signal and the first reference signal to generate a correction signal; and

the correction signal is divided by a duty cycle to generate the control signal.

9. The method of claim 8, wherein the step of dividing the correction signal by the duty cycle comprises the steps of:

supplying the correction signal to a first input of an amplifier;

switching a second input of the amplifier to an output of the amplifier when the coil current flows; and

when the coil current is terminated, the second input of the amplifier is switched to a reference node.

10. An integrated PFC circuit comprising:

a driver circuit having: a first input for receiving a clock pulse to initiate a coil current; a second input terminal for receiving a control signal to terminate the charging portion of the coil current; and an output for generating a PFC signal from the coil current; and

a current modulator having: a first input terminal connected to detect the PFC signal to set the magnitude of the coil current; a second input for monitoring the coil current during a period of the clock pulse to generate a duty cycle signal; and an output for providing said control signal as a function of the magnitude of said coil current and the duty cycle signal.