[go: up one dir, main page]

GB9828381D0 - Hardware/software codesign system - Google Patents

Hardware/software codesign system

Info

Publication number
GB9828381D0
GB9828381D0 GBGB9828381.5A GB9828381A GB9828381D0 GB 9828381 D0 GB9828381 D0 GB 9828381D0 GB 9828381 A GB9828381 A GB 9828381A GB 9828381 D0 GB9828381 D0 GB 9828381D0
Authority
GB
United Kingdom
Prior art keywords
hardware
codesign system
software codesign
software
codesign
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
GBGB9828381.5A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oxford University Innovation Ltd
Original Assignee
Oxford University Innovation Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oxford University Innovation Ltd filed Critical Oxford University Innovation Ltd
Priority to GBGB9828381.5A priority Critical patent/GB9828381D0/en
Publication of GB9828381D0 publication Critical patent/GB9828381D0/en
Priority to PCT/GB1999/004338 priority patent/WO2000038087A1/en
Priority to GB0115062A priority patent/GB2362005B/en
Priority to AU18752/00A priority patent/AU1875200A/en
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/347—Physical level, e.g. placement or routing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2117/00—Details relating to the type or aim of the circuit design
    • G06F2117/08—HW-SW co-design, e.g. HW-SW partitioning

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stored Programmes (AREA)
  • Devices For Executing Special Programs (AREA)
GBGB9828381.5A 1998-12-22 1998-12-22 Hardware/software codesign system Ceased GB9828381D0 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GBGB9828381.5A GB9828381D0 (en) 1998-12-22 1998-12-22 Hardware/software codesign system
PCT/GB1999/004338 WO2000038087A1 (en) 1998-12-22 1999-12-21 Hardware/software codesign system
GB0115062A GB2362005B (en) 1998-12-22 1999-12-21 Hardware/software codesign system
AU18752/00A AU1875200A (en) 1998-12-22 1999-12-21 Hardware/software codesign system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GBGB9828381.5A GB9828381D0 (en) 1998-12-22 1998-12-22 Hardware/software codesign system

Publications (1)

Publication Number Publication Date
GB9828381D0 true GB9828381D0 (en) 1999-02-17

Family

ID=10844844

Family Applications (2)

Application Number Title Priority Date Filing Date
GBGB9828381.5A Ceased GB9828381D0 (en) 1998-12-22 1998-12-22 Hardware/software codesign system
GB0115062A Expired - Fee Related GB2362005B (en) 1998-12-22 1999-12-21 Hardware/software codesign system

Family Applications After (1)

Application Number Title Priority Date Filing Date
GB0115062A Expired - Fee Related GB2362005B (en) 1998-12-22 1999-12-21 Hardware/software codesign system

Country Status (3)

Country Link
AU (1) AU1875200A (en)
GB (2) GB9828381D0 (en)
WO (1) WO2000038087A1 (en)

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
DE19651075A1 (en) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Unit for processing numerical and logical operations, for use in processors (CPU's), multi-computer systems, data flow processors (DFP's), digital signal processors (DSP's) or the like
DE19654593A1 (en) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh Reconfiguration procedure for programmable blocks at runtime
DE19654846A1 (en) 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Process for the independent dynamic reloading of data flow processors (DFPs) as well as modules with two- or multi-dimensional programmable cell structures (FPGAs, DPGAs, etc.)
DE19704728A1 (en) 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Method for self-synchronization of configurable elements of a programmable module
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
DE19704742A1 (en) 1997-02-11 1998-09-24 Pact Inf Tech Gmbh Internal bus system for DFPs, as well as modules with two- or multi-dimensional programmable cell structures, for coping with large amounts of data with high networking effort
JP2002530780A (en) 1998-11-20 2002-09-17 アルテラ・コーポレーション Reconfigurable programmable logic device computer system
US6430736B1 (en) 1999-02-26 2002-08-06 Xilinx, Inc. Method and apparatus for evolving configuration bitstreams
US6378122B1 (en) 1999-02-26 2002-04-23 Xilinx, Inc. Method and apparatus for evolving a plurality of versions of a configuration bitstream in parallel
US6539532B1 (en) 1999-02-26 2003-03-25 Xilinx, Inc. Method and apparatus for relocating elements in an evolvable configuration bitstream
US6363519B1 (en) 1999-02-26 2002-03-26 Xilinx, Inc. Method and apparatus for testing evolvable configuration bitstreams
US6363517B1 (en) 1999-02-26 2002-03-26 Xilinx, Inc. Method and apparatus for remotely evolving configuration bitstreams
US7343594B1 (en) 2000-08-07 2008-03-11 Altera Corporation Software-to-hardware compiler with symbol set inference analysis
US7257780B2 (en) 2000-08-07 2007-08-14 Altera Corporation Software-to-hardware compiler
US7069204B1 (en) * 2000-09-28 2006-06-27 Cadence Design System, Inc. Method and system for performance level modeling and simulation of electronic systems having both hardware and software elements
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
JP2004517386A (en) 2000-10-06 2004-06-10 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト Method and apparatus
GB0028079D0 (en) * 2000-11-17 2001-01-03 Imperial College System and method
US20020112219A1 (en) * 2001-01-19 2002-08-15 El-Ghoroury Hussein S. Matched instruction set processor systems and efficient design and implementation methods thereof
US20020116166A1 (en) * 2001-02-13 2002-08-22 El-Ghoroury Hussein S. Matched instruction set processor systems and method, system, and apparatus to efficiently design and implement matched instruction set process systems using interconnected design components
US7055019B2 (en) * 2001-02-13 2006-05-30 Ellipsis Digital Systems, Inc. Matched instruction set processor systems and method, system, and apparatus to efficiently design and implement matched instruction set processor systems by mapping system designs to re-configurable hardware platforms
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7581076B2 (en) 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
EP1286279A1 (en) * 2001-08-21 2003-02-26 Alcatel Configuration tool
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US7577822B2 (en) 2001-12-14 2009-08-18 Pact Xpp Technologies Ag Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
US20030121010A1 (en) * 2001-12-21 2003-06-26 Celoxica Ltd. System, method, and article of manufacture for estimating a potential performance of a codesign from an executable specification
US6668312B2 (en) * 2001-12-21 2003-12-23 Celoxica Ltd. System, method, and article of manufacture for dynamically profiling memory transfers in a program
US20030140337A1 (en) * 2001-12-21 2003-07-24 Celoxica Ltd. System, method, and article of manufacture for data transfer reporting for an application
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
GB0215034D0 (en) * 2002-06-28 2002-08-07 Critical Blue Ltd Architecture generation method
EP1527390A2 (en) * 2002-07-25 2005-05-04 Koninklijke Philips Electronics N.V. Source-to-source partitioning compilation
WO2004021176A2 (en) * 2002-08-07 2004-03-11 Pact Xpp Technologies Ag Method and device for processing data
EP1537486A1 (en) 2002-09-06 2005-06-08 PACT XPP Technologies AG Reconfigurable sequencer structure
US6964029B2 (en) * 2002-10-31 2005-11-08 Src Computers, Inc. System and method for partitioning control-dataflow graph representations
US6983456B2 (en) * 2002-10-31 2006-01-03 Src Computers, Inc. Process for converting programs in high-level programming languages to a unified executable for hybrid computing platforms
DE10316292A1 (en) * 2003-04-09 2004-11-11 Siemens Ag Method and arrangement for the performance prediction of an information technology system
US7424698B2 (en) 2004-02-27 2008-09-09 Intel Corporation Allocation of combined or separate data and control planes
US7073159B2 (en) 2004-03-31 2006-07-04 Intel Corporation Constraints-directed compilation for heterogeneous reconfigurable architectures
US7849449B2 (en) 2005-12-05 2010-12-07 National Instruments Corporation Implementing a design flow for a programmable hardware element that includes a processor
US8121813B2 (en) 2009-01-28 2012-02-21 General Electric Company System and method for clearance estimation between two objects
US20120096445A1 (en) * 2010-10-18 2012-04-19 Nokia Corporation Method and apparatus for providing portability of partially accelerated signal processing applications
US8959469B2 (en) 2012-02-09 2015-02-17 Altera Corporation Configuring a programmable device using high-level language
CN107111663B (en) * 2014-11-12 2021-01-08 赛灵思公司 Heterogeneous Multiprocessor Program Compilation Targeting Programmable Integrated Circuits
CN104572234A (en) * 2014-12-29 2015-04-29 杭州华为数字技术有限公司 Method for generating source codes used for parallel computing architecture and source-to-source compiler
US10956241B1 (en) 2017-12-20 2021-03-23 Xilinx, Inc. Unified container for hardware and software binaries
US11270051B1 (en) * 2020-11-09 2022-03-08 Xilinx, Inc. Model-based design and partitioning for heterogeneous integrated circuits
CN115879402A (en) * 2022-12-16 2023-03-31 无锡亚科鸿禹电子有限公司 A Communication Method for Software-Hardware Co-simulation

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5535342A (en) * 1992-11-05 1996-07-09 Giga Operations Corporation Pld connector for module having configuration of either first PLD or second PLD and reconfigurable bus for communication of two different bus protocols
SE505783C2 (en) * 1995-10-03 1997-10-06 Ericsson Telefon Ab L M Method of manufacturing a digital signal processor
EP1065611A3 (en) * 1995-10-23 2006-05-10 Interuniversitair Microelektronica Centrum Vzw A design environment for hardware/software co-design
ATE257611T1 (en) * 1995-10-23 2004-01-15 Imec Inter Uni Micro Electr DESIGN SYSTEM AND METHODS FOR COMBINED DESIGN OF HARDWARE AND SOFTWARE

Also Published As

Publication number Publication date
GB0115062D0 (en) 2001-08-15
WO2000038087A1 (en) 2000-06-29
GB2362005A (en) 2001-11-07
GB2362005B (en) 2003-07-16
AU1875200A (en) 2000-07-12

Similar Documents

Publication Publication Date Title
GB2362005B (en) Hardware/software codesign system
GB9806843D0 (en) Software application development system
GB9816088D0 (en) System
GB9825102D0 (en) Computer system
GB2354323B (en) Location system
HUP0102601A3 (en) Construction system
GB2326254B (en) Agent system
PL348824A1 (en) Precompression system
GB9807281D0 (en) Plaster system
HU9900470D0 (en) Condansation system
IL138643A0 (en) Block system
GB2334751B (en) Anti-pinching system
GB2339049B (en) Game system
GB2359162B (en) Parallel processor system
GB9816261D0 (en) Cross-care system
GB9813045D0 (en) Simulator system
GB0112100D0 (en) Vibratory system
GB2341255B (en) Odering system
GB9922670D0 (en) Mounting system
GB0227323D0 (en) Selection system
GB9714051D0 (en) Software/hardware system
GB9811713D0 (en) Data-collection system
GB9809378D0 (en) System
HU9802844D0 (en) Compost-making system
GB9814544D0 (en) Babyfeeding system

Legal Events

Date Code Title Description
COOA Change in applicant's name or ownership of the application
AT Applications terminated before publication under section 16(1)