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GB9206126D0 - Parallel vector processor architecture - Google Patents

Parallel vector processor architecture

Info

Publication number
GB9206126D0
GB9206126D0 GB929206126A GB9206126A GB9206126D0 GB 9206126 D0 GB9206126 D0 GB 9206126D0 GB 929206126 A GB929206126 A GB 929206126A GB 9206126 A GB9206126 A GB 9206126A GB 9206126 D0 GB9206126 D0 GB 9206126D0
Authority
GB
United Kingdom
Prior art keywords
processor architecture
vector processor
parallel vector
parallel
architecture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
GB929206126A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MAXYS CIRCUIT TECHNOLOGY LIMIT
Original Assignee
MAXYS CIRCUIT TECHNOLOGY LIMIT
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MAXYS CIRCUIT TECHNOLOGY LIMIT filed Critical MAXYS CIRCUIT TECHNOLOGY LIMIT
Priority to GB929206126A priority Critical patent/GB9206126D0/en
Publication of GB9206126D0 publication Critical patent/GB9206126D0/en
Priority to PCT/GB1993/000580 priority patent/WO1993019431A1/fr
Priority to AU37620/93A priority patent/AU3762093A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8015—One dimensional arrays, e.g. rings, linear arrays, buses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
    • F02B—INTERNAL-COMBUSTION PISTON ENGINES; COMBUSTION ENGINES IN GENERAL
    • F02B75/00—Other engines
    • F02B75/02—Engines characterised by their cycles, e.g. six-stroke
    • F02B2075/022—Engines characterised by their cycles, e.g. six-stroke having less than six strokes per cycle
    • F02B2075/027—Engines characterised by their cycles, e.g. six-stroke having less than six strokes per cycle four

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Complex Calculations (AREA)
GB929206126A 1992-03-20 1992-03-20 Parallel vector processor architecture Pending GB9206126D0 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB929206126A GB9206126D0 (en) 1992-03-20 1992-03-20 Parallel vector processor architecture
PCT/GB1993/000580 WO1993019431A1 (fr) 1992-03-20 1993-03-22 Architecture de processeur vectoriel en parallele
AU37620/93A AU3762093A (en) 1992-03-20 1993-03-22 Parallel vector processor architecture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB929206126A GB9206126D0 (en) 1992-03-20 1992-03-20 Parallel vector processor architecture

Publications (1)

Publication Number Publication Date
GB9206126D0 true GB9206126D0 (en) 1992-05-06

Family

ID=10712538

Family Applications (1)

Application Number Title Priority Date Filing Date
GB929206126A Pending GB9206126D0 (en) 1992-03-20 1992-03-20 Parallel vector processor architecture

Country Status (3)

Country Link
AU (1) AU3762093A (fr)
GB (1) GB9206126D0 (fr)
WO (1) WO1993019431A1 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2045095C1 (ru) * 1994-09-14 1995-09-27 Виталий Оскарович Гроппен Способ оптимального формирования визуального изображения
US5768445A (en) * 1996-09-13 1998-06-16 Silicon Graphics, Inc. Compression and decompression scheme performed on shared workstation memory by media coprocessor
WO2000068882A1 (fr) * 1999-05-10 2000-11-16 Sony Corporation Appareil et procede de traitement d'images, et robot associe
US6460120B1 (en) * 1999-08-27 2002-10-01 International Business Machines Corporation Network processor, memory organization and methods
FR3011659B1 (fr) * 2013-10-04 2015-10-16 Commissariat Energie Atomique Circuit electronique, notamment apte a l'implementation d'un reseau de neurones, et systeme neuronal
CN106528047B (zh) * 2015-10-08 2019-04-09 上海兆芯集成电路有限公司 一种处理器、神经网络单元及其运作方法
CN105468335B (zh) * 2015-11-24 2017-04-12 中国科学院计算技术研究所 流水级运算装置、数据处理方法及片上网络芯片
US11263011B2 (en) 2018-11-28 2022-03-01 International Business Machines Corporation Compound instruction set architecture for a neural inference chip
CN113342721B (zh) * 2021-07-06 2022-09-23 无锡众星微系统技术有限公司 存储控制器dma设计方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5163133A (en) * 1987-02-17 1992-11-10 Sam Technology, Inc. Parallel processing system having a broadcast, result, and instruction bus for transmitting, receiving and controlling the computation of data
WO1991019259A1 (fr) * 1990-05-30 1991-12-12 Adaptive Solutions, Inc. Architecture distributive et numerique de maximalisation, et procede
FR2666670B1 (fr) * 1990-09-11 1994-07-01 Lawson Jean Christophe Coprocesseur de calcul parallele optimise pour les traitements a base de matrices creuses.

Also Published As

Publication number Publication date
AU3762093A (en) 1993-10-21
WO1993019431A1 (fr) 1993-09-30

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