GB2638320A - Pixel ciruit and display device including the same - Google Patents

Abstract

A pixel circuit includes: a driving element, DT, including a first electrode connected to a first power line, EVDD, a gate electrode connected to a first node, n1, and a second electrode connected to a second node, n2; a first switch element, T1, configured to apply a data voltage, Vdata, to the first node in response to a first gate signal, SCAN; a second switch element, T2, configured to connect a third node, n3, to the second node in response to a reset signal, RESET, or the first gate signal; a third switch element, T3, configured to connect a sensing line, SL, to the third node in response to a second gate signal, SENSE; a fourth switch element, T4, configured to connect a second power line, EVSS, to the third node in response to a third gate signal, EM; a capacitor, Cst, connected between the first node and the second node; and a light-emitting element, EL, connected between the second node and the third node.

Description

PIXEL CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0193950, filed on December 28, 2023, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

Field

[0002] The present disclosure relates to a pixel circuit and a display device including the same.

Description of Related Art

[0003] Display devices include a liquid crystal display (LCD) device, an electroluminescence display device, a field emission display (FED) device, a plasma display panel (PDP), and the like.

[0004] Electroluminescent display devices are divided into inorganic light emitting display devices and organic light emitting display devices according to a material of a light emitting layer. An active-matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as an "OLED") which emits light by itself, and has advantages in that a response speed is fast and luminous efficiency, luminance, and a viewing angle are large.

[0005] Some display devices, for example, a liquid crystal display device or an organic light emitting display device include a display panel including a plurality of sub-pixels, a driver outputting a driving signal for driving the display panel, a power supply generating power to be supplied to the display panel or the driver, and the like. The driver includes a gate driver that supplies a gate signal, such as a scan signal and emission signal to the display panel, and a data driver that supplies a data signal to the display panel.

SUMMARY

[0006] Each of a plurality of pixels includes an OLED and a driving element which supplies current that flows to the OLED according to a gate-source voltage Vgs. Since an afterimage may appear on a screen due to deterioration of the OLED in addition to the driving element, various schemes for being able to sense deterioration information of the OLED have been presented.

[0007] However, the operating voltage of the OLED is unable to be directly sensed, and a deterioration tendency is sensed by using an operating point relationship between the driving element and the OLED. If such a deterioration tendency is sensed, the characteristic of the driving element is unable to be completely excluded, and thus compensation for this is required.

[0008] The present disclosure is directed to solving all the above-described necessities and problems.

[0009] The present disclosure provides a pixel circuit and a display device including the same.

[0010] It should be noted that objects of the present disclosure are not limited to the above-described objects, and other objects of the present disclosure will be apparent to those skilled in the art from the following descriptions.

[0011] According to a first aspect there is provided a pixel circuit comprising a driving element including a first electrode connected to a first power line, a gate electrode connected to a first node, and a second electrode connected to a second node, a first switch element configured to apply a data voltage to the first node in response to a first gate signal, a second switch element configured to connect a third node to the second node in response to a reset signal or the first gate signal, a third switch element configured to connect a sensing line to the third node in response to a second gate signal, a fourth switch element configured to connect a second power line to the third node in response to a third gate signal, a capacitor connected between the first node and the second node; and a light-emitting element connected between the second node and the third node.

[0012] A display device according to embodiments of the present disclosure may include at least one pixel circuit of any preceding claim; and a data driver associated with each pixel circuit.

[0013] According to the present disclosure, the operating voltage of the light-emitting element may be directly sensed in a state where the characteristic of the driving element is completely excluded by additionally constituting a switch element for sensing the operating voltage of the light-emitting element.

[0014] Even in the structure in which the sensing line is shared, it is possible to extract the characteristic of the light-emitting element for each pixel by applying a data voltage of a relatively high voltage level to the pixel circuit that is intended to be sensed and by applying a data voltage of a relatively low voltage level to the pixel circuit that is not to be sensed.

[0015] According to the present disclosure, since the pixel circuit may be selectively sensed, low-power driving may be possible.

[0016] The effects of the present specification are not limited to the above-mentioned effects, and other effects that are not mentioned will be apparently understood by those skilled in the art from the following description and the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features, and advantages of the present disclosure will become more apparent to those of ordinary skill in the art by describing exemplary embodiments thereof in detail with reference to the attached drawings, in which: [0018] FIG. 1 is a block diagram showing a display device according to an

embodiment of the present disclosure;

[0019] FIG. 2 is a diagram showing time to enter a sensing mode in a driving sequence of a display device; [0020] FIG. 3 is a diagram showing a pixel circuit and a compensation circuit according to a first embodiment of the present disclosure; [0021] FIG. 4 is a diagram illustrating a display mode driving timing of a pixel circuit illustrated in FIG. 3; [0022] FIGS. 5A to 5C are diagrams explaining an operation of a pixel circuit by FIG. 4; [0023] FIG. 6 is a diagram illustrating a first sensing mode driving timing of a pixel circuit illustrated in FIG. 3; [0024] FIGS. 7A to 7C are diagrams explaining an operation of a pixel circuit by FIG. 6; [0025] FIG. 8 is a diagram illustrating a second sensing mode driving timing of a pixel circuit illustrated in FIG. 3; [0026] FIGS. 9A to 9D are diagrams explaining an operation of a pixel circuit according to FIG. 8; [0027] FIG. 10 is a diagram showing a modified pixel circuit of a first embodiment illustrated in FIG. 3; [0028] FIG. 11 is a diagram showing a pixel circuit and a compensation circuit according to a second embodiment of the present disclosure; [0029] FIG. 12 is a diagram illustrating a display mode driving timing of a pixel circuit illustrated in FIG. 11; [0030] FIGS. 13A to 13C are diagrams explaining an operation of a pixel circuit by FIG. 12; [0031] FIG. 14 is a diagram illustrating a first sensing mode driving timing of a pixel circuit illustrated in FIG. 11; [0032] FIGS. 15A to 15C are diagrams explaining an operation of a pixel circuit by FIG. 14; [0033] FIG 16 is a diagram illustrating a second sensing mode driving timing of a pixel circuit illustrated in FIG. 11; [0034] FIGS. 17A to 17D are diagrams explaining an operation of a pixel circuit by FIG. 16; [0035] FIG. 18 is a diagram showing a pixel circuit and a compensation circuit according to a third embodiment of the present disclosure; [0036] FIGS. 19A to 19C are diagrams explaining an operation for each mode of a pixel circuit illustrated in FIG. 18; [0037] FIG. 20 is a diagram showing a modified pixel circuit of a third embodiment illustrated in FIG. 18; [0038] FIG. 21 is a diagram showing a pixel circuit and a compensation circuit according to a fourth embodiment of the present disclosure; and [0039] FIGS. 22A to 22C are diagrams explaining an operation for each mode of a pixel circuit illustrated in FIG. 21.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0040] Advantages and features of the present specification and methods of achieving them will become apparent with reference to preferable embodiments, which are described in detail, in conjunction with the accompanying drawings.

However, the present specification is not limited to the embodiments to be described below and may be implemented in different forms, the embodiments are only provided to completely disclose the present disclosure and completely convey the scope of the present disclosure to those skilled in the art, and the present specification is defined by the disclosed claims.

[0041] Since the shapes, sizes, proportions, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present disclosure are only exemplary, the present disclosure is not limited to the illustrated items. The same reference numerals indicate the same components throughout the specification. Further, in describing the present disclosure, when it is determined that a detailed description of related known technology may unnecessarily obscure the gist of the present disclosure, the detailed description thereof will be omitted.

[0042] When ncluding,"having,' 'comprising,' and the like mentioned in the present specification are used, other parts may be added unless 'only' is used. A case in which a component is expressed in a singular form includes a plural form unless explicitly stated otherwise.

[0043] In interpreting the components, it should be understood that an error range is included even when there is no separate explicit description.

[0044] In the case of a description of a positional relationship, for example, when the positional relationship of two parts is described as 'on, at an upper portion,' at a lower portion,' next to', and the like, one or more other parts may be located between the two parts unless 'immediately' or 'directly' is used.

[0045] Although first, second, and the like are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, a first component, which is mentioned, below may also be a second component within the technical spirit of the present disclosure.

[0046] The same reference numerals may refer to substantially the same

elements throughout the present disclosure.

[0047] The following embodiments can be partially or entirely bonded to or combined with each other and can be linked and operated in technically various ways.

The embodiments can be carried out independently of or in association with each other.

[0048] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0049] In a display device of the present disclosure, the pixel circuit and the gate driving circuit may include a plurality of transistors. Transistors may be implemented as oxide thin film transistors (oxide TFTs) including an oxide semiconductor, low temperature polysilicon (LTPS) TFTs including low temperature polysilicon, or the like.

[0050] A transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. In the transistor, carriers start to flow from the source. The drain is an electrode through which carriers exit from the transistor. In a transistor, carriers flow from a source to a drain. In the case of an n-channel transistor,since carriers are electrons, a source voltage is a voltage lower than a drain voltage such that electrons may flow from a source to a drain. The n-channel transistor has a direction of a current flowing from the drain to the source. In the case of a p-channel transistor (p-channel metal-oxide semiconductor (PMOS)), since carriers are holes, a source voltage is higher than a drain voltage such that holes may flow from a source to a drain. In the p-channel transistor, since holes flow from the source to the drain, a current flows from the source to the drain. It should be noted that a source and a drain of a transistor are not fixed. For example, a source and a drain may be changed according to an applied voltage. Therefore, the disclosure is not limited due to a source and a drain of a transistor. In the following description, a source and a drain of a transistor will be referred to as a first electrode and a second electrode.

[0051] A gate signal swings between a gate-on voltage and a gate-off voltage.

The gate-on voltage is set to a voltage higher than a threshold voltage of a transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

[0052] The transistor is turned on in response to the gate-on voltage and is turned off in response to the gate-off voltage. In the case of the n-channel transistor, a gate-on voltage may be a gate high voltage, and a gate-off voltage may be a gate low voltage. In the case of the p-channel transistor, a gate-on voltage may be a gate low voltage, and a gate-off voltage may be a gate high voltage.

[0053] FIG. 1 is a block diagram showing a display device according to an embodiment of the present disclosure. FIG. 2 is a diagram showing time to enter a sensing mode in a driving sequence of a display device.

[0054] Referring to FIG. 1, the display device according to an embodiment of the present disclosure includes a display panel 100, and a display panel driving circuit for writing pixel data to pixels of the display panel 100. Additionally, the display device includes a power supply 150.

[0055] The display panel 100 may be, but not limited to, a panel having a rectangular structure with a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. For example, the display panel may be a heterogeneous panel of which at least a portion is curved or elliptical.

[0056] The display area AA of the display panel 100 includes a pixel array to display an input image. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 crossing the data lines 102, and pixels 101 arranged in a matrix form. The display panel 100 may further include power lines commonly connected to the pixels. The power lines may be commonly connected to pixel circuits to supply a voltage required for driving pixels 101 to the pixels 101.

[0057] Each of the pixels 101 may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color implementation. Each pixel may further include a white sub-pixel. Each sub-pixel includes a pixel circuit for driving a light emitting element. The light emitting element may include an OLED or an inorganic light emitting diode (LED). Each pixel circuit is connected to the data lines, the gate lines, and the power lines. In the following description, a pixel may be interpreted as a sub-pixel.

[0058] The pixels may be arranged as real color pixels and pentile pixels. A pentile pixel may realize a higher resolution than a real color pixel by driving two sub-pixels with different colors as one pixel 101 and using a preset pixel rendering algorithm. This pixel rendering algorithm may compensate for insufficient color representation in each pixel with the color of light emitted from adjacent pixels.

[0059] Each of the pixels may include at least one first light-emitting element that emits light in first mode, and a second light-emitting element that emits light in second mode. Each of the pixels 101 emits light from the first light-emitting element at a wide viewing angle in first mode, while emitting light from the second light-emitting element at a narrow viewing angle in second mode.

[0060] The display area AA includes a plurality of pixel lines Ll to Ln. Each of the pixel lines LI to Ln includes one line of pixels arranged along the line direction (X-axis direction) in the pixel array of the display panel 100. Those pixels arranged in one pixel line share the gate lines 103. The pixels arranged in the column direction Y along the data line direction share the same data line 102. One horizontal period is a time obtained by dividing one frame period by the total number of pixel lines LI to Ln.

[0061] The display panel 100 may be implemented with a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device in which an image is displayed on the screen and a real object in the background is visible. The display panel 100 may be made of a flexible display panel.

[0062] The power supply 150 receives an input voltage applied from the host system 300 and outputs a voltage needed to drive the pixels 101 of the display panel 100 and the display panel driving circuit. To this end, the power supply 150 may include a direct current to direct current converter (DC-DC converter). The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, and the like. The power supply 150 may output a constant voltage (or direct current voltage), such as gate-on voltage, gate-off voltage, pixel driving voltage, cathode voltage, reference voltage, IC driving voltage of the display panel driving circuit, through the DC-DC converter. The gate-on voltage and the gate-off voltage may be supplied to the level shifter 140 and the gate driver 120. Voltages such as pixel driving voltage, cathode voltage, and reference voltage may be supplied to the pixels 101 through the power lines commonly connected to the pixels 101.

[0063] The power supply 150 may further include a gamma voltage generator.

The gamma voltage generator receives a high-potential reference voltage and a low-potential reference voltage and outputs a plurality of gamma reference voltages divided at specific intervals on a preset gamma curve, for example, a 2.2 gamma curve. The gamma reference voltages are supplied to the data driver 110. In the data driver 110, the gamma reference voltages are subdivided by a voltage dividing circuit into grayscale voltages. The gamma voltage generator may be implemented with a programmable gamma circuit that may adjust the level of each of the gamma reference voltages according to digital data. The timing controller 130, the host system 300, or a separate external device may update digital data stored in a register of the programmable gamma circuit through a communication interface.

[0064] The display panel driving circuit writes pixel data of the input image to the pixels 101 of the display panel 100 under the control of the timing controller 130. The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0065] The display panel driving circuit may further nclude a touch sensor driver for driving touch sensors. The touch sensor driver is not shown in FIG. 1.

The data driver 110 and the touch sensor driver may be integrated into one source drive IC.

[0066] The data driver 110 receives pixel data of the input image as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 may receive gamma reference voltages and generate gamma compensation voltages for each grayscale through a voltage dividing circuit. The per-grayscale gamma compensation voltages are supplied to a digital to analog converter (hereinafter referred to as "DAC") disposed in each channel of the data driver 110.

[0067] The data driver 110 samples and latches digital data received from the timing controller 130 and then inputs the digital data to the DAC. Here, the digital data includes pixel data of the input image. Additionally, the digital data may include mode selection data for selecting first mode and second mode. The DAC converts the pixel data into a gamma compensation voltage and outputs a data voltage of the pixel data.

[0068] The data driver 110 may apply a data voltage of a predetermined voltage level to a pixel circuit selected for sensing in a first sensing mode for sensing or measuring the threshold voltage of the driving element in the pixel circuit, and may apply a data voltage of 0 V or a black grayscale to a pixel circuit that is not selected.

[0069] The data driver 110 may apply a data voltage of a maximum voltage level or a data voltage generated using a maximum gamma voltage to a pixel circuit selected for sensing in a second sensing mode for sensing or measuring the threshold voltage of the light-emitting element in the pixel circuit, and may apply a data voltage of 0 V or a black grayscale to a pixel circuit that is not selected.

[0070] The gate driver 120 may be formed on the display panel 100 together with the circuit elements and wiring lines of the display area AA. The gate driver may be disposed in at least one of left and right non-display areas NA outside the display area AA in the display panel 100 or at least a part thereof may be disposed within the display area AA.

[0071] The gate driver 120 may be disposed in the non-display areas NA on both sides of the display panel 100 with the display area AA of the display panel interposed therebetween to supply gate pulses on both sides of the gate lines 103 in a double feeding method. In another embodiment, the gate driver 120 may be disposed in at least one of the left and right non-display areas NA of the display panel 100 to supply gate signals to the gate lines 103 in a single feeding method.

The gate driver 120 sequentially outputs pulses of the gate signals to the gate lines 103 under the control of the timing controller 130. The gate driver 120 may sequentially supply the gate signals to the gate lines 103 by shifting the pulses of the gate signals using shift registers. When a plurality of gate signals are applied to each pixel, the gate driver 120 may include a plurality of shift registers. The gate signal may include a scan signal being input to the pixel circuit through a plurality of gate lines, and an emission signal (or EM signal).

[0072] The timing controller 130 receives digital video data of an input image and a timing signal synchronized with this data from the host system 300. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since the vertical period and horizontal period may be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The horizontal synchronization signal Hsync and the data enable signal DE have a periodicity of 1 horizontal period (1H).

[0073] The timing controller 130 may control the display panel driving circuit by generating a data timing control signal for controlling the operation timing of the data driver 110 and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, DE received from the host system 300. The timing controller 130 may synchronize the data driver and the gate driver 120 by controlling the operation timing of the display panel driving circuit.

[0074] The gate timing control signal output from the timing controller 130 may be input to the shift register of the gate driver 120 through the level shifter 140.

The level shifter 140 may convert a voltage of the gate timing control signal received from the timing controller 130 to a swing width between the gate-on voltage and the gate-off voltage and supply it to the gate driver 120.

[0075] The host system 300 may include a main board of one of a television system, a set-top box, a navigation system, a personal computer (PC), a vehicle system, a mobile terminal, and a wearable terminal. The host system 300 may scale an image signal from a video source according to the resolution of the display panel 100, and may transmit it to the timing controller 130 together with the timing signals.

[0076] The host system 300 may transmit a mode signal having different logic values in first mode and second mode together with an image signal to the timing controller 130 at least once per frame.

[0077] The display panel driving circuit writes the pixel data of the input image into the pixels 101 by scanning the pixels in the display mode under the control of the timing controller HO. In the display mode, the input image is reproduced on the display area AA. The sensing circuit sequentially senses the threshold voltages of the driving elements in all the sub-pixels by sensing the sub-pixels in the display area AA line by line in the sensing mode.

[0078] The display device may enter the sensing mode in at least one of the following sequences: a Power ON sequence ON RF in which power is applied to the display device, a Vertical Blank time VB within the display time, and a Power OFF sequence OFF RS in which the power-off switch of the display device is turned on (activated), as shown in FIG. 2. The vertical blank time VB is a blank period, excluding an active period AT, during which the pixel data of the input image is written to the pixels within a one-frame period. During the vertical blank time VB, no pixel data is inputted to the data driver 110 and no pixel data is written to the sub-pixels. During the active period AT, the pixel data is inputted to the data driver 110, and the data voltage outputted from the data driver 110 is charged to the sub-pixels so that the pixel data is written to the sub-pixels.

[0079] In the Power OFF sequence, the sensing circuit is further driven for a predetermined period of time after the power-off switch is turned on to sense the threshold voltage of the driving element in each of the sub-pixels, and then stops its driving when the power is cut off. During the sensing time, the sensing data outputted from the sensing channels of the data driver 110 is transmitted to the timing controller 130.

[0080] FIG. 3 is a diagram showing a pixel circuit and a compensation circuit according to a first embodiment of the present disclosure.

[0081] Referring to FIG. 3, a pixel circuit according to the first embodiment includes a light-emitting element EL, a driving element DT that supplies current to the light-emitting element EL, a plurality of switch elements T1 to T4 which switch a current path connected to the driving element DT, and a capacitor Cst that stores a gate-source voltage of the driving element DT. The driving element DT and the plurality of switch elements T1 to T4 may be implemented as n-channel TFTs, but are not limited thereto.

[0082] The light-emitting element EL emits light by current that is applied through a channel of the driving element DT according to the gate-source voltage Vgs of the driving element DT that is changed according to a data voltage Vdata. The light-emitting element EL may be implemented as an OLED including an organic compound layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, a light emission layer EML, an electron transport layer ETL, and an electron injection layer EIL, but is not limited thereto. The anode of the light-emitting element EL is connected to the driving element DT through a second node n2, and the cathode of the light-emitting element EL is connected to a low-potential power voltage line 42 to which a low-potential power voltage EVSS is applied.

[0083] The OLED that is used as the light-emitting element EL may be a tandem structure in which a plurality of light emission layers are stacked. The OLED of the tandem structure can improve the luminance and lifetime of pixels.

[0084] The driving element DT drives the light-emitting element EL by supplying current to the light-emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to a first node nl, a first electrode (or drain) connected to a pixel driving voltage line to which a pixel driving voltage EVDD is applied (also known as first power line 41), and a second electrode (or source) connected to the second node n2.

[0085] The first switch element T1 is turned on according to a gate-on voltage of a first gate signal SCAN, and connects a data line DL to the first node n 1 to supply the data voltage Vdata to the first node nl. The first switch element Ti includes a gate electrode to which the first gate signal SCAN is applied, a first electrode connected to the data line DL, and a second electrode connected to the first node nl.

[0086] The second switch element T2 is turned on according to a reset signal RESET, and connects the second node n2 to a third node n3. The second switch element T2 includes a gate electrode to which a reset signal RESET is applied, a first electrode connected to the second node n2, and a second electrode connected to the third node n3.

[0087] The third switch element T3 is turned on according to a gate-on voltage of a second gate signal SENSE, and connects a sensing line SL or a third power line 43 to the third node n3 to supply a reference voltage to the third node n3. The third switch element T3 includes a gate electrode to which the second gate signal SENSE is applied, a first electrode connected to the third node n3, and a second electrode connected to the third power line 43 to which the reference voltage is applied.

[0088] The fourth switch element T4 is turned on according to a gate-on voltage of a third gate signal EM, and connects a pixel base voltage line (or low-potential power voltage line) to which a pixel base voltage (or low-potential power voltage) EVSS is applied or a second power line 42 to the third node n3. The fourth switch element T4 includes a gate electrode to which the third gate signal EM is applied, a first electrode connected to the third node n3, and a second electrode connected to the second power line 42.

[0089] The capacitor Cst may be connected between the first node n1 and the second node n2. The capacitor Cst may be charged with the gate-source voltage Vgs of the driving element DT.

[0090] A compensation circuit may include a sensing part 111 connected to the pixel circuit in each pixel. The sensing part 111 may sense the electrical characteristics of the pixels through a sensing line SL. Here, the electrical characteristics of the pixels may include a threshold voltage of the driving element and a threshold voltage of the light-emitting element.

[0091] The sensing part 111 may be disposed in the data driver 110 together with a digital-to-analog converter DAC.

[0092] The sensing part 111 may sense the electrical characteristics of the light-emitting element and the driving element for each pixel. The sensing part 111 may include an analog-to-digital converter ADC, a first switch SPRE, and a second switch SAM.

[0093] In a display mode, the first switch SPRE connected to a reference voltage line to which a reference voltage Vprer is applied or a third power line 43 is turned on, and the second switch SAM is turned off, so that the reference voltage Vprer may be supplied to the pixel circuit through a sensing line SL.

[0094] In a sensing mode after the power-off, the first switch SPRE is turned off, and the second switch SAM connected to the analog-to-digital converter ADC is turned on, so that the current that flows through a channel of the driving element DT, or the threshold voltage of the driving element DT and the operating voltage of the light-emitting element EL may be sensed through the sensing line SL. The current that flows through the sensing line SL may be converted into digital data through the analog-to-dimital converter ADC, and the converted digital data may be transferred to the timing controller. The digital data is sensing data including the threshold voltage Vth of the driving element DT and the operating voltage of the light-emitting element. The operating voltage of the light-emitting element may be the threshold voltage of the light-emitting element.

[0095] FIG. 4 is a diagram illustrating a display mode driving timing of a pixel circuit illustrated in FIG. 3. FIGS. 5A to 5C are diagrams explaining an operation of a pixel circuit by FIG. 4.

[0096] Referring to FIG. 4, in a display mode after the power-on of the display device, the pixel circuit may be driven in the order of an initialization and data writing period Tini/w, a boosting period Tboost, and a light emission period Tern.

[0097] In the display mode, the first switch SPRE is on, and the second switch SAM maintains an off state.

[0098] Referring to FIGs. 4 and 5A, in the initialization and data writing period Tini/w, the fourth switch element T4 is turned off, and the first to third switch elements T1 to T3 are turned on, so that the data voltage Vdata is supplied to the first node nl, and the second node n2 is initialized to the reference voltage Vprer.

[0099] Referring to FIGs. 4 and 5B, in the boosting period Tboost, the first to third switch element T1 to T3 are turned off, and the fourth switch element T4 is turned on, so that the voltage of the first node n1 may be boosted.

[00100] Referring to FIGs. 4 and 5C, in the light emission period Tem, the first to third switch elements T1 to T3 are turned off, and the fourth switch element T4 maintains a turn-on state, so that the current may flow through the driving element DT by the pixel driving voltage, and thus the light-emitting element EL may emit light.

[00101] FIG. 6 is a diagram illustrating a first sensing mode driving timing of a pixel circuit illustrated in FIG. 3. FIGS. 7A to 7C are diagrams explaining an operation of a pixel circuit by FIG. 6.

[00102] Referring to FIG. 6, in the first sensing mode after the power-off of the display device, the pixel circuit may be driven in the order of an initialization and data writing period Tini/w, a sensing period Ts, and a sampling period Tsam.

[00103] In the first sensing mode, the threshold voltage of the driving element DT may be sensed through the sensing line SL. During an entire period of the first sensing mode, the first to third switch elements T1 to T3 may be turned on, and the fourth switch element T4 may be turned off.

[00104] Referring to FIGS. 6 and 7A, in the initialization and data writing period Tini/w, the second switch SAIVI is turned off, the first switch SPRE is turned on, the fourth switch element T4 is turned off, and the first to third switch elements T1 to T3 are turned on, so that the data voltage Vdata is supplied to the first node nl, and the reference voltage Vprer is supplied to the second node n2.

[00105] Referring to FIGS. 6 and 7B, in the sensing period Ts, the first switch SPRE is switched to a turn-off state, and the supply of the reference voltage Vprer to the second node n2 is blocked. Accordingly, the voltage of the second node n2 rises by the pixel driving voltage EVDD.

[00106] Referring to FIGS. 6 and 7C, in the sampling period Tsam, the second switch SAM is switched to a turn-on state, and the threshold voltage of the driving element DT is sampled through the sensing line SL.

[00107] The sampled threshold voltage of the driving element DT may be converted into digital data by the analog-to-digital converter ADC in the data driver, and the converted digital data may be transferred to the timing controller.

[00108] FIG. 8 is a diagram illustrating a second sensing mode driving timing of a pixel circuit illustrated in FIG. 3. FIGS. 9A to 9D are diagrams explaining an operation of a pixel circuit according to FIG. 8.

[00109] Referring to FIG. 8, in the second sensing mode after the power-off of the display device, the pixel circuit may be driven in the order of an initialization and data writing period Tini/w, a programming period Tp, a sensing period Ts, and a sampling period Tsam.

[00110] In the second sensing mode, the threshold voltage of the light-emitting element EL may be sensed through the sensing line SL.

[00111] Referring to FIGS. 8 and 9A, in the initialization and data writing period Tini/w, the second switch SAM is turned off, the first switch SPRE is turned on, the fourth switch element T4 is turned off, and the first to third switch elements T1 to T3 are turned on, so that the data voltage Vdata is supplied to the first node nl, and the reference voltage Vprer is supplied to the second node n2. In this case, the reference voltage Vprer may be, for example, in the range of 0 to 1 V, but is not necessarily limited thereto. Further, as the data voltage Vdata, a relatively high voltage for using the driving element as a switch element is used. For example, the data voltage Vdata may be about 16 V [00112] In the second sensing mode, the data voltage Vdata that is applied to the pixel circuit selected for the sensing may be a data voltage of the maximum voltage level or a data voltage generated by using the maximum gamma voltage. The data voltage that is applied to the non-selected pixel circuit may be a data voltage of 0 V or a black grayscale.

[00113] Since data voltages of different voltage levels are applied to respective pixel circuits depending on whether to select for sensing, the sensing for each pixel may be possible even if the sensing line is shared.

[00114] Referring to FIGS. 8 and 9B, in the programming period Tp, the first to second switch elements Tt to T2 and the fourth switch element T4 are turned off, and the third switch element T3 is turned on, so that the light-emitting element EL emits light, the voltage of the second node n2 rises up to the pixel driving voltage EVDD, and the voltage of the third node n3 maintains the reference voltage Vprer.

[00115] Referring to FIGS. 8 and 9C, in the sensing period Ts, the first switch SPRE is switched to be turned off, the first to second switch elements Tt to T2 and the fourth switch element T4 are turned off, and the third switch element T3 maintains a turn-on state, so that the sensing line becomes in a floating state, and the voltage of the sensing line rises until the light-emitting element emits light and then is turned off [00116] Referring to FIGS. 8 and 9D, in the sampling period Tsam, the second switch SAM is switched to be turned on, and the threshold voltage of the light-emitting element EL is sampled through the sensing line SL.

[00117] The sampled threshold voltage of the light-emitting element EL may be converted into digital data by the analog-to-digital converter ADC in the data driver, and the converted digital data may be transferred to the timing controller.

[00118] FIG. 10 is a diagram showing a modified pixel circuit of a first embodiment illustrated in FIG. 3.

[00119] Referring to FIG. 10, a modified pixel circuit of the first embodiment includes a light-emitting element EL, a driving element DT that supplies current to the light-emitting element EL, a plurality of switch elements T1 to T4 which switch a current path connected to the driving element DT, and a capacitor Cst that stores a gate-source voltage of the driving element DT.

[00120] The modified pixel circuit of the first embodiment illustrated in FIG. 10 may be configured so that the first gate signal SCAN that is not the reset signal 25 RESET is applied to the gate electrode of the second switch element T2.

[00121] In the modified embodiment, since the gate signal being used in another switch element, which is not the reset signal, is used as it is, an additional wiring is not required as compared with the first embodiment, and thus that much space can be secured, and the cost can be saved as well.

[00122] FIG. 11 is a diagram showing a pixel circuit and a compensation circuit according to a second embodiment of the present disclosure.

[00123] Referring to FIG. 11, a pixel circuit according to a second embodiment includes a light-emitting element EL, a driving element DT that supplies current to the light-emitting element EL, a plurality of switch elements T1 to T4 which switch a current path connected to the driving element DT, and a capacitor Cst that stores a gate-source voltage of the driving element DT. The driving element DT and the switch elements T1 to T4 may be implemented as n-channel TFTs, but are not limited thereto.

[00124] The light-emitting element EL emits light by current that is applied through a channel of the driving element DT according to the gate-source voltage Vgs of the driving element DT that is changed according to a data voltage Vdata.

[00125] The driving element DT drives the light-emitting element EL by supplying current to the light-emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to a first node nl, a first electrode (or drain) connected to a pixel driving voltage line to which a pixel driving voltage EVDD is applied (also known as first power line 41), and a second electrode (or source) connected to a second node n2.

[00126] The first switch element T1 is turned on according to a gate-on voltage of a first gate signal SCAN, and connects a data line DL to the first node n1 to supply the data voltage Vdata to the first node nl. The first switch element T1 includes a gate electrode to which the first gate signal SCAN is applied, a first electrode connected to the data line DL, and a second electrode connected to the first node nl.

[00127] The second switch element T2 is turned on according to a second gate signal SENSE1, and connects a sensing line SL to the second node n2 to supply a reference voltage Vprer to the second node n2. The second switch element T2 includes a gate electrode to which the second gate signal SENSE1 is applied, a first electrode connected to the second node n2, and a second electrode connected to the sensing line SL.

[00128] The third switch element T3 is turned on according to a gate-on voltage of a third gate signal SENSE2, and connects the sensing line SL to the third node n3 to supply a reference voltage to the third node n3. The third switch element T3 includes a gate electrode to which a third gate signal SENSE2 is applied, a first electrode connected to the third node n3, and a second electrode connected to the sensing line SL.

[00129] The fourth switch element T4 is turned on according to a gate-on voltage of a fourth gate signal EM, and connects a pixel base voltage line to which a pixel base voltage EVSS is applied or a second power line 42 to the third node n3 The fourth switch element T4 includes a gate electrode to which the fourth gate signal EM is applied, a first electrode connected to the third node n3, and a second electrode connected to the second power line 42.

[00130] The capacitor Cst may be connected between the first node n1 and the second node n2. The capacitor Cst may be charged with the gate-source voltage Vgs of the driving element DT.

[00131] A compensation circuit may include a sensing part 111 connected to the pixel circuit in each pixel. The sensing part 111 may sense the electrical characteristics of the pixels through the sensing line SL.

[00132] The sensing part 111 may be disposed in the data driver 110 together with a DAC.

[00133] The sensing part 111 may sense the electrical characteristics of the light-emitting element and the driving element for each pixel. The sensing part 111 may include an analog-to-digital converter ADC, a first switch SPRE, and a second switch SAM.

[00134] In a display mode, the first switch SPRE connected to a reference voltage line to which a reference voltage Vprer is applied or a third power line 43 is turned on, and the second switch SAM is turned off, so that the reference voltage Vprer may be supplied to the pixel circuit through a sensing line SL.

[00135] In a sensing mode after the power-off, the first switch SPRE is turned off and the second switch SAM connected to the analog-to-digital converter ADC is turned on, so that the current that flows through a channel of the driving element DT, or the threshold voltage of the driving element DT and the threshold voltage of the light-emitting element EL may be sensed through the sensing line SL. The current that flows through the sensing line SL may be converted into digital data through the analog-to-digital converter ADC, and the converted digital data may be transferred to the riming controller.

[00136] FIG. 12 is a diagram illustrating a display mode driving timing of a pixel circuit illustrated in FIG. 11. FIGS. 13A to 13C are diagrams explaining an operation of a pixel circuit by FIG. 12.

[00137] Referring to FIG. 12, in a display mode after the power-on of the display device, the pixel circuit may be driven in the order of an initialization and data writing period Tini/w, a boosting period Tboost, and a light emission period Tem.

[00138] In the display mode, the first switch SPRE is on, and the second switch SAM maintains an off state.

[00139] Referring to FIGS. 12 and 13A, in the initialization and data writing period Tini/w, the fourth switch element T4 is turned off, and the first to third switch elements T1 to T3 are turned on, so that the data voltage Vdata is supplied to the first node nl, and the second node n2 is initialized to the reference voltage Vprer.

[00140] Referring to FIGS. 12 and 13B, in the boosting period Tboost, the first to third switch element T1 to T3 are turned off, and the fourth switch element T4 is turned on, so that the voltage of the first node n1 may be boosted.

[00141] Referring to FIGS. 12 and 13C, in the light emission period Tern, the first to third switch elements T1 to T3 are turned off, and the fourth switch element T4 maintains a turn-on state, so that the current may flow through the driving element DT by the pixel driving voltage, and thus the light-emitting element EL may emit light.

[00142] FIG. 14 is a diagram illustrating a first sensing mode driving timing of a pixel circuit illustrated in FIG. 11. FIGS. 15A to 15C are diagrams explaining an operation of a pixel circuit by FIG. 14.

[00143] Referring to FIG. 14, in the first sensing mode after the power-off of the display device, the pixel circuit may be driven in the order of an initialization and data writing period Tini/w, a sensing period Ts, and a sampling period Tsam.

[00144] In the first sensing mode, the threshold voltage of the driving element DT may be sensed through the sensing line SL.

[00145] Referring to FIGS. 14 and 15A, in the initialization and data writing period Tini/w, the second switch SAM is turned off, the first switch SPRE is turned on, the fourth switch element T4 is turned off, and the first to third switch elements T1 to T3 are turned on, so that the data voltage Vdata is supplied to the first node nl, and the reference voltage Vprer is supplied to the second node n2.

[00146] Referring to FIGS. 14 and 15B, in the sensing period Ts, the first switch SPRE is switched to a turn-off state, and the supply of the reference voltage Vpref to the second node n2 is blocked. Accordingly, the voltage of the second node n2 rises by the pixel driving voltage EVDD.

[00147] Referring to FIGS. 14 and 15C, in the sampling period Tsam, the second switch SAM is switched to a turn-on state, and the threshold voltage of the driving element DT is sampled through the sensing line SL.

[00148] The sampled threshold voltage of the driving element DT may be converted into digital data by the analog-to-digital converter ADC in the data driver, and the converted digital data may be transferred to the timing controller.

[00149] FIG. 16 is a diagram illustrating a second sensing mode driving timing of a pixel circuit illustrated in FIG. 11. FIGS. 17A to 17D are diagrams explaining an operation of a pixel circuit by FIG. 16.

[00150] Referring to FIG. 16, in the second sensing mode after the power-off of the display device, the pixel circuit may be driven in the order of an initialization and data writing period Tini/w, a programming period Tp, a sensing period Ts, and a sampling period Tsam.

[00151] In the second sensing mode, the threshold voltage of the light-emitting element EL may be sensed through the sensing line SL.

[00152] Referring to FIGS. 16 and 17A, in the initialization and data writing period Tini/w, the second switch SAM is turned off, the first switch SPRE is turned on, the fourth switch element T4 is turned off, and the first to third switch elements T1 to T3 are turned on, so that the data voltage Vdata is supplied to the first node nl, and the reference voltage Vprer is supplied to the second node n2.

[00153] In the second sensing mode, the data voltage Vdata that is applied to the pixel circuit selected for the sensing may be a data voltage of the maximum voltage level or a data voltage generated by using the maximum gamma voltage. The data voltage that is applied to the non-selected pixel circuit may be a data voltage of 0 V or a black grayscale.

[00154] Referring to FIGS. 16 and 17B, in the programming period Tp, the first to second switch elements T1 to T2 and the fourth switch element T4 are turned off, and the third switch element T3 is turned on, so that the light-emitting element EL emits light, the voltage of the second node n2 rises up to the pixel driving voltage EVDD, and the voltage of the third node n3 maintains the reference voltage Vprer.

[00155] Referring to FIGS. 16 and 17C, in the sensing period Ts, the first switch SPRE is switched to be turned off, the first to second switch elements T1 to T2 and the fourth switch element T4 are turned off, and the third switch element T3 maintains a turn-on state, so that the sensing line becomes in a floating state, and the voltage of the sensing line rises until the light-emitting element emits light and then is turned off [00156] Referring to FIGS. 16 and 17D, in the sampling period Tsam, the second switch SAM is switched to be turned on, and the threshold voltage of the light-emitting element EL is sampled through the sensing line SL.

[00157] The sampled threshold voltage of the light-emitting element EL may be converted into digital data by the analog-to-digital converter ADC in the data driver, and the converted digital data may be transferred to the timing controller.

[00158] FIG. 18 is a diagram showing a pixel circuit and a compensation circuit according to a third embodiment of the present disclosure. FIGS. 19A to 19C are diagrams explaining an operation for each mode of a pixel circuit illustrated in FIG. 18.

[00159] Referring to FIG. 18, a pixel circuit according to the third embodiment includes a light-emitting element EL, a driving element DT that supplies current to the light-emitting element EL, a plurality of switch elements Ti to T4 which switch a current path connected to the driving element DT, and a capacitor Cst that stores a gate-source voltage of the driving element DT. The driving element DT and the switch elements T1 to T4 may be implemented as p-channel TFTs, but are not limited thereto.

[00160] The light-emitting element EL emits light by current that is applied through a channel of the driving element DT according to the gate-source voltage Vgs of the driving element DT that is changed according to the data voltage Vdata.

[00161] The driving element DT drives the light-emitting element EL by supplying the current to the light-emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to the first node nl, a first electrode (or source) connected to the second node n2, and a second electrode (or drain) connected to a pixel base voltage line to which a pixel base voltage is applied or a second power line 42.

[00162] The first switch element T1 is turned on according to the gate-on voltage of the first gate signal SCAN, and connects the data line DL to the first node n1 to supply the data voltage Vdata to the first node nl. The first switch element T1 includes a gate electrode to which the first gate signal SCAN is applied, a first electrode connected to the data line DL, and a second electrode connected to the first node nl.

[00163] The second switch element T2 is turned on according to a reset signal RESET, and connects the second node n2 to the third node n3. The second switch element T2 includes a gate electrode to which the reset signal RESET is applied, a first electrode connected to the third node n3, and a second electrode connected to the second node n2 [00164] The third switch element T3 is turned on according to a gate-on voltage of a second gate signal SENSE, and connects the sensing line SL to the third node n3 to supply the reference voltage Vprer to the third node n3 The third switch element T3 includes a gate electrode to which the second gate signal SENSE is applied, a first electrode connected to the third node n3, and a second electrode connected to the sensing line SL.

[00165] The fourth switch element T4 is turned on according to a gate-on voltage of a third gate signal EM, and connects a pixel driving voltage line to which a pixel driving voltage EVDD is applied (also known as first power line 41) to the third node n3 The fourth switch element T4 includes a gate electrode to which the third gate signal EM is applied, a first electrode connected to the first power line 41, and a second electrode connected to the third node n3.

[00166] The capacitor Cst may be connected between the first node n1 and the second node n2. The capacitor Cst may be charged with the gate-source voltage Vgs of the driving element DT.

[00167] A compensation circuit may include a sensing part 111 connected to the pixel circuit in each pixel. The sensing part 111 may sense the electrical characteristics of the pixels through the sensing line SL.

[00168] The sensing part 111 may be disposed in the data driver 110 together with a digital-analog converter DAC.

[00169] The sensing part 111 may sense the electrical characteristics of the light-emitting element and the driving element for each pixel. The sensing part 111 may include an analog-to-digital converter ADC, a first switch SPRE, and a second switch SAM.

[00170] In a display mode, the first switch SPRE connected to the reference voltage line to which the reference voltage Vprer is applied or a third power line 43 is turned on, and the second switch SAM is turned off, so that the reference voltage Vprer may be supplied to the pixel circuit through the sensing line SL.

[00171] In a sensing mode after the power-off, the first switch SPRE is turned off, and the second switch SAM connected to the analog-to-digital converter ADC is turned on, so that the current that flows through a channel of the driving element DT, or the threshold voltage of the driving element DT and the operating voltage of the light-emitting element EL may be sensed through the sensing line SL. The current that flows through the sensing line SL may be converted into digital data through the analog-to-digital converter ADC, and the converted digital data may be transferred to the riming controller.

[00172] Since the pixel circuit according to the third embodiment is driven with the same constitution and the same operating mechanism as those of the pixel circuit according to the first embodiment although the only difference is that it is implemented with the p-channel TFTs, the detailed explanation of the driving method will be omitted.

[00173] Referring to FIG. 19A, in the display mode after the power-on of the display device, the pixel circuit may be driven in the order of an initialization and data writing period Tini/w, a boosting period Tboost, and a light emission period Tem, and thus the light-emitting element EL may emit light to display an image on the screen.

[00174] Referring to FIG. 19B, in the first sensing mode after the power-off of the display device, the pixel circuit may be driven in the order of an initialization and data writing period Tini/w, a sensing period Ts, and a sampling period Tsam, and the threshold voltage of the driving element DT may be sensed through the sensing line SL.

[00175] Referring to FIG. 19C, in the second sensing mode after the power-off of the display device, the pixel circuit may be driven in the order of an initialization and data writing period Tini/w, a programming period Tp, a sensing period Ts, and a sampling period Tsam, and the threshold voltage of the light-emitting element EL may be sensed through the sensing line SL.

[00176] FIG. 20 is a diagram showing a modified pixel circuit of a third embodiment illustrated in FIG. 18.

[00177] Referring to FIG. 20, a modified pixel circuit of the third embodiment includes a light-emitting element EL, a driving element DT that supplies current to the light-emitting element EL, a plurality of switch elements T1 to T4 which switch a current path connected to the driving element DT, and a capacitor Cst that stores a gate-source voltage of the driving element DT.

[00178] The modified pixel circuit of the third embodiment illustrated in FIG. 20 may be configured so that the first gate signal SCAN that is not the reset signal RESET is applied to the gate electrode of the second switch element T2.

[00179] In the modified embodiment, since the gate signal being used in another switch element, which is not the reset signal, is used as it is, an additional wiring is not required as compared with the third embodiment, and thus that much space can be secured, and the cost can be saved as well.

[00180] FIG. 21 is a diagram showing a pixel circuit and a compensation circuit according to a fourth embodiment of the present disclosure. FIGS. 22A to 22C are diagrams explaining an operation for each mode of a pixel circuit illustrated in FIG. 21.

[00181] Referring to FIG. 21, a pixel circuit according to a fourth embodiment includes a light-emitting element EL, a driving element DT that supplies current to the light-emitting element EL, a plurality of switch elements T1 to T4 which switch a current path connected to the driving element DT, and a capacitor Cst that stores a gate-source voltage of the driving element DT. The driving element DT and the switch elements T1 to T4 may be implemented as p-channel TFTs, but are not limited thereto.

[00182] The light-emitting element EL emits light by current that is applied through a channel of the driving element DT according to the gate-source voltage Vgs of the driving element DT that is changed according to a data voltage Vdata.

[00183] The driving element DT drives the light-emitting element EL by supplying current to the light-emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to a first node nt, a first electrode (or source) connected to a second node n2, and a second electrode (or drain) connected to a pixel base voltage line to which a pixel base voltage is applied or a second power line 42.

[00184] The first switch element T1 is turned on according to a gate-on voltage of a first gate signal SCAN, and connects a data line DL to the first node n1 to supply the data voltage Vdata to the first node nt. The first switch element T1 includes a gate electrode to which the first gate signal SCAN is applied, a first electrode connected to the data line DL, and a second electrode connected to the first node nl.

[00185] The second switch element T2 is turned on according to a second gate signal SENSE1, and connects a sensing line SL to the second node n2 to apply a reference voltage Vprer to the second node n2. The second switch element T2 includes a gate electrode to which the second gate signal SENSE1 is applied, a first electrode connected to the second node n2, and a second electrode connected to the sensing line SL.

[00186] The third switch element T3 is turned on according to a gate-on voltage of a third gate signal SENSE2, and connects the sensing line SL to the third node n3 to supply a reference voltage Vprer to the third node n3 The third switch element T3 includes a gate electrode to which the third gate signal SENSE2 is applied, a first electrode connected to the third node n3, and a second electrode connected to the sensing line SL.

[00187] The fourth switch element T4 is turned on according to a gate-on voltage of a fourth gate signal EM, and connects a pixel driving voltage line to which a pixel driving voltage EVDD is applied (also known as first power line 41) to the third node n3. The fourth switch element T4 includes a gate electrode to which the fourth gate signal EM is applied, a first electrode connected to the first power line 41, and a second electrode connected to the third node n3.

[00188] The capacitor Cst may be connected between the first node n1 and the second node n2. The capacitor Cst may be charged with the gate-source voltage Vgs of the driving element DT.

[00189] A compensation circuit may include a sensing part 111 connected to the pixel circuit in each pixel. The sensing part 111 may sense the electrical characteristics of the pixels through the sensing line SL.

[00190] The sensing part 111 may be disposed in the data driver 110 together with a digital-analog converter DAC.

[00191] The sensing part 111 may sense the electrical characteristics of the light- 1 0 emitting element and the driving element for each pixel. The sensing part 111 may include an analog-to-digital converter ADC, a first switch SPRE, and a second switch SAM.

[00192] In a display mode, the first switch SPRE connected to a reference voltage line to which a reference voltage Vprer is applied or a third power line 43 is 15 turned on, and the second switch SAM is turned off, so that the reference voltage Vprer may be supplied to the pixel circuit through the sensing line SL.

[00193] In a sensing mode after the power-off, the first switch SPRE is turned off, and the second switch SAM connected to the analog-to-digital converter ADC is turned on, so that the current that flows through a channel of the driving element DT, or the threshold voltage of the driving element DT and the threshold voltage of the light-emitting element EL may be sensed through the sensing line SL. The current that flows through the sensing line SL may be converted into digital data through the analog-to-digital converter ADC, and the converted digital data may be transferred to the timing controller.

[00194] Since the pixel circuit according to the fourth embodiment is driven with the same constitution and the same operating mechanism as those of the pixel circuit according to the second embodiment although the only difference is that it is implemented with the p-channel TFTs, the detailed explanation of the driving method will be omitted.

[00195] Referring to FIG. 22A, in the display mode after the power-on of the display device, the pixel circuit may be driven in the order of an initialization and data writing period Tini/w, a boosting period Tboost, and a light emission period Tem, and thus the light-emitting element EL may emit light to display an image on the screen.

[00196] Referring to FIG. 22B, in the first sensing mode after the power-off of the display device, the pixel circuit may be driven in the order of an initialization and data writing period Tini/w, a sensing period Ts, and a sampling period Tsam, and the threshold voltage of the driving element DT may be sensed through the sensing line SL.

[00197] Referring to FIG. 22C, in the second sensing mode after the power-off of the display device, the pixel circuit may be driven in the order of an initialization and data writing period Tini/w, a programming period Tp, a sensing period Ts, and a sampling period Tsam, and the threshold voltage of the light-emitting element EL may be sensed through the sensing line SL.

[00198] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and do not limit the present disclosure.

The disclosure also comprises the following numbered clauses: 1. A pixel circuit comprising: a driving element arranged to supply current to a light-emitting element; first to fourth switching elements each comprising a gate electrode arranged to receive a gate signal to switch a current path connected to the driving element; a sensing line for sensing electrical characteristics of the light-emitting element; wherein according to a gate source voltage of the driving element at a first node that is changed according to a data voltage, current is supplied to the light-emitting element through a second node disposed between the driving element and the light-emitting element.

2. The pixel circuit of clause 1, wherein the pixel circuit is configured to be driven in the order of an initialization and data writing period, a sensing period, and a sampling period in a first sensing mode for measuring a threshold voltage of the driving element, and wherein during an entire period of the first sensing mode, the first to third switch elements are turned on, and the fourth switch element is turned off 3. The pixel circuit of clause I, wherein the pixel circuit is configured to be driven in the order of an initialization and data writing period, a programming period, a sensing period, and a sampling period in a second sensing mode for measuring a threshold voltage of the light-emitting element, wherein during the initialization and data writing period, the first to third switch elements are turned on, and the fourth switch element is turned off, wherein during the programming period, the first to second switch elements and the fourth switch element are all turned off, and the third switch element is turned on, and wherein during the sampling period, the third switch is maintained to a turn-on state, and the first to second switch elements and the fourth switch element are all 10 turned off 4. The pixel circuit of clause 3, wherein in the second sensing mode, the data voltage that is applied to the first node is a data voltage corresponding to a maximum gamma voltage.

5. The pixel circuit of any preceding clause, wherein the first switch element comprises a gate electrode to which the first gate signal is applied, a first electrode connected to a data line to which the data voltage is applied, and a second electrode connected to the first node, wherein the second switch element includes a gate electrode to which the reset signal or the first gate signal is applied, a first electrode connected to the second node, and a second electrode connected to the third node, wherein the third switch element includes a gate electrode to which the second gate signal is applied, a first electrode connected to the third node, and a second electrode connected to the sensing line, and wherein the fourth switch element includes a gate electrode to which the third gate signal is applied, a first electrode connected to the third node, and a second electrode connected to the second power line.

6. A pixel circuit comprising: a driving element including a first electrode connected to a first power line, a gate electrode connected to a first node, and a second electrode connected to a second node; a first switch element configured to apply a data voltage to the first node in response to a first gate signal; a second switch element configured to connect a sensing line to the second node in response to a second gate signal; a third switch element configured to connect the sensing line to a third node in response to a third gate signal; a fourth switch element configured to connect a second power line to the third node in response to a fourth gate signal; a capacitor connected between the first node and the second node; and a light-emitting element connected between the second node and the third node.

7. The pixel circuit of clause 6, wherein the first switch element includes a gate electrode to which the first gate signal is applied, a first electrode connected to a data line to which the data voltage is applied, and a second electrode connected to the first node, wherein the second switch element includes a gate electrode to which the second gate signal is applied, a first electrode connected to the second node, and a second electrode connected to the sensing line, wherein the third switch element includes a gate electrode to which the third gate signal is applied, a first electrode connected to the third node, and a second electrode connected to the sensing line, and wherein the fourth switch element includes a gate electrode to which the fourth gate signal is applied, a first electrode connected to the third node, and a second electrode connected to the second power line.

8. A display device comprising: a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits are disposed; a data driver configured to output a data voltage to the plurality of data lines; and a gate driver configured to output a gate signal to the plurality of gate lines. wherein each of the pixel circuits includes: a driving element including a first electrode connected to a first power line, a gate electrode connected to a first node, and a second electrode connected to a second node; a first switch element configured to apply a data voltage to the first node in response to a first gate signal; a second switch element configured to connect a third node to the second node in response to a reset signal; a third switch element configured to connect a sensing line to the third node in response to a second gate signal; a fourth switch element configured to connect a second power line to the third node in response to a third gate signal; a capacitor connected between the first node and the second node; and a light-emitting element connected between the second node and the third node.

9. The display device of clause 8, wherein the data driver comprises a sensing part configured to sense threshold voltages of the driving element and the light-emitting element through the sensing line, wherein the sensing part includes: a first switch connected between the sensing line and a third power line; an ADC configured to convert a voltage sensed from the sensing line into digital data; and a second switch connected between the ADC and the sensing line.

10. The display device of clause 9, wherein the pixel circuit is configured to be driven in the order of an initialization and data writing period, a sensing period, and a sampling period in a first sensing mode for measuring the threshold voltage of the driving element, wherein during the initialization and data writing period, the first switch is turned on, and the second switch is turned off, wherein during the sensing period, the first switch and the second switch are 25 turned off, and wherein during the sampling period, the first switch is turned off, and the second switch is turned on.

11. The display device of clause 10, wherein the data driver is configured to: apply a data voltage of a predetermined voltage level to the pixel circuit selected for sensing in the first sensing mode, and apply a data voltage of 0 V or a black grayscale to the non-selected pixel circuit.

12. The display device of clause 9, wherein the pixel circuit is configured to be driven in the order of an initialization and data writing period, a programming period, a sensing period, and a sampling period in a second sensing mode for measuring the threshold voltage of the light-emitting element, wherein during the initialization and data writing period and the programming period, the first switch is turned on, and the second switch is turned off, wherein during the sensing period, the first switch and the second switch are turned off, and wherein during the sampling period, the first switch is turned off, and the second switch is turned on.

13. The display device of clause 12, wherein the data driver is configured to: apply a data voltage generated by using a maximum gamma voltage to the pixel circuit selected for sensing in the second sensing mode, and apply a data voltage of 0 V or a black grayscale to the non-selected pixel circuit.

14. A display device comprising: a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits are disposed; a data driver configured to output a data voltage to the plurality of data lines; and a gate driver configured to output a gate signal to the plurality of gate lines.

wherein each of the pixel circuits includes: a driving element including a first electrode connected to a first power line, a gate electrode connected to a first node, and a second electrode connected to a second node; a first switch element configured to apply a data voltage to the first node in response to a first gate signal; a second switch element configured to connect a sensing line to the second node in response to a second gate signal; a third switch element configured to connect the sensing line to a third node in response to a third gate signal; a fourth switch element configured to connect a second power line to the third node in response to a fourth gate signal; a capacitor connected between the first node and the second node; and a light-emitting element connected between the second node and the third node.

15. The display device of clause 14, wherein the data driver is configured to: apply a data voltage of a predetermined voltage level to the pixel circuit selected for sensing in a first sensing mode for measuring a threshold voltage of the driving element, and apply a data voltage of 0 V or a black grayscale to the non-selected pixel circuit.

1 0 16. The display device of clause 14, wherein the data driver is configured to: apply a data voltage generated by using a maximum gamma voltage to the pixel circuit selected for sensing in a second sensing mode for measuring a threshold voltage of the light-emitting element, and 1 5 apply a data voltage of 0 V or a black grayscale to the non-selected pixel circuit.

Claims (19)

1. WHAT IS CLAIMED IS: E A pixel circuit comprising: a driving element including a first electrode connected to a first power line, a gate electrode connected to a first node, and a second electrode connected to a second node; a first switch element configured to apply a data voltage to the first node in response to a first gate signal; a second switch element configured to connect a third node to the second node in response to a reset signal or the first gate signal; a third switch element configured to connect a sensing line to the third node in response to a second gate signal; a fourth switch element configured to connect a second power line to the third node in response to a third gate signal; a capacitor connected between the first node and the second node; and a light-emitting element connected between the second node and the third node.
2. 2. The pixel circuit of claim 1, wherein the pixel circuit is configured to be driven in the order of an initialization and data writing period, a sensing period, and a sampling period in a first sensing mode for measuring a threshold voltage of the driving element, and wherein during each period of the first sensing mode, the first to third switch elements are turned on, and the fourth switch element is turned off
3. 3. The pixel circuit of claim 1, wherein the pixel circuit is configured to be driven in the order of an initialization and data writing period, a programming period, a sensing period, and a sampling period in a second sensing mode for measuring a threshold voltage of the light-emitting element, wherein during the initialization and data writing period, the first to third switch elements are turned on, and the fourth switch element is turned off, wherein during the programming period, the first to second switch elements and the fourth switch element are all turned off, and the third switch element is turned on, and wherein during the sampling period, the third switch is maintained to a turn-on state, and the first to second switch elements and the fourth switch element are all turned off.
4. 4. The pixel circuit of claim 3, wherein in the second sensing mode, the data voltage that is applied to the first node is a data voltage corresponding to a maximum gamma voltage.
5. 5. The pixel circuit of any preceding claim, wherein the first switch element comprises a gate electrode arranged to have the first gate signal applied, a first electrode connected to a data line arranged to have the data voltage applied, and a second electrode connected to the first node, wherein the second switch element includes a gate electrode arranged to have the reset signal or the first gate signal applied, a first electrode connected to the second node, and a second electrode connected to the third node, wherein the third switch element includes a gate electrode arranged to have the second gate signal applied, a first electrode connected to the third node, and a second electrode connected to the sensing line, and wherein the fourth switch element includes a gate electrode arranged to have the third gate signal applied, a first electrode connected to the third node, and a second electrode connected to the second power line.
6. 6. A display device comprising: a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits of claim 1 are disposed; a data driver configured to output a data voltage to the plurality of data lines; and a gate driver configured to output a gate signal to the plurality of gate lines.
7. 7. The display device of claim 6, wherein the data driver comprises a sensing part configured to sense threshold voltages of the driving element and the light-emitting element through the sensing line, wherein the sensing part includes: a first switch connected between the sensing line and a third power line; an ADC configured to convert a voltage sensed from the sensing line into digital data; and a second switch connected between the ADC and the sensing line.
8. 8. The display device of claim 7, wherein the pixel circuit is configured to be driven in the order of an initialization and data writing period, a sensing period, and a sampling period in a first sensing mode for measuring the threshold voltage of the driving element, wherein during the initialization and data writing period, the first switch is turned on, and the second switch is turned off, wherein during the sensing period, the first switch and the second switch are turned off, and wherein during the sampling period, the first switch is turned off, and the second switch is turned on.
9. 9. The display device of claim 8, wherein the data driver is configured to: apply a data voltage of a predetermined voltage level to a pixel circuit selected for sensing in the first sensing mode, and apply a data voltage of 0 V or a black grayscale to a non-selected pixel circuit.
10. 10. The display device of claim 7, wherein the pixel circuit is configured to be driven in the order of an initialization and data writing period, a programming period, a sensing period, and a sampling period in a second sensing mode for measuring the threshold voltage of the light-emitting element, wherein during the initialization and data writing period and the programming period, the first switch is turned on, and the second switch is turned off, wherein during the sensing period, the first switch and the second switch are turned off, and wherein during the sampling period, the first switch is turned off, and the second switch is turned on.
11. 11. The display device of claim 10, wherein the data driver is configured to: apply a data voltage generated by using a maximum gamma voltage to a pixel circuit selected for sensing in the second sensing mode, and apply a data voltage of 0 V or a black grayscale to the a-selected pixel circuit.
12. 12. A pixel circuit comprising: a driving element including a first electrode connected to a first power line, a gate electrode connected to a first node, and a second electrode connected to a second node; a first switch element configured to apply a data voltage to the first node in response to a first gate signal; a second switch element configured to connect a sensing line to the second node in response to a second gate signal; a third switch element configured to connect the sensing line to a third node in response to a third gate signal; a fourth switch element configured to connect a second power line to the third node in response to a fourth gate signal; a capacitor connected between the first node and the second node; and a light-emitting element connected between the second node and the third node.
13. 13. The pixel circuit of claim 12, wherein the first switch element includes a gate electrode to which the first gate signal is applied, a first electrode connected to a data line to which the data voltage is applied, and a second electrode connected to the first node, wherein the second switch element includes a gate electrode to which the second gate signal is applied, a first electrode connected to the second node, and a second electrode connected to the sensing line, wherein the third switch element includes a gate electrode to which the third gate signal is applied, a first electrode connected to the third node, and a second electrode connected to the sensing line, and wherein the fourth switch element includes a gate electrode to which the fourth gate signal is applied, a first electrode connected to the third node, and a second electrode connected to the second power line.
14. 14. A display device comprising: a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits of claim 12 are disposed; a data driver configured to output a data voltage to the plurality of data lines; and a gate driver configured to output a gate signal to the plurality of gate lines.
15. 15. The display device of claim 14, wherein the pixel circuit is configured to be driven in the order of an initialization and data writing period, a sensing period, and a sampling period in a first sensing mode for measuring the threshold voltage of the driving element, wherein during the initialization and data writing period, the first switch is turned on, and the second switch is turned off, wherein during the sensing period, the first switch and the second switch are 25 turned off, and wherein during the sampling period, the first switch is turned off, and the second switch is turned on.
16. 16. The display device of claim 15, wherein the data driver is configured to: apply a data voltage of a predetermined voltage level to a pixel circuit selected for sensing in the first sensing mode for measuring a threshold voltage of the driving element, and apply a data voltage of 0 V or a black grayscale to a non-selected pixel circuit.
17. 17. The display device of claim 14, wherein the pixel circuit is configured to be driven in the order of an initialization and data writing period, a programming period, a sensing period, and a sampling period in a second sensing mode for measuring the threshold voltage of the light-emitting element, wherein during the initialization and data writing period and the programming period, the first switch is turned on, and the second switch is turned off, wherein during the sensing period, the first switch and the second switch are turned off, and wherein during the sampling period, the first switch is turned off, and the second switch is turned on.
18. 18. The display device of claim 17, wherein the data driver is configured to: apply a data voltage generated by using a maximum gamma voltage to a pixel circuit selected for sensing in the second sensing mode for measuring a threshold voltage of the light-emitting element, and apply a data voltage of 0 V or a black grayscale to a non-selected pixel circuit.
19. 19. The display device of any of claims 14 to 18, wherein the data driver comprises a sensing part configured to sense threshold voltages of the driving element and the light-emitting element through the sensing line, wherein the sensing part includes: a first switch connected between the sensing line and a third power line; an ADC configured to convert a voltage sensed from the sensing line into digital data; and a second switch connected between the ADC and the sensing line.