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GB2488680B - Requests and data handling in a bus architecture - Google Patents

Requests and data handling in a bus architecture

Info

Publication number
GB2488680B
GB2488680B GB1205830.1A GB201205830A GB2488680B GB 2488680 B GB2488680 B GB 2488680B GB 201205830 A GB201205830 A GB 201205830A GB 2488680 B GB2488680 B GB 2488680B
Authority
GB
United Kingdom
Prior art keywords
requests
data handling
bus architecture
architecture
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB1205830.1A
Other versions
GB201205830D0 (en
GB2488680A (en
Inventor
Jason Meredith
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Imagination Technologies Ltd
Original Assignee
Imagination Technologies Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imagination Technologies Ltd filed Critical Imagination Technologies Ltd
Priority to GB1205830.1A priority Critical patent/GB2488680B/en
Publication of GB201205830D0 publication Critical patent/GB201205830D0/en
Publication of GB2488680A publication Critical patent/GB2488680A/en
Application granted granted Critical
Publication of GB2488680B publication Critical patent/GB2488680B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/37—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1621—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
GB1205830.1A 2010-03-19 2010-03-19 Requests and data handling in a bus architecture Active GB2488680B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB1205830.1A GB2488680B (en) 2010-03-19 2010-03-19 Requests and data handling in a bus architecture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB1205830.1A GB2488680B (en) 2010-03-19 2010-03-19 Requests and data handling in a bus architecture

Publications (3)

Publication Number Publication Date
GB201205830D0 GB201205830D0 (en) 2012-05-16
GB2488680A GB2488680A (en) 2012-09-05
GB2488680B true GB2488680B (en) 2013-03-13

Family

ID=46160154

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1205830.1A Active GB2488680B (en) 2010-03-19 2010-03-19 Requests and data handling in a bus architecture

Country Status (1)

Country Link
GB (1) GB2488680B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118642856B (en) * 2024-06-28 2025-11-28 摩尔线程智能科技(北京)股份有限公司 Data processing method and system, storage medium and electronic equipment

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6073210A (en) * 1998-03-31 2000-06-06 Intel Corporation Synchronization of weakly ordered write combining operations using a fencing mechanism
US6275914B1 (en) * 1999-10-15 2001-08-14 Micron Technology, Inc Apparatus for preserving memory request ordering across multiple memory controllers
EP1191452A2 (en) * 2000-09-20 2002-03-27 Broadcom Corporation Out of order associative queue in two clock domains
US20070214298A1 (en) * 2006-03-10 2007-09-13 Sullivan James E Jr Efficient execution of memory barrier bus commands

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6073210A (en) * 1998-03-31 2000-06-06 Intel Corporation Synchronization of weakly ordered write combining operations using a fencing mechanism
US6275914B1 (en) * 1999-10-15 2001-08-14 Micron Technology, Inc Apparatus for preserving memory request ordering across multiple memory controllers
EP1191452A2 (en) * 2000-09-20 2002-03-27 Broadcom Corporation Out of order associative queue in two clock domains
US20070214298A1 (en) * 2006-03-10 2007-09-13 Sullivan James E Jr Efficient execution of memory barrier bus commands

Also Published As

Publication number Publication date
GB201205830D0 (en) 2012-05-16
GB2488680A (en) 2012-09-05

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)

Free format text: REGISTERED BETWEEN 20240822 AND 20240828