GB2306067A - Modulator circuit and data transfer system - Google Patents

Abstract

A modulator circuit (30) includes a latch (32) for providing a latched data signal at a periodic portion of a carrier frequency (35) and a voltage amplifier (37, 39) which is coupled to receive the carrier frequency (35) and provides an output. A switched impedance network (31), coupled between the carrier frequency (35) and the voltage amplifier (37, 39) provides first and second impedance paths depending upon the latched data signal;. In this way the modulator circuit (30) achieves modulation of the carrier frequency by producing first and second amplitudes of the output signal in dependence upon the selected impedance path. The modulator circuit may be included in a data transmission system for control of electronic locks.

Description

MODULATOR CIRCUIT AND DATA TRANSFER SYSTEM Field of the Invention This invention relates to a data transfer system, and particularly though not exclusively, to a short range contactless data transfer system.

Background of the Invention Short range contactless data transfer systems, such as electronic locks typically include a modulator/controller (or reader) and a transponder key. Energy from the controller may be transferred to the key by magnetic coupling to provide power for the key to transfer data to the controller. Such systems are used in a number of applications, such as anti-theft systems. For example, in a vehicle the key is the vehicle door or ignition key and coded data is transferred between the controller and the key to verify the key and thereby unlock the door or enable the ignition system of the vehicle.

Energy is provided by the controller into a first inductance coil so as to develop an oscillating magnetic field into which a second inductance coil mounted on the key, is passed. When the second coil is placed in the region of the first coil, a current is induced therein and the key receives current to power integrated circuits in the key. Typically the controller modulates the current in the coil in response to data to be transmitted. In this way data transfer between the controller and the key is facilitated. A problem with this arrangement is that portions of the data to be transmitted having a zero value result in a zero modulated carrier, which therefore carries no current. This then necessitates a higher power level for the non-zero portions of the transmission, in order for enough power to be transferred to operate the key.

Furthermore, saturation of the driven signal gives rise to unwanted harmonics, which adversely effect power spectral efficiency. Additional components are typically used to filter these harmonics. However the cost and inconvenience of these components are undesirable.

This invention seeks to provide a data transfer system which mitigates the above mentioned disadvantages.

Summarv of the Invention According to a first aspect of the present invention there is provided modulator circuit comprising: a latch coupled to receive a data signal and a carrier frequency signal, for providing a latched data output signal at each occurrence of a predetermined periodic portion of the carrier frequency signal; a voltage amplifier coupled to receive the carrier frequency signal; and a switched impedance network, coupled between the carrier frequency signal and the voltage amplifier, for providing a selected one of first and second impedance paths therebetween, in dependence upon the latched output signal; wherein the voltage amplifier produces first and second dynamic output amplitude signals in dependence upon the selected impedance path, such that modulation of the carrier frequency signal is achieved.

Preferably the voltage amplifier comprises an unbuffered CMOS inverter and a feedback resistor. The switched impedance network preferably comprises first and second impedances coupled in series and a switch coupled in parallel to the first impedance, wherein when the switch is closed, the first impedance is short circuited.

Preferably the switch is coupled to receive the latched data output signal as a control input. The data signal is preferably a binary signal and the modulation of the carrier frequency signal represents logical high and logical low values.

According to a second aspect of the present invention there is provided a data transfer system comprising: a transmitter portion having a modulator circuit as claimed in any preceding claim, a current amplifier and a first inductance coil; and, a receiver portion having an integrated circuit and a second inductance coil arranged to receive current by inductance from the first inductance coil.

In this way the occurrence of a zero modulated carrier is avoided and unwanted harmonics are substantially reduced without the need for additional external filtering components.

Brief Description of the Drawmg(s) An exemplary embodiment of the invention will now be described with reference to the drawing in which: FIG. 1 shows a circuit diagram of a preferred embodiment of a data transfer system in accordance with the invention.

FIG.2 shows a transform function graph of operating voltage for an amplifier forming part of the system of FIG. 1.

FIG.3 shows a modulation graph of two data states of the system of FIG. 1 FIG.4 shows a modulated carrier waveform of the system of FIG. 1.

FIG.5 shows a graph of voltage signal coupling of a prior art system.

FIG.6 shows a graph of power spectral efficiency of a prior art system.

FIG.7 shows a graph of voltage signal coupling of the system of FIG. 1.

FIG.8 shows a graph of power spectral efficiency of the system of FIG. 1.

Detailed Descngtlon of a Preferred Embodiment Referring to FIG.1, there is shown a data transfer system including a controller circuit 10 and a key circuit 100. The controller circuit 10 comprises a data input 20, a modulator circuit 30, a carrier frequency input 35, a current amplifier 40 and a first inductance coil 50.

The modulator circuit 30 is coupled to receive a data signal from the data terminal 20, and a carrier frequency signal from the carrier frequency terminal 35. The carrier frequency signal is amplitude modulated by the data signal within the modulator, as further described below, to produce a modulated signal.

The data signal may be produced either internally by software within the controller or externally.

The driver circuit is coupled to receive the modulated signal from the modulator circuit 30, for providing an amplified modulated signal to the first inductance coil 50.

The key circuit 100 includes a second inductance coil 110 and an integrated circuit 120. The second inductance coil is arranged such that when in proximity to the first inductance oil of the controller circuit 10, a current is induced therein, in dependence upon the modulated current flowing in the first inductance coil 50. The integrated circuit 120 is coupled to the second inductance coil 110, for receiving the induced current. The induced current provides operating voltage for the integrated circuit 120, and the modulation thereof is demodulated to reproduce the data signal.

The modulator circuit 30 comprises a latch 32, a switched impedance network 31 and an amplifier formed with an unbuffered CMOS (Combined Metal Oxide Semiconductor) inverter 39 and a feedback resistor 37, and operates as a voltage amplifier. The latch 32 has a data input coupled to the data terminal 20, a clock input coupled to the carrier frequency terminal 35 and an output which provides a control signal for the switched impedance network 31.

The switched impedance network 31 comprises a switch 33 arranged to selectively couple the carrier frequency terminal 35 to a first terminal of a second resistor 38, in dependence upon the received output from the modulator 30. A first resistor 36 provides a further path between the carrier frequency terminal 35 and the first terminal of the second resistor 38. The CMOS inverter 39 has the feedback resistor 37 coupled between an input and an output of the CMOS inverter 39. The input of the CMOS inverter 39 is also coupled to a second terminal of the second resistor 38, and to the current amplifier 40.

The CMOS inverter 39 and the current amplifier 40 both have S transfer function characteristics. Appropriate ohmic values are chosen for the first and second resistors 38 and 36 respectively, to produce a satisfactory overall transfer functicn of the modulator circuit 30.

In operation, and referring now also to FIG.2, the S transfer function of the CMOS inverter 39 is shown. The operating point 150 of the CMOS inverter 39 is located on the middle of the transform function. The operating range is modified according to the input voltage amplitude applied, in the range 160 to 160'.

Modulation of the carrier frequency signal is achieved via the switch 33. When the data latched in the latch 32 is low, the switch 33 is open, causing the carrier frequency signal to flow only through the second resistor 36 and the first resistor 38 to the input of the CMOS inverter 39. When the data latched in the latch 32 is high, the switch 33 is closed, causing the carrier frequency signal to flow through the switch 33. Since this is of negligible resistance substantially all of the current flows through the switch 33, avoiding the second resistor 36 and only being impeded by the first resistor 38 before reaching the input of the CMOS inverter 39. In this way the switch 33 and latch 32 arrangement provides first and second resistance paths through which the carrier frequency signal passes. Switching between the paths causes the required modulation.

The first resistor 38 has the effect of shifting the operating range of the class A amplifier from a full range between saturation points 160-160' to between points 170-170". When the switch 33 is closed, the influence of the second resistor 36 in addition to the first resistor 38 further limits the operating range to between points 180 and 180'. In this way two non-zero amplitudes of the carrier frequency define logical states 1 and 0, corresponding to data high and data low values of the data signal. This is shown in FIG.3 which shows the logical 0 state carrier voltage range 200 and the logical 1 state carrier voltage range 210.

Similarly FIG.4 shows the logical 1 carrier profile 220 and the logical 0 carrier profile 230.

It is known that when driving a tuned serial circuit with a square wave, harmonics of the carrier frequency occur. FIG.5 shows the voltage signal across a coil of a prior art modulator circuit, including the disturbances 200 due to saturation of the driver output. FIG.6 shows the power spectrum associated with the voltage signal of FIG.5, including unwanted high frequency harmonics 250.

In contrast, the modulator circuit 30 does not operate up to saturation points 160 and 160', as the dynamic range of the transfer function is reduced to points 170-170' by virtue of the first resistor 38. This reduces the number and power of unwanted harmonics. FIG.7 shows the voltage signal across the inductance coils when driven by the modulator circuit 30. FIG.8 shows the power spectrum associated with this voltage signal. The high frequency harmonics are limited to less than 3Mhz, and are less than 20dBm for all frequencies higher than 2Mhz.

This results in a higher power spectral efficiency of the induced current in the inductance coil, which in turn allows a lower overall power level to be used, and significantly reduces internally generated noise.

It will be appreciated that alternative embodiments to the one described above are possible. For example, the resistors described above could be replaced by alternative impedances, such as those provided by capacitors and inductors.

Furthermore, the CMOS inverter 29 and current amplifier 40 described above could both be replaced by alternative equivalent devices, having the same transform functions.

Claims (8)

Claims

1. A modulator circuit comprising: a latch coupled to receive a data signal and a carrier frequency signal, for providing a latched data output signal at each occurrence of a predetermined periodic portion of the carrier frequency signal; a voltage amplifier coupled to receive the carrier frequency signal; and a switched impedance network, coupled between the carrier frequency signal and the voltage amplifier, for providing a selected one of first and second impedance paths therebetween, in dependence upon the latched output signal; wherein the voltage amplifier produces first and second dynamic output amplitude signals in dependence upon the selected impedance path, such that modulation of the carrier frequency signal is achieved.

2. The modulator circuit of claim 1 wherein the voltage amplifier comprises an unbuffered CMOS inverter and a feedback resistor.

3. The modulator circuit of claim 1 or claim 2 wherein the switched impedance network comprises first and second impedances coupled in series and a switch coupled in parallel to the first impedance, wherein when the switch is closed, the first impedance is short circuited.

4. The modulator of claim 3 wherein the switch is coupled to receive the latched data output signal as a control input.

5. The modulator of any preceding claim wherein the data signal is a binary signal and the modulation of the carrier frequency signal represents logical high and logical low values.

6. A data transfer system comprising: a transmitter portion having a modulator circuit as claimed in any preceding claim, a current amplifier and a first inductance coil; and a receiver portion having an integrated circuit and a second inductance coil arranged to receive current by inductance from the first inductance coil.

7. A modulator circuit substantially as hereinbefore described and with reference to the drawings.

8. A data transfer system substantially as hereinbefore described and with reference to the drawings.