GB2385688A

GB2385688A - Minimising power loss in addressing memory

Info

Publication number: GB2385688A
Application number: GB0204509A
Authority: GB
Inventors: Nicholas Craig Bowdler
Original assignee: NEC Technologies UK Ltd
Current assignee: NEC Technologies UK Ltd
Priority date: 2002-02-26
Filing date: 2002-02-26
Publication date: 2003-08-27
Also published as: GB0204509D0

Abstract

In order to minimise the number of address line state changes and hence power loss due to charge/discharge of the address line(s), address differences are passed from a CPU 2 to a memory 4. The difference between a current address and a previous address latched at 6 is formed by a subtractor 10 and sent in parallel or serial form on address bus 12. Adder 14 receives the difference, adds it to a previous address from latch 16 to form a new absolute address for the memory, and latches 6 and 16 are updated.

Description

MEMORY ADDRESSING This invention relates to a method and apparatus for addressing solid state'memory devices.

Known solid state memory devices are addressed by multi-bit digital words. These can be supplied to a memory device either in parallel on a plurality of address lines or as a serial address by time division multiplexing on a single address line. Addressing in these known devices uses what is known as absolute addressing. This means that each time a location is addressed the full address is sent on the address line or lines. In the case of parallel address lines there will be changes in the states of a plurality of the address lines with each new address. In the case of serial address line there will be a plurality of changes of state sent along the address line as the new address is sent along it.

These changes in state on address lines result in dissipation of power. It is desirable to minimise power loss in electronic devices, particularly in portable devices where batteries are relied upon to provide electrical power.

Specific embodiments of the present invention seek to overcome this problem with power dissipation when addresses are changed by transmitting only a differential address change. In the case of parallel addressing, this leads to address lines being kept at constant value when addresses are incrementing at a constant rate. In the case of serial addressing, it results in fewer state changes having to be sent along the serial address line for each incremental address.

The invention is defined with more precision in the appended claims to which reference should now be made.

Embodiments of the invention will now be described in detail by way of example with reference to the accompanying drawing in which:

Figure 1 shows a block diagram of an embodiment of a memory interface in accordance with the invention.

In the figure there is shown a central processing unit (CPU) 2 which is used to address a memory 4. A plurality of address bits 0-N are output by the CPU 2 and are latched in a latch 6 in response to a clock pulse provided on clock line 8. This clock pulse simultaneously clocks a subtractor 10 to subtract a previous value stored in latch 6 from the current value provided on the address lines 0-N and to output the result of the subtraction on address lines 12. The subtracter 10 and latch 6 are provided physically in close proximity to the CPU 2 and are preferably provided in an integrated package 12.

Initially, the latch 6 will have a zero value stored in it and thus the effect of subtraction in subtracter 10 where the memory is first addressed will be to leave the values of the address line as 0-N unchanged. However, on subsequent address changes, either incremental or address jumps, there will be a value stored in the latch. Thus, this value will be subtracted from the new address value in the subtracter 10 and the output on lines 12 will then be the differential between the last address and the new address. For sequential addressing with an increment of 1 this means that only a single bit needs to be provided on output lines 12 and this will be the least significant bit provided on a single address line. Thus, only one address line has a state transmitted on it, and as long as the increment remains the same, there is no alternative current power dissipated by charging and discharging of address lines, i. e. the status of all lines remain the same.

Some larger addressing increments will lead to charging and discharging of address lines but this will usually result in fewer charges and discharges than with conventional addressing, thereby reducing the power dissipated.

When the address jumps the number of address line changes which are required will usually be fewer than in conventional addressing but may on sometimes be larger.

However, most addressing is incremental and this incremental addressing is what usually leads to the dissipation of power in address lines. Jumps in addresses occur much less frequently and therefore power dissipated in them is not such a problem.

The memory being addressed is memory 4. Address lines 12 are input to adder 14. This also receives a previous address from a further latch 16. Thus, the incremental address is added to the previous address in the adder 14 the obsolete address is output on address lines 18 which form the address input to the memory. The output of the adder also forms an input to the latch 16 which latches this value in its registers as the adder is clocked, for use in a following address.

A reset line 20 is provided as an input to latch 6 and latch 16 and this is able to reset the value stored in these to 0 when a new addressing program is desired to commence. This reset will therefore cause absolute addressing to the memory unit 4 until reset is released and a differential addressing recommences.

The invention could also be used with serial address lines with address bits suitably synchronised by the clock 8. This would again lead to lower power dissipation as there would be fewer changes in state on the address lines 12, i. e. most bits will be zero.

The memory 4, adder 14 and latch 16 are preferably provided in close proximity. In a preferred embodiment they are provided in a single package.

Claims

CLAIMS 1. A method for addressing a memory device comprising the steps of storing a current memory address receiving an increment for the current memory address and incrementing the current memory address with the recorded increment.
2. A method according to claim 1 in which the step of incrementing the current memory address comprises adding the increment to the current memory address.
3. A method according to claim 1 and 2 including the step of storing the incremented address.
4. A method according to claim 3 in which the incremented address replaces the current memory address.
5. A method according to claim 1,2, 3 or 4 in which the current memory address is stored at the memory device and at an address generator.
6. A method according to claim 5 in which the steps of generating a new memory address at the address generator, comprises subtracting the current memory address from the new memory address to generate the increment.
7. Apparatus for addressing a memory device comprising means for storing a current memory address, means for receiving an increment to the current memory address, and means for incrementing the current memory address with the received increment.
8. Apparatus according to claim 7 in which means for incrementing comprises an address for adding the increment to the current memory address.

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9. Apparatus according to claim 8 in which the storing means stores the incremented address.
10. Apparatus according to claim 9 in which the storing means replaces the current memory address with the incremented address.
11. Apparatus according to claim 7,8, 9, or 10 including an address generator which includes a further storing means for the current memory address.
12. Apparatus according to claim 7 in which the address generator generates a new memory address and includes a subtractor to subtract the stored current memory address from the new memory address to generate the increment.
13. A method for addressing a memory device substantially as herein described.
14. Apparatus for addressing a memory device substantially as herein described with reference to the figure.