GB2263002A - Parallel binary adder. - Google Patents

Abstract

An N-bit binary adder with a highly parallel structure comprises a multiplicity of parallel modulo-2 adders for forming the sum of corresponding operand and carry bits. The carry inputs are generated by a conditional carry propagation generator and an unconditional carry generator from which carry bits are generated in log22N operational levels. <IMAGE>

Description

A PARALLEL BINARY ADDER FIELD OF INVENTION The invention pertains to the field of arithmetic adder circuits and more specifically to binary adder networks.

BACKGROUND TO THE INVENTION Binary adder networks are basic to digital computer arithmetic operation. Because of the large number of adder operations involved, the history of computer development shows a constant search for faster adder networks either through faster component technology or by improved network organization using various auxiliary logic or computing networks to augment the basic adder unit.

Early digital computers used ripple-carry adders in which the ilh adder output bit may be represented by the modulo-2 bit sum S=Aid3 Bq3 Ci where Aj and Bj are the jlh bit of the input operands, and Ci-1 is the carry-in from the next lowest bit sum. The carry-in may be represented in terms of the prior stage operands (Ai-1, Bi-1) and the prior stage carry-in, Cl-2, as Ci-1= A1.1 B.1 + Cj 2 (A1.1 + Bi.1) where (',+) are Boolean (AND, OR) operators respectively. The time for the carry-bits to ripple through became the limiting factor in the speed of adders.Subsequent fixed-time adders were introduced to overcome these deficiencies. These fixed-time adders may be classified into two categories: conditional sum and carry-look-ahead (CLA) adders.

Conditional adders compute each bit sum, Si, twice: one sum, SN.

based on the assumption that the carry-in bit, Cl, is zero; a second sum, 5E1, on the assumption that Cl = 1. Figure 1 is the logic diagram of a 4-bit-slice conditional sum adder. (Ref. "Introduction to Arithmetic", Waser and Flynn, Holt, Rinehart and Winston, 1982, p. 77ff). The two input operands are represented by input bits Ao, Aj, A2, A3 and Bo, B11 B2, Bs, respectively.

Each pair of operand bits (Al, Bi) are applied to input terminals 110. Ao, Bo correspond to the input operand least significant bit while Ag, B3 correspond to the most significant bits. The conditional sum adder consists of two basic sections: the conditional sum generator unit 130 that forms at its output the two sets of conditional sums hand conditional carry, SNO, SN1. SN2.SN3. CN4 and SE0 SE1, SE2, SE3, CE4, the latter group being based on the assumption of a non-zero carry-in to its corresponding individual conditional sum generator 141, 143, 145, 147, 149, respectively.These conditional signals are applied to conditional sum selector unit 150 consisting of the individual output selectors 161, 163, 165, 167, 169 corresponding to output sum bits So, S1, S2, S3 and output carry bit C4. The selection is controlled by the carry-in bit, Co, and its complement, Co, operating on the conditional sums by means of AND-gates 113 and OR-gates 115.

The logic equations governing the behavior of the conditional 4-bit slice adder of Figure 1 are as follows: SN0=A0#B0 SE0=SN0 SN1=A1 # B1 # G0 S@@@@@@@@@@@@@@ El = 1 0 SN2=A2 # B2 # (G1+T1G0) SE2=A2 # B2 # (G1+T1P0) SN3=A3 # B3 # (G2+T2G1+T2T1G0) SE3=A3 # B3 # (G2+T2G1+T2T1P0) CN4=G3+T3G2+T3T2G1+T3T2T1G0 C@@=G3+T3G2+T3T2G1+T3T2T1P0 3 3 2 3 2 1 3'2'1' 0 where G1=A1B1 P1=A1B1, T1=A1#B1, The true 4-bit sum and carry-out is selected by selector unit 150 in accordance in accordance with the following boolean equations:: So = SEoCO + SN0 C0 S1=SE1C0+SN1 C0 S2=SE2C0+SN2 C0 S3=SE3C0+SN3 C0 C4 = CE4Co + CN4 The above concept could be extended to additional bits with the attendant increase in complexity implied by the above equations and by Figure 1.

Carry-looks ahead (CLA) adders have been the most popular integrated circuit implementation in the recent past because of their simplicity and modularity. Modularity implies relative ease in extending the number of bits in each operand by the use of identical parallel units.

Consider, for example, the 4-bit slice CLA of Figure 2. Comparison with Figure 1, a 4-bit slice conditional adder, clearly shows the relative simplicity of the CLA.

The CLA sum may be expressed in the following logic expression as Si = Ai#Bi#Ci , , 1=0,1,2,3 and the CLA carry as Cl + A1B1 + C1 (A1 + 81) or C1=Gj+PjO1 where Gi=AiBi and Pi=Ai+Bi The above CLA sum expression can be immediately evaluated, absent the carry term (Ci-1), by forming the EOR of the two operands (Ai, Bj).

The carry term, Ci-1, is a function of lower order indexed operands, (Ai.i, bi-1), and lower order carries, Ci-2. As a result, the time to complete an addition is generally governed by availability of the carry-in bit to each sumbit.

The above expression for Ci is a recursive equation, i.e., one in which the current value, Ci+1, is a function of its own past values. It may be explicitly stated as follows: Ci+1=Gi+PiGi-1+PiPi-1Gi-2+...+PiPi-1...P0C0 Hence, for the four-bit case of Figure 2, the major output carry, C4, may be expressed as C4 = G3 + P3G2 + P3P2G1 + P3P2P1Go + P3P2P1PoCo By substituting the following into the above expression Go' = G3 + P3G2 + P3P2G1 + P3P2P1G0 and Po' = P3P2P1PoCo obtains C4 = Go' + P0'C0 which represents the logical expression for the G0', P0' output terminals of Figure 2.

If two networks of the type shown in Figure 2 were to be used as a modular units for generating an 8-bit sum, the carry-in bit to the higher order 4-bit network, C4, would have to be formed in accordance with the above expression. The output carry of the higher order unit, C8, would then be expressible as C8=G1'+P1'G0' +P1'P0'C0' where G; and P1 are the CLA output pair of the next higher order CLA modular unit.

Modularity was extended by means of a four group CLA generator that accommodated four CLA 4-bit slice adders and produced at output the necessary carry information, i.e., C4, C8, C12 and P", G", to form a 16-bit CLA adder using four modular adder units of the type shown in Figure 2. Figure 3 shows a four group CLA generator with four input pairs, (G0',P0'),(G1',P1'),(G2',P2')and(G3',P3') and carry outputs corresponding to C4, C8, C12 and (P",G"), where G12=G2'+P2'G1'+P2'P1'G0'+P2'P1'P0'C0 and G" = G3'+P3'G2'+P3'P2'P1'C0 B" = B'B'B'B' P,,=P' P'P'P 3210 Thus, the most significant carry-out bit, C16, could be logically formed as C16=G"*P"C0 and passed on, as needed, to higher order modular CLA adder units.

Figure 4 shows the logical extension of modular CLA concept to 64-bit addition. A total of sixteen modular 4-bit slice SLA adders 200 are arrayed in parallel to accept input operand pairs, (Ao, B0)... (A3, B3), (A41 B4) (A7,B7),...,(A60,B60)...(A63,B63) and carry-in bits, (C0,C16.C32,C48), each producing 4-bit output sums, (So, Si, S21 S3) ... (S60, S61, S62, S63) and carry-generate/carry-propagate pairs (P0',G0'),...(P15',G15') A second logical level of four modular four group CLA generators 250, each accepting the carry putput information of a corresponding group of four CLA adders 200, generates the necessary carry information for its associated adders 200 from the four pairs of carry-generate/carry-propagate pairs and the necessary carry-generate/carry-propagate pairs, [(P0",G0"),(P1",G1"), and (P2",G2")], from which the third logic level consisting of a single CLA generator 250 generates the three additional carry-in bits, (C16, C32, C48) supplied to the first and second levels. In this manner, modular 4-bit slice CLA adders have been used to accommodate higher precision operation.

Also, the basic conditional adder unit of Figure 1 may be used as a modular adder and extended to higher precision addition by using the CLA generator concept because the logic equations defining the higher order carries are similar. For example, it may be shown (op cit Waser and Flynn) that the second level conditional same carries may be expressed as C4 = CN4 + CE4 CO C8 = CN8 + CE8 CN4 + CE8 CE4 CO C12 = CN12 + CE12 CN8 + CE12 CE8 CN8 + CE12 CE8 CE4 CO Because the logic required to implement the above expressions is identical to that of the CLA generator 250 of Figure 3 and 4, a 16-bit adder may be implemented as shown in Figure 5. The adder has four conditional adders 100 connected in parallel, each accepting 4-bit pairs of operands. Each adder 100 consists of a conditional sum generator 130 and a multiplexor 150. The modular group carry-out pairs, I(CN4, CE4), (CN8, CE8), (CN12.

CE12)], are supplied to CLA generator 250 which produces the modular carry-in bits (C4, C8, C12) required to form the sixteen bit addition. The extension required to accommodate more bits clearly indicated by the CLA method previously discussed.

Because of the need for cost effective parallel fast adders, it is highly desirable that the number of processing steps required to generate the carry-bits (and hence the sum) be proportional to the logarithm of the number of bits in each operand, and at a relatively low-cost. Also, a logic structure that allows constant fan-in and fan-out and permits static versus fixed rate pre-chargeldischarge operation is desIrable. The present invention is designed to achieve these goals.

SUMMARY OF THE INVENTION A parallel N-bit binary adder network is described comprising a multiplicity of parallel modulo-2 adders, each accepting and summing corresponding operand bit pairs and a final sum carry input. The final sum carry bits are generated in parallel by a carry generating network that comprises a parallel carry propagation logic array for generating conditional carry propagation terms based on the logical OR-ing of pairs of input operand bits, an unconditional carry generation logic network based on AND-ing of pairs of input operand bits, and a logic array for operating on conditional and unconditional carry terms, in parallel for producing a set of final sum carry terms that are fed in parallel to the modulo-2 parallel adders.

The number of gate delays for generating the final set of N sum carry inputs to the modulo-2 adder is [log22N], providing a substantial increase in adder throughput.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a logic diagram of a prior art 4-bit slice conditional sum adder.

Figure 2 is a logic diagram of a prior art 4-bit slice carry-look-ahead (CLA) adder.

Figure 3 is a logic diagram of a prior art four group CLA generator.

Figure 4 is a block diagram of a prior art 64-bit adder using full CLA.

Figure 5 is a block diagram of a prior art 16-bit conditional sum adder using a four group CLA generator.

Figure 6 is a flow diagram of a four-bit carry process.

Figure 7 is a flow diagram of an eight-bit carry process.

Figure 8 is a flow diagram of a sixteen-bit carry process.

Figure 9 is a logic diagram for a typical carry generator node implementation.

Figure 10 is a block diagram of an 8-bit carry generator.

Figure 11 is a logic diagram for an 8-bit propagation generator.

Figure 12 is a logic diagram for a one-bit adder with carry input.

Figure 13 shows a block diagram of a complete parallel adder.

Figure 14 shows the structure of an m-bit two-level carry generator module.

Figure 15 shows the interconnections for a 16-bit carry-generator using 4-bit two-level modules.

Figure 16 shows the partitioning of a 16-bit first and second level carry-generate matrix for use with 4-bit two-level modules.

Figure 17 shows the partitioning of a 16-bit third and fourth level carry-generate matrix for use with 4-bit two-level modules.

Figure 18 shows the interconnections for a 64-bit carry-generator using 8-bit two-level modules.

DETAILED DESCRIPTION OF THE INVENTION The sum, S, of two N-bit binary number operands (A,B) where A=AN-1,AN-2,...,A0 B=BN-1,BN-2,...,B0 may be expressed as S=S1,SN-2,...,S0 where Si=Ai#Bi#Ci-1 represents the value of the ilh sum bit expressed as the modulo-2 sum of the itti operand bit values (Ai, Bi) and the carry-in bit Ci-1, from the modulo-2 sum of the next least significant bit pair (Ai-1, Bi-1).Thus, by using the boolean logic operators (g) for "AND" and (+) for "OR", the carry bits may be expressed as C0=A0*B0 C1=A1*B1+(A1+B1)*C0 C2=A2*B2+(A2+B2)*C1 C1=A1' B+(A+B1)' C1.1 CN-1 = AN-I BN-1 + (AN-1 + BN-1) 'CN.2 For convenience, let Gi=Ai*Bi Pi-=Ai+Bi so the above carry bit expression becom C0= G0 C1=G1+P1C0 C2=G2+P2C1 C =G C@=G@+P@C@ (Note that for further convenience, the explicit "AND" operator symbol has been omitted so that Pi Ci#Pi* Ci) This convention will be used throughout the following description.

The above recursive expressions may be expanded as follows: C0=G0 C1=G1+P1G0 C2 = G2 + P2 G1 + P2 P1 Go C3 = G3 + P3 G2 + P3 P2 Gi + P3 P2 P1 Go C4=G4+P4G3+P4P3G2+P4P3P2G1+P4P3P2P1G0 Ci=Gi+PiGi-1+PiPi-1Gi-2+PiPi-1Pi-2G-3 + ... +PiPi-1Pi-2 ... P1G0 # This set of equations may, in tun, be expressed in matrix form as

or simply #=P(N)# where # is the carry column vector, g is the carry generator column vector, and p(N) Is the lower triangular NXN carry propagation matrix.

Thus, Q = [ Go G1 G2 ... GN-1]T = [ AOBO A1B1 A2B2... AN.lBN.11T represents the "AND"-ing of operand bit pairs which generate a carry-out when high. Matrix P, whose elements represent propagation control variables, describes the means by which the carry-outs are propagated to and through higher order bits.

Significantly, the P-matrix may be factorized into the product of sparse lower triangular matrices. For example, where and

Thus, at each binary increment, 2k < r < 2k+ 1, p(r) is factorizable into (k+1) lower triangle matrices of the form shown. These factorized equations may be represented by the flow diagrams of Figure 6, 7 and 8.

Figure 6 corresponds to the four-bit carry propagation process represented by the factorization of P(4). The input to the process consists of the carry-generator vector, [Go G1 G2 G3 ] T shown at the bottom. The diagonal lines with arrow-heads correspond to multiple ("AND") operations on the data of the node of origin by the corresponding labelled expression.

Unlabeled vertical lines between nodes represent transmission paths with no modification of data transmitted from a lower node to a higher node. All nodes are summing ("OR") junctions. For example, C1 n G1 + PiGo and C3 = P3P2 (G1 + P1Go) + (G3 + P3G2) = P3P2P1Go + P3P2G1 + P3G2 + G3.

The carry-out vector, [ C0 C1 C2 C3 ] T, is represented by the values present at the upper output nodes.

Figure 7 and 8 show flow diagrams for p(8) and p(16), respectively representing 8 and 16 bit carry generation processes. Clearly, flow diagrams for greater number of bits may be generated in a similar fashion by extending the principles expounded.

For each binary increment, 2k# r 5 2 r or for each doubling of the number of bits used in the operands, one additional sparse lower triangular matrix is required to represent the factorized form of the P(r) matrix.

Thus, for 2 Sr s3, p(r) factors into 2 matrices; for 4 Sr 57, p(r) factors into 3 matrices, and for 2k Sr S2k+1.l, p(r) factors into (k+1 ) matrices.

Each factorized matrix operation corresponds to a row of nodes shown in Figures 6, 7, and 8. The lowest (zero) level nodes correspond to the input carry generate vector values, 9. The values at the next level of nodes corresponds to the column vector that would obtain if the extreme right hand factorized matrix of the examples given above were to operate on the input generate vector, g. Similarly, the second level of nodes has values corresponding to that which would obtain if the second most extreme right had factorized matrices operated on the vector resulting from product to its right. And so on for succeeding levels.

In general, k + 1 factorized matrices (stages) are required for 2k+1 bits in each operand, i.e., [ lognN ] stages for N-bit operands.

The flow diagrams of Figures 6, 7 and 8 also imply the logic network structures shown in Figures 9 through 11.

Figure 9 represents a typical nodal processor 10 located at, say, node I, k of Figure 8 producing Gllk at its output. Processor 10 accepts as input PP P # k k-1 k 21-1 at its input terminals 11, 12 and 13 respectively. "AND"-gate 16 and "OR"-gate operate on these inputs to produce at output 14 the boolean function G =GIi1k+PkPkl...P -1G 1-1 k-2 I-1, k-2 Figure 10 is an embodiment of an 8-bit carry generator having four rows (0-3) and 8 columns (0-7?. Rows 1 through 3 comprises 7, 6 and 4 nodal processors 10, respectively, each of the type depicted in Figure 9.

Row 0 comprises 8 AND-gates 20 arranged to accept at input terminals 301 corresponding operand bit pairs, (Ak, B, forming Golk = Ak * Bk and supplied to processors 10 on line 11. The processors 10 of row 1 also accept the seven propagation variable P, through P7 on input lines 305. Propagation variable Pk being applied as an input to processor 10 located at row 1, column k on line 13 together with Go, k-i supplied by lines 12. The output of processor 10 located at 1 ,k is G1.k=Go.k+PkGo,k.1 In a similar manner, processors 10 of row 2 are supplied the outputs of row 1 together with propagation variable P21 through P76 from input line 307.The output of processor 10 located at 2, k is G2,k=G1,k + Pk.k-1 G1,k.2 Processor 10 at location 3, k in a similar manner generates an output G3.k = G2, k + PkPk-1Pk-2Pk-3 G2,k-4 from inputs provided by lower level processors and propagation variable P4P3P2P1 through P7P6P5P4 supplied on input lines 309.

Carry output C0 is available directly from AND-gate 20 at location 0,0 on line 303; C1 from output line 14 of processor 10 at location 1,1; C2 and C3 from processors 10 at location 2,2, and 2,3 respectively; and C4 through C7 from row 3 processor 10 outputs.

It is clear, by reference to the flow diagrams of Figures 6, 7 and 8 and carry generators 300 of Figure 10, that the architecture and organization of the 8-bit carry generator 300 may be expanded indefinitely adding an additional row each time the number of bits in each operand is doubled.

The number of parallel processors required in each row is summarized in Table I.

Operand Bits

4 8 16 32 64 0 4 8 16 32 64 1 3 7 15 31 63 Row 2 2 6 14 30 62 3 4 12 28 60 4 8 24 56 5 16 48 6 32 Table I Figure 11 is a logic circuit for implementing an 8-bit propagation generator suitable for supplying propagation variables to the 8-bit carry generator of Figure 10. Propagation generator 400 comprises 7 OR-gates 40 in row 0 used to form propagation variables P1, P2 ..., P7 from input operand bit pairs (Ak, Bk) as follows: Pk=Ak+ Bk The set, {Pk}, is available on output lines 307. Subsequent rows are comprised of AND-gates 50. The klh AND-gate of row 1 accepts the kit' and k-1 th output of row 0 to form at its output 307 Pk Pk 1. Similarly, the kth processor of row 2 accepts the kth and k-21h output of row 1 to form the set of propagation variables, (Pk Pk 1 Pk 2 Pk 3}, provided at output 309.

Clearly, the organization and architecture of processor 400 may be extended to accommodate more operand bits by extending the structure of Figure 11 to the left and adding an additional row of AND-gates 50 each time the number of input operand bits are doubled. The number of gates required per row are indicated in Table ll.

Operand Bits

4 8 16 32 64 0 3 7 15 31 63 1 2 6 14 30 62 Row 2 4 12 28 60 3 8 24 56 4 16 48 5 32 Table II Figure 12 represents a logic network 60 for forming the complete bit sum of two operand bits (Ak, Bk) and a carry-in bit Ck comprising exclusiveor (EOR) networks 61 and 62.EOR network 61 forms the modulo-2 sum Ak#Bk and network 62 produces at its output Sk = Ak # Bk # Ck-1 Based on the preceding descriptions summer network 60, carry generator 300 and propagation generator 400, a complete parallel binary adder may be defined as shown in Figure 13, organized to accept two N-bit operands A = A0 A1 A2... AN-1 B=B0B1B2...BN-1 Operands A and B are applied to the inputs of propagation generator 400, carry generator 300 and sum unit 500. Propagation generator 400 and carry generator 300 are configured in accordance with the prior description. Sum unit 500 comprises N one-bit plus carry-in bit EOR networks 60, each as described in Figure 12. The carry-in to each EOR network 60 is provided by the appropriate output terminal of carry generator 300.Propagation variables are provided to carry generator 300 by propagation generator 400 as determined by the two input operands A and B. The output of sum unit 500 is S = So S1 ... St4-1 where Sk=Ak#Bk#Ck-1 Note that carry CN-1 is available at the output as an overflow bit of for use in extending the number of bits in the operands A and B.

The preferred implementation of carry generation 300 uses modular medium scale integrated circuit technology. For example, by properly sub-sectioning the flow graph of Figure 8 into seven subsections as shown by the dotted outlines, a 4-bit wide and 2-level deep module may be defined that forms the basis for a modular building-biock approach to the circuit implementation. The 4-bit wide partitioning is somewhat arbitrary and is mainly chosen for purposes of explanation because it probably represents the lowest level of modularization that allows the principle of modularity to be described.

Figure 14 is a block diagram of an m-bit wide, 2-level module 500 comprising two layers of m nodal processors 10 of the type shown in Figure 9. Five sets of m-input lines are accommodated: inputs 501 accept the corresponding Level outputs, (Gi,id; inputs 503 accept the Level outputs displaced by 21-1, (Gl,k-pll; inputs 505 and 507 accept the conditional carry-terms

and

respectively; and inputs 509 accept the (1+1 )to inner layer output terms (displaced by 21), (Gl+1,k.21).

Two sets of output lines are provided: outputs 511 correspond to the first layer output terms, (Gl+l,k); and outputs 513 are the second layer (or module) outputs, (GI+2,k).

Figure 15 is an interconnection diagram for a carry generator 300 using 4-bit wide (m=4) 2-layer modules 500. Each logic unit 520 represents a set of four unit 20 AND-gates used to form (Gk).

Figure 15 may be best understood by referring to Figure 16 that shows the matrix equation relating the zero level (I=0) inputs, (GO,k), to the second level (1=2) outputs, (G2,k), and to Figure 17 showing the matrix equation relating the second level outputs to the fourth level outputs, (G4,k) In Figure 16, the two 1 6x1 6 matrices

are each partitioned into 16 4x4 submatrices. Each non-zero valued submatrix corresponds to a single layer 4-bit wide operation performed within a 500 module. The submatrices of the right-hand Matrix correspond to first layer operations while those in the left-hand matrix correspond to the second layer operations previously described.Similarly, the right hand set of submatrices in Figure 17 corresponds to third level (1=3) operations and the left set corresponds to fourth level (1=4) operations. These equations provide interconnect information by relating the individual module 500 inputs to their outputs.

For example, consider the input/output relationship of module 500 in the first row of Figure 15 identified by coordinates (1,3).

G2.8-11=P2.32*P1.21G0.0-3+P2.32*P1.22*G0.4-7+P2.33P1.32G0.4-7+P2.33G0.8-11 Because P2,32'P1,21=0 G2.8-11=P2.32*P1.22G0.4-7+P2.33P1.32G0.4-7+P2.33G0.8-11

Because

This latter equation expresses the required inputs to module 500 (1,3): the first expression on the right implies only two non-zero products #.G 1,6 and #.G1.7 thus requiring # . # .G1.6 and G1.7 as inputs; the second expression requires # , #,; and the third requires the inpu1 quadruptet [G0.8 G0.9 G0.10 G0.11]T, and the triplet # , # , #, Summarizing, the required inputs are: g0.8-11, g1,6-7, Go,7, and # , as shown in Figure 15, (Please note that for Figure 15, the output carries, {Ck}, are equalto {G4k}.) A similar analysis for module 500 (2,4) results in the following expression:

The interconnections shown in Figure 15 for module 500 (2,4) result.

Figure 18 shows a simplified interconnection diagram for a 64-bit carry generator using 3-layersiof 8-bit wide two layer modules. Specific details of the interconnections may be obtained by partitioning the carry-generator 300 matrices in the same manner as shown for the 4-bit wide two layer example. For the 64-bit case, however, three sets of equations, corresponding to the three layers of Figure 18, must be used.

Another preferred embodiment using a slightly different concept of modularity is shown in Figure 19. For purposes of explanation, a 24-bit adder network is shown comprising: three 8-bit conditional adder networks 141 each accepting two eight bit operands [ (Ao-7, Bio 7), (A8 1s, 88.15), (A16 23, 816-23) ] . and each outputting two conditional 8-bit sums (SE,SN) as previously described in Figure 1; multiplexer units 160 for selecting the SE or SN output of each conditional adder unit which is controlled by a two state carry signal; carry and propagation generator units 600 each comprising a carry generator 400 for accepting two 8-bit operands and producing at its output the highest carry, say, out of a possible set of (Co, C1, ..., C7) for controlling its associated 2:1 MUX 160. Note that the lowest order (extreme left) MUX 160 is shown dotted so as to indicate that modularity consideration may require that each 8-bit conditional adder 141 be packaged with an associated MUX 160, in which case its control but would be set low because the absence of an input carry makes the SN output always valid. In effect, each of the three vertical grouping of units 141, 160 and 600 constitute a modular adder and carry-out generator 700 requiring its associated two fields of operand bits and carry-in bit. The tandem ensemble of these units makes-up the complete adder. The output sum is represented by the 25-bit sum SO-7, So 15. S16 232 S24.

In order to accommodate the carry-in bits (C-1, C7, C15) to units 600, a slight modification of the basic matrix and flow diagram must be made.

Consider, the unit 600 shown on the extreme right of Figure 19. The requisite matrix has the form

Note that if the carry-in, C 1, is zero (non-existent), the first row and column are zero. Also, P0=C.1 so that PO and all its product terms vanish if C.1 =0.

Thus, when C.1 =0, networks 300 and 400 are as previously defined. If C1=1 when the form of the matrix, carry-generator network 300 and propagation generator 400 have the same logic structure as previously described.

For example, Figure 20 shows the flow diagram corresponding to a 4-bit carry-generator 300 with an input carry bit C 1, suitable for concatenating 4-bit conditional adder units in a similar fashion to that shown for 8-bit conditional adder units 141 in Figure 19. The necessary steps required for generating the output carry, Cg, are shown by solid lines while the dotted-lines represent the other possible, but not required, processing steps previously shown. This implies the carry-out generator structure 300' shown in Figure 21 using processing modules 10.

Figure 22 and Figure 23 are the corresponding flow diagram and simplified carry-out generator structure 300 for an 8-bit unit respectively, as used in the adder network of Figure 19.

Figure 24 shows a simplified block diagram for propagation generator 400' suitable for use with the 8-bit adder module 700 of Figure 19. The subset of propagation terms required the 4-bit carry-out generator 300' (P3P2P1Po, P3P2, P3 P1) is also available from this unit.

The same flow diagram and logic networks are applicable to all concatenated units 600 of Figure 19. However, in the case of the lowest significant unit 600 at the extreme right of Figure 19, the carry-in from the previous stage is non-existent so that C.1 =0. For the other stages, the carry-out of the previous section is used as the carry-in.

Clearly, the concept of modular carry propagation for extended operand precision, an example of which is shown in Figure 19 is adaptable to the use of 4, 8, 16,... or any other size modular bit units by implementing units 600, 160 and 141 for the word size desired. Also, mixed systems in which associated units 600, 160, and 141 of a given 700 section, are of the same word size, but not necessarily the same word size the other 700 units tandemly connected with it, can be constructed.

These and other similar variations will become apparent to those versed in the art.

Claims (12)

1. A parallel carry generating network for use in a multibit binary adder comprising: (a) means for accepting a first and second N-bit binary operands; (b) carry propagation logic network array for generating conditional carry propagation terms by parallel logical operations on pairs of corresponding bits of said first and second operands; and (c) carry generator logic array for generating final sum carry bits, comprising: i) logic network for generating unconditional carry terms by parallel operation on said pairs of corresponding bits of said first and second operands; and ii) logic network array for accepting and operating on said unconditional carry terms and said conditional carry terms for producing a parallel set of final sum carry terms.

2. A parallel carry generating network as in Claim I wherein said carry propagation logic further comprises: (a) a zero level (I=0) multiplicity of N-l gates for the logical OR-ing of said corresponding bit pairs for all said bit pairs except the least significant, producing at each gate output, its associated first level conditional carry term arranged in ascending order of said operand bit pair inputs; (b) a first level (I=1) multiplicity of N-2 AND-gates, each said gate accepting as inputs adjacent overlapping ascending order outputs producing an ordered ascending set of second level conditional carry terms; and (c) additional higher levels of AND-gates, each succeeding level having N-21 AND-gates, each said gates having a first input connected its corresponding lower level ordered output and second input connected to the 21 1h lesser ordered output of said lower level, for forming the required higher level up to and including level, I=L, for which 21 = N/2; each level producing succeeding higher order conditional carry terms at the individual AND-gate outputs.

3. A parallel carry generating network as in Claim 1 wherein said carry generator logic array further comprises: (a) a zero level (I=0) multiplicity of N gates in parallel for the logical AND-ing of said corresponding operand bit pairs producing at each gate output the unconditional carry term associated with said operand input bit pair, said outputs being arranged in ascending order corresponding to the ascending order of said operand input bit pairs; (b) carry generator processor having a first second and third input, said first and second inputs connected to distinct partial carry terms of the same next lower level and said third input connected to an associated conditional carry term provided by said conditional carry generator for producing at its output a next level partial carry term;; (c) a first level (1=1) multiplicity of N-l processors arranged in ascending order each having a first, second and third input, each said first input connected to one corresponding zero level processor outputs for all outputs except that associated with the least significant of said input bit pairs, said second input of each processor connected to the output of the zero level gate associated with the next least significant of said input bit pairs, each said third processor input connected to the corresponding zero level output of said carry propagation logic, producing at a each processor output a partial carry term of second order arranged in ascending order; and (d) additional higher levels (I = 2, 3,..., L) of processors each level having N-21-1 processors, each said first input connected to one said corresponding next lower level processor output for all outputs in ascending order beginning at the 211 output, said second input of each processor connected to the output of the next lower level processor at 21-1 positions below said corresponding next lower level processor input to said first input, and said third input connected to the corresponding liii level conditional carry generator output.

4. A parallel carry generator network as in Claim 3 wherein said carry processor comprises: (a) OR-gate with an output and a first and second input; said first input connected to said processor first input, said OR-gate output being said processor output; and (b) AND-gate with its output connected to said OR-gate second input, with a first and second input, said first input connected to said processor second input and said second AND-gate input connected to said processor third input.

5. A parallel adder network comprising: (a) parallel sum unit having first, second and third set of inputs, said first and second input set for accepting a first and second input operand, said third input set connected to the output of a parallel carry generating network, for accepting parallel carry bits and producing the sum of the input operands.

(b) parallel carry generating network having a first and second operand and generating at its output terminals a parallel set of carry bits.

6. A parallel adder network as in Claim 5 wherein said parallel sum unit further comprises a multiplicity of sum units, one for each operand bit pair comprising adder means for forming the modulo-2 sum of each corresponding operand bit pair and carry bit.

7. A parallel adder network as in Claim 6 wherein said adder means comprises exclusive-or gates.

8. A carry generating module comprising: (a) an equal number of first and second level carry generator processors each having a first, second and third input, said first and second input connected to distinct partial carry terms from the corresponding next lower level output, said second input connected to associated displaced partial carry terms from the next lower layer output and said third input connected to an associated conditional carry term from the next lower layer output, for producing at each said carry generator processor output a next level partial carry term; (b) means for connecting said output of each said first level carry generator processor to a corresponding said second level processor first input; (c) means for connecting said first and second level processor outputs to a first set of external terminals;; (d) means for connecting said first and second level processor second and third inputs to a second set of external terminals; and (e) means for supporting said network as a unitized structure.

9. A multibit adder network comprising: (a) modular adder and carry-out generator unit capable of accepting two fields of operand bits and an input carry bit for producing the sum and output carry, said modular adder and carry-out generator comprising a conditional sum adder, conditional sum selector means controlled by the input carry, and a parallel carry generator unit for generating said output carry from said operand bits and input carry bits; (b) multiplicity of said modular adder and carry-out generator units connected in tandem so that the prior modular adder and carry-out generator carry-out is connected to the control input of said conditional sum based on a carry-in is selected when said prior carry-out is asserted, otherwise selecting the other conditional sum, said selected sums and final carry-out being representative of the desired adder output.

10. A modular multibit adder network as in claim 9 wherein each said modular adder and carry-out generator units accepts two input operand pairs comprising a like number of bits.

11. A modular multibit adder network as in claim 9 wherein each said modular adder and carry-out generator units may each accept input operand pairs of differing numbers of bits.

12. A modular carry prçpagation unit for use in a modular multibit adder network comprising: (a) a simplified carry generator for generating an output carry bit from the two sets of operand bits and a carry-in bit comprising a minimum set of processor elements necessary to generate said output carry bit, controlled by an associated minimum set of propagation variables; and (b) a simplified propagation generator for generating propagation control variables from the two sets of operand bits and a carry-in bit comprising a minimum set of logic elements necessary to generate said minimum set of propagation variables needed to control said simplified carry generator.