GB2138998A - Chip carrier package for semiconductor devices - Google Patents

Abstract

A chip carrier formed from ceramic, plastic or glass epoxy combination for packaging high lead count semiconductor devices comprises a plurality of arms radiating from a central area and terminal connecting points arranged at the outer end of each arm. <IMAGE>

Description

SPECIFICATION Chip carrier package for semiconductor devices This invention relates to a chip carrier package for semi-conductor devices otherwise known as integrated circiuts. In particular to chip carriers of high lead count (terminals) and containing one or a pluricity of integrated circuits.

Known forms of semiconductor packages of high lead count consist of the following.

The four or two sided chip carrier manufactured in a multiplicity of materials but originally ceramic, and more recently, of plastic materials, consisting of a base on the upper face of which, in a central position is an area for mounting the semiconductor device, by for example eutectic soldering. Connections are then made from the appropriate points on the device to electrically conductive pads on the base, usually of a metallic nature. These pads are in turn electrically connected to outside contact points along the sides of the carrier, again usually metallic. The device and the immediate links are then usually protected by a suitable coating of, for example, a silicon material and/or by a lid.

Another package is similar in internal detail but the terminals are arranged over the underneath of the base as a matrix of pads or pins.

The packaged device is then mounted, usually with other devices, to a main assembly, for example, a printed circuit board to form a complete circuit.

With each of the above types of package problems are encountered when dealing with large lead out (terminal) requirements.

For the two or four sided chip carrier the terminals are formed by cutting the sides centrally through holes arranged along the line of the side and a single row can be accommodated on any one side, thus causing the carriers for large lead counts to be physically large compared with the contained device.

With matrix terminal packages those with pins are unsuitable for the future interconnect technology requirements, namely surface mounted compaonents, as they require insertion into the mian assembly. Those with a matrix of pads, though suitable for surface mount technology, present an impossible inspection condition when attached to the main assembly as most of the connections are hidden under the device.

In the present invention is provided a chip carrier that provides full inspection of all terminals when connected to the main assembly, it is of a much reduced size than of a conventional chip carrier and can, by the prudent choice of materials (as outlined below), be thermally compatiable with any main assembly material.

The chip carrier base central area will contain an area for mounting the semiconductor device or the combination of several, and any internal interconnect requirements. From the border of this central area will radiate an electrically conductive pattern connecting a pad at the central end, to which the appropriate point of a semiconductor device will be linked, to the terminal at the outer end, which is along a side arm from the central area of the base.

The carrier may also have provided an optional wall or ring around the central area to form a cavity for the device to be mounted in, and a ring at the outer end of the terminal arms for mechanical strength and as an aid for automatic handling.

The materials used for the carrier may be any suitable combination of electrically non conductive material for the base such as ceramic, plastic or epoxy glass combinations coupled with a suitable choice of electrically conductive material for connecting the pads for the links from the semiconductor device to the terminals of the carrier.

The cavity rings (walls) and the peripheral mechanical integrity ring may be formed of any suitable material and method for example, plastic by moulding.

So that a clearer understanding may be acquired of the current invention, one construction and manufacturing process will now be described with reference to the accompanying drawings in which Figure 1 is a plan view of the Stage 1 array Figure 2 is a top and reverse view of Stage 2 Figure 3 An array of the chip carriers in the manner of the invention from a base material (1) such as a flexible copper coated plastic material, such as used for flexible circuits in the printed circuit industry.

The base sheet (1) is fabricated with a series of arrays of electrically conductive pads (2) arranged in rows. There is fabricated on the reverse a similar array of rows of pads (3). The holes (4) are formed in each pad (2) and an electrically conductive material plated though the base (1) to join pads 2 and 3. This is performed for all pads (2) in the array, all being carried out by conventional printed circuit board manufacture techniques and currently are preferably manufactured using gold or nickel gold on copper with a nickel barrier for the conductive material. The jig holes (5) are formed. The array of carriers is now separated into strips along the interface lines (10) (4).

The strips are now stacked together on edge utilising the jig holes (5) for accurate alignment and clamped in a jig arranged on a slitting saw so that the stack may be accurately positioned relative to the blade (Figure 3) and may then be stepped accurately so that the blade may pass through the stack to a predetermined depth and passing centrally through each row of pads (2), leaving approximately a semicircular capillary hole at each interface between slit and appropriate part of pad 2 as shown in Figure 4.

The strips are now again laid flat on a jig plate (3) and a semiconductor device(s) fixed to the base (1) at the appropriate point in the central area of each chip carrier.

Electrical connections are now made from the device(s) to the pads (8) by an appropriate means such as wire bonding or a TAB process. If a die cavity and outer mechanical ring are required then the jig plate (9) will already form the base of the plastic mould. The upper part of the mould tool will now be placed in position. Note that it is designed to put gentle curves between the terminal points of each arm. This is to retain the flexible properties of the base material in order that it may thermally match any main material. Figure 5 The plastic frame is now moulded in position.

Finally the die cavity may be filled with a suitable encapsuiaton to provide protection and finally a lid may be affixed over the die cavity and the whole removed from the jig.

The strips are then divided into single carriers by a simple guillotine operation.

Claims (9)

1. A chip carrier consisting of a base of plastic and an electrically conductive pattern connecting central connection points to which a semiconductor device may be linked and terminal connecting points arranged on the edge of arms of the base radiating from the central area to the effective peripheral of the carrier.

The base being mechanically suppoerted by a framework attache dto the upper surface of the base and the material of the arms formed to absorb thermal stress.

2. A chip carrier as detailed in claim 1) without framework in part or full.

3. A chip carrier as detailed in claim 1) or 2) with in full or part or without framework and having terminals along arms radiating outward and formed from a a ceramic material.

A chip carrier as detailed in any of the above claims made of any epoxy glass combination with or without a plastic frame.

5. A chip carrier as detailed in claim 1) where terminal connections are formed by plated through holes on arms perpendicular to the appropriate peripheral line of the carrier and effectively radiating from the central area to that peripheral in rows, and effectively facing along lines parallel with the peripheral edge.

6. A method of manufacture for making chip carriers as detailed in claim 1)

7. A chip carrier as in any of the above claims where terminal connections are formed by printing techniques with or without the aid of a vacuum.

8. A chip carrier as in any of the above claims where terminal connections are formed by vacuum deposition techniques.

9. It is claimed a chip carrier of basic design identified in the above fabricated from a separate metallic conductor pattern and then encapsualted in a plastic moulding with terminals as in the above claims or extending below the main base line and being part of the main metallic pattern.