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GB2114821A - Semiconductor chip package carrier - Google Patents

Semiconductor chip package carrier Download PDF

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Publication number
GB2114821A
GB2114821A GB08201482A GB8201482A GB2114821A GB 2114821 A GB2114821 A GB 2114821A GB 08201482 A GB08201482 A GB 08201482A GB 8201482 A GB8201482 A GB 8201482A GB 2114821 A GB2114821 A GB 2114821A
Authority
GB
United Kingdom
Prior art keywords
carrier
chip package
base
contacts
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB08201482A
Other versions
GB2114821B (en
Inventor
Norman Cameron Thompson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GE Healthcare UK Ltd
Plessey Co Ltd
Original Assignee
GE Healthcare UK Ltd
Plessey Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GE Healthcare UK Ltd, Plessey Co Ltd filed Critical GE Healthcare UK Ltd
Priority to GB08201482A priority Critical patent/GB2114821B/en
Publication of GB2114821A publication Critical patent/GB2114821A/en
Application granted granted Critical
Publication of GB2114821B publication Critical patent/GB2114821B/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00Constructional details common to different types of electric apparatus
    • H05K7/02Arrangements of circuit components or wiring on supporting structure
    • H05K7/10Plug-in assemblages of components, e.g. IC sockets
    • H05K7/1053Plug-in assemblages of components, e.g. IC sockets having interior leads
    • H05K7/1061Plug-in assemblages of components, e.g. IC sockets having interior leads co-operating by abutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Connecting Device With Holders (AREA)

Abstract

A carrier for a semiconductor chip package of the type having metallised connection contacts (e.g. JEDEC types) comprises a resilient base (10/14) adapted on its upper side to receive and locate the chip package (18). A multiplicity of contacts are provided on the resilient base and electrical conductor means 16 extends between each contact on the base and a termination 22 which extends on the lower side of the base. Retaining means (24, 26, 28) is provided which is operable to urge the chip package 18 into compressive contact with the base to effect a releasable connection between the contacts 20 on the chip package 18 and corresponding contacts on the base. The carrier may be permanently secured to a printed circuit board and enables the chip package to be charged without destroying the board. <IMAGE>

Description

SPECIFICATION Semiconductor chip package carrier This invention relates to a semiconductor chip package carrier for chip packages of the type having metallised connection contacts for example JEDEC packages.
Semiconductor chip packages of the type having metallised connection contacts are normally soldered or pressure welded onto printed circuit boards during the manufacture of equipment. Such constructions are difficult to service as it is often impossible to remove a chip package without destroying the printed circuit board. The present invention seeks to provide a carrier for a semiconductor chip package which enables the chip package to be replaced so that the carrier itself can be permanently secured to a printed circuit board whilst enabling the chip package to be changed. The carrier is applicable both to original equipment manufacture and also is particularly advantageous in chip package testing equipment where it permits simple and accurate location and connection of a chip package into a test circuit.
According to the invention there is provided a carrier for a semiconductor package of the type having metallised connection contacts, the carrier comprising a resilient base adapted on its upper side to receive and locate the chip package, a multiplicity of contacts on the resilient base positioned for engagement with the contacts of the chip package when located on the base, electrical conductor means extending between each contact on the base and a termination which extends on the lower side of the base, retaining means operable to urge the chip package into compressive contact with the base to effect a releasable contact between the contacts on the chip package and corresponding contacts on the base.
The base may comprise a substantially rigid lower portion provided with the terminations which extend therethrough to an upper surface and a resilient spacer positionally locatable on the upper surface of the lower portion and provided with said multiplicity of contacts and said electrical conductor means. The spacer may be formed from an elastomer. The resilient spacer may be provided with combined contact and conductor means formed as metallisations which extend from its upper surface over the periphery to its lower surface. In a particularly advantageous form the spacer is in the form of an apertured plate and the metallisations forming conductor means for each contact extend continuously from the contact over the outer perimeter, the lower perimeter and the inner perimeter to the contact to form a loop.
The base may be in the form of a housing and a closure may be provided for urging the chip package into compressive contact with the base.
The spacer may have a recess which conforms to the outline shape of the chip package and serves to positionally locate the package.
Alternatively the housing may have inner dimensions conforming to the outline dimensions of the chip package to positionally locate the package.
In order that the invention and its various other preferred features may be understood more easily, embodiments thereof will now be described, by way of example only, with reference to the accompanying drawings, wherein; Figure 1 is a cross sectional view to an enlarged scale of a carrier, constructed in accordance witn the invention for a semiconductor chip package the sectional axis being taken through the metallised contacts of the chip package, Figure 2 is an elevational view to a reduced scale showing a resilient spacer of the carrier of Figure 1, Figure 3 is a schematic illustration of some possible configurations of termination applicable to carriers constructed in accordance with the invention, Figure 4 is an elevational view of an alternative construction of a housing for a carrier constructed in accordance with the invention, and Figure 5 is an elevational view of an alternative construction of resilient spacer which may be employed with the carriers of Figures 1 or 4.
Referring now to Figure 1 the semiconductor chip package carrier comprises a rigid rectangular housing 10 moulded from a plastics material. The housing is open at one side and provides a rectangular cavity 1 2. Located in the base of the cavity there is a spacer 14 of rectangular plate like form having outer dimensions conforming to the dimensions of the cavity. The spacer is formed from an elastomer material and accordingly is resilient. Around the edges of the spacer 14 there are formed, by metallisation, fingers 16 of metal which extend from a position inset on the upper surface over the edge of the spacer to a position inset on the lower surface directly below there portion on the upper surface.These fingers are positioned so as to contact a metallised connection contact of a standard JEDEC type semiconductor chip package 18 which again has outlines dimensions conforming to the dimensions of the cavity 12. When the chip package 18 is inserted in the housing each of its metallised contacts 20 contact a different one of the fingers 16 which serve as electrically conductor means for interconnecting the contact 20 to a particular one of the terminations 22 which extend through the housing 10. In the particular embodiment shown in Figure 1 the terminations 22 are in the form of pins of configuration complying with a standard lead frame assembly.
The housing 10 is provided with a lid type closure 24 which is pivotally mounted by means of a pivot 26 and releasably closeable over the open side of the housing to close the cavity 1 2.
The lid is provided with an internal pressure spring 28 which in the closed positioned, shown in the drawing serves to press the chip package 18 against the spacer 14 thereby compressing the spacer against its natural resilience and ensuring good electrical contact between the metallised contacts 20 of the chip package and the fingers 16 and also between the fingers 16 and the terminations 22. The spacer 14 is shown in greater detail in elevation in Figure 2.
The terminations 22 in Figure 1 are shown to be in the form of pins but may be of any other suitable form. Some alternative possible configurations of the terminations are shown in Figure 3. The termination 22 comprises a wire or strip inserted through a hole in the housing 10 and bent over internally to form a contact portion 28 for cooperation with a finger 14. The termination 30 comprises 3 wire or sfrip inserted through a hole in the housing 10 and bent over inside and outside the housing to form a C-shaped termination the internal contact portion 28 being for cooperation with a finger 14 whilst the contact portion 32 constitutes one contact of the housing for connection to a printed circuit board.A multiplicity of the contacts 32 are arranged on the housing so as to reproduce the contact positions of the semiconductor chip package and the carrier then has the same "footprint" as the chip package. This arrangement is particularly advantageous as it permits either a chip package or a carrier for receiving a chip package to be connected to a printed circuit board and enables equipment to be manufactured with either removable or non-removable semiconductor chip packages. Terminations 34 and 36 are again formed from wire or strip metal bent to the configurations illustrated. They each provide an internal contact portion 28 for cooperation with a finger 1 6.
Figure 4 shows an alternative housing 38 moulded from a plastics material and a removable lid 40. The housing is again rectangular and is moulded from a plastics material. The base of the housing is provided with holes 42 and 44 for receiving terminations 22, 30, 34 or 36. Only some of the holes are illustrated and only two possible alternative configurations of hole pattern are shown. The holes 42 are disposed in a single line whilst the holes 44 are disposed in two parallel lines with holes in adjacent lines being staggered to improve separation. With both configurations the contact portions 28 would be arranged to cooperate with fingers 16 of the spacer 14.The walls of the rectangular housing are provided adjacent its open side and near to each corner with cut-outs 46 of rectangular form, two on each side for receiving projecting tongues 48 on the plate like lid 40. The lid is formed from a springy material e.g. spring metal or plastics and is bowed in two directions to form a shallow dish shape. The lid is inserted into the housing with the disposition shown in the drawings such that its bowed outward surface faces outwardly. The lid is then depressed inwardly of the housing where upon it springs into an over centre positioned such that it is bowed inwardly and urges the chip package into intimate contact with the spacer 14 thereby compressing the spacer and effecting contact between the fingers 16, the metallised contacts of the chip package and the terminations.
Figure 5 shows an alternative resilient spacer in the form of a rectangular frame 50 formed from an elastomeric material. Each side of the frame is provided with several metallised strips 52 each of which extends transversely right round that side of the frame to form a continuous loop. The strips 52 are disposed so as to align with the metallised contacts of a chip package and with the terminations provided on the housing. This configuration is particular by advantageous in that the formation of the metallised strips as continuous loops results in reduction of inductance, capacitance and resistance.
Elastomeric materials normally have a low dielectric constant and this enhances the effectiveness of the strips 52.
The use of a removable resilient spacer member such as 14 or 50 is particular advantageous in that if damage should occur to the fingers 1 6 or metallised strips 52 then the spacer can be replaced without requiring removal of the housing from the printed circuit board. This is of particular value in application to test equipment for semiconductor chip packages where continual replacement of packages to be tested is involved.
Instead of employing a housing having internal dimensions conforming to the outer periphery of the semiconductor chip package in order to provide accurate location of the package within the housing, the spacer itself may be provided with some means of accurately locating the chip package e.g. a recess into which the chip package locates. This configuration is particular advantageous in that it permits a common housing to accommodate different configurations of chip package purely by changing to an appropriate resilient spacer.
Instead of employing a base which comprises a housing and a separate resilient spacer, the housing itself may be formed of a resilient material and provided with terminations which have extensions forming conductor means and contacts for engagement with the contacts of the chip package. Such a construction may employ any of the features previous described and is more likely to find application where regular replacement of chip packages is not envisaged.
In conclusion some of the advantages which may be obtained from constructions previously described are a) accurate alignment and connections of the chip package.
b) simple maintenance by replacement of resilient spacer members.
c) provision of a socket having the same "footprint" as a semiconductor chip package.
d) good performance at RF frequencies.
e) application to original equipment manufacture, production or test usage.

Claims (14)

1. A carrier for a semiconductor chip package of the type having metallised connection contacts, the carrier comprising a resilient base adapted on its upper side to receive and locate the chip package, a multiplicity of contacts on the resilient base positioned for engagement with the contacts of the chip package when located on the base, electrical conductor means extending between each contact on the base and a termination which extends on the lower side of the base, retaining means operable to urge the chip package into compressive contact with the base to effect a releasable connection between the contacts on the chip package and corresponding contacts on the base.
2. A carrier as claimed in claim 1, wherein the base comprises a substantially rigid lower portion provided with the terminations which extend therethrough to an upper surface and a resilient spacer positionally locatable on the upper surface of the lower portion and provided with said multiplicity of contacts and said electrical conductor means.
3. A carrier as claimed in claim 2, wherein the spacer is formed from an elastomer.
4. A carrier as claimed in claim 2 or 3, wherein the resilient spacer is provided with combined contact and conductor means formed as metallisations which extend from its upper surface over the periphery to its lower surface.
5. A carrier as claimed in claim 4, wherein the spacer is in the form of an apertured plate and the metallisation forming the conductor means for each contact extends continuously from the contact over the outer perimeter, the lower perimeter and the inner perimeter to the contact to form a loop.
6. A carrier as claimed in any one of claims 1 to 5, wherein the base is in the form of a housing and a closure is provided for urging the chip package into compressive contact with the base.
7. A carrier as claimed in any one of claims 2 to 6, wherein the spacer has a recess which conforms to the outline shape of the chip package and serves to positionally locate the package.
8. A carrier as claimed in claim 6, wherein the housing has inner dimensions conforming to the outline dimensions of the chip package and serves to positionally locate the package.
9. A carrier as claimed in claim 6 or 8, wherein the closure comprises a resilient bowed plate locatable on the housing in a bowed out configuration and conformable through an overcentre position to a bowed in position where it is self retaining on the housing and serves to urge the chip package into compressive contact with the base.
10. A carrier as claimed in any one of the preceding claims, wherein the terminations on the base conform to the same dispositions as the connections on the chip package whereby chip package and carrier are interchangeable.
1 A carrier as claimed in any one of claims 1 to 9, wherein the terminations on the base are in the form of a standard lead frame.
12. A carrier as claimed in claim 1 wherein leads of the standard lead frame are arranged in single line configuration.
13. A carrier as claimed in claim 1 wherein leads of the standard lead frame are arranged in dual line staggered configuration.
14. A carrier for a semiconductor chip package of the type heaving metallised connection contacts, the carrier being substantially as herein described or as illustrated in the drawings.
GB08201482A 1982-01-19 1982-01-19 Semiconductor chip package carrier Expired GB2114821B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB08201482A GB2114821B (en) 1982-01-19 1982-01-19 Semiconductor chip package carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB08201482A GB2114821B (en) 1982-01-19 1982-01-19 Semiconductor chip package carrier

Publications (2)

Publication Number Publication Date
GB2114821A true GB2114821A (en) 1983-08-24
GB2114821B GB2114821B (en) 1985-10-23

Family

ID=10527726

Family Applications (1)

Application Number Title Priority Date Filing Date
GB08201482A Expired GB2114821B (en) 1982-01-19 1982-01-19 Semiconductor chip package carrier

Country Status (1)

Country Link
GB (1) GB2114821B (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2149980A (en) * 1983-11-15 1985-06-19 Gen Electric Co Plc Packaging integrated circuits for connection to hybrid circuits
GB2203270A (en) * 1987-03-05 1988-10-12 Seiko Epson Corp Timepiece assembly
US5369627A (en) * 1987-07-21 1994-11-29 Seiko Epson Corporation Improvements in bearing and frame structure of a timepiece
US5416752A (en) * 1987-07-21 1995-05-16 Seiko Epson Corporation Timepiece
EP1085794A1 (en) * 1999-09-15 2001-03-21 CONNECTEURS CINCH, Société Anonyme dite : Junction box for electronic components
WO2001082009A3 (en) * 2000-04-20 2002-08-22 Cogiscan Inc Automated manufacturing control system
CN112992821A (en) * 2019-12-13 2021-06-18 珠海格力电器股份有限公司 Chip packaging structure and packaging method thereof

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2149980A (en) * 1983-11-15 1985-06-19 Gen Electric Co Plc Packaging integrated circuits for connection to hybrid circuits
GB2203270A (en) * 1987-03-05 1988-10-12 Seiko Epson Corp Timepiece assembly
US5008868A (en) * 1987-03-05 1991-04-16 Seiko Epson Corporation Structure for mounting an integrated circuit
GB2203270B (en) * 1987-03-05 1991-09-11 Seiko Epson Corp Timepiece assembly.
US5369627A (en) * 1987-07-21 1994-11-29 Seiko Epson Corporation Improvements in bearing and frame structure of a timepiece
US5416752A (en) * 1987-07-21 1995-05-16 Seiko Epson Corporation Timepiece
US5712831A (en) * 1987-07-21 1998-01-27 Seiko Epson Corporation Timepiece
EP1085794A1 (en) * 1999-09-15 2001-03-21 CONNECTEURS CINCH, Société Anonyme dite : Junction box for electronic components
FR2799923A1 (en) * 1999-09-15 2001-04-20 Cinch Connecteurs Sa INTERCONNECTION BOX FOR ELECTRONIC COMPONENTS
WO2001082009A3 (en) * 2000-04-20 2002-08-22 Cogiscan Inc Automated manufacturing control system
US7069100B2 (en) 2000-04-20 2006-06-27 Cogiscan Inc. Automated manufacturing control system
US7286888B2 (en) 2000-04-20 2007-10-23 Cogiscan Inc. Automated manufacturing control system
CN112992821A (en) * 2019-12-13 2021-06-18 珠海格力电器股份有限公司 Chip packaging structure and packaging method thereof

Also Published As

Publication number Publication date
GB2114821B (en) 1985-10-23

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Legal Events

Date Code Title Description
732 Registration of transactions, instruments or events in the register (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19940119