GB2193063A - Line circuits - Google Patents

Description

SPECIFICATION Subscriber line interface circuit This invention relates to a subscriber line interface circuit (SLIC) adapted for use in an electronic switching system. A subscriber line interface circuit is used to couple a subscriber terminal, typically a telephone set, with an exchange (an electronic exchange, particularly a digital exchange). The subscriber line interface circuit is coupled to a telephone set (subscriber terminal) and an exchange, and handles battery feed or current feed (B), supervisory (S) and hybrid functions (H). The supervisory function supplies a DC current to the telephone set coupled to a telephone line (or a subscriber line) and monitors the status of the handset of the telephone set. That is, the supervisory function monitors whether the handset is in the on-hook state or off-hook state. The battery feed function supplies a DC current to the telephone set to drive an audio exchange for the purpose of telephone communications. The hybrid function is a so-called a 2-to-4/4-to-2 wire conversion function, which terminates the telephone line with a complex impedance that matches with the telephone line impedance, extracts a communication signal from the telephone set into the exchange, and transfers a communication signal from the switching device of the exchange to the telephone set via a communications line.The subscriber line interface circuit having these functions may sometimes be called "BSH circuit." As mentioned above, it is necessary to supply a constant DC current to a telephone set via a telephone line, and at the same time, a voice signal flows through this same telephone line. In order to separate the voice signal, which includes an AC component, from the constant DC current and prevent the AC component from being superimposed onto the DC current, a conventional subscriber line interface circuit that comprises a hybrid coil and a switching current is provided with a large inductance coupled in series to a DC power source. With this design, the DC current is supplied to the telephone set via the inductance element.In order to prevent the DC current from leaking onto the telephone line, thus preventing the DC component from being superimposed onto the voice signal, a capacitor of as large as 2 MicroF is coupled in series to each of a pair of telephone lines so that the voice signal is transferred via this capacitor to the hybrid circuit for 2-to-4/4-to2 wire conversion. However, the subscriber line interface circuit of this type needs relatively large inductance element and capacitor. In this respect, this subscriber line interface circuit is not suitable to make the electronic exchange compact, reduce the manufacturing cost of the subscriber line interface circuit or realize its large integration. In circuit calculation or design, the line impedance of a telephone line is typically treated to be

characteristic when coupled to a subscriber line interface circuit through a telephone line whose length is set to provide a line loss of 5dB. However, in the case of a private branch exchange (PBX), the telephone line has a relatively short length and its allowed line loss is reduced to 2dB or below. Since a subscriber line interface circuit is used in such a private branch exchange, its terminal impedance and/or balance network impedance is demanded to have a complicated characteristic that should also include the cable characteristic of the telephone line. As already mentioned, the conventional subscriber line interface circuit needs a large inductance and/or capacitor to attain a predetermined impedance, so that this restriction significantly hinders the realization of a compact exchange. To overcome this problem, it has been proposed to realize the functions of the traditional subscriber line interface circuit using an electronic circuit. However, this electronic circuit needs a number of circuit elements and is not therefore effective in reducing the size and the manufacturing cost of the subscriber line interface circuit. An example of such an electronic subscriber line interface circuit is disclosed in Japanese Patent Disclosure (Kokai) No. 58-104558. For example, Fig. 3 of this publication shows a series circuit of a terminal resistor (31) and a capacitor (32) of a subscriber line, which gives a predetermined value to the impedance of the subscriber line interface circuit as measured from the side of the subscriber terminal. The system with such a series circuit requires that the capacitor should have a large volume or a large size. This stands in the way to reduce the size of the system (the subscriber line interface circuit).In addition, the conventional circuit necessitates that a resistor denoted by 52 in Fig. 3 or 68 in Fig. 4 of the aforementioned Japanese publication should have a highly accurate absolute value and should be constituted by a discrete element for securing the necessary accuracy. Since the above capacitor and resistors are constituted by discrete elements, not all the constituent elements of the conventional subscriber line interface circuit can be integrated in a circuit if tried. Therefore, enlarging the overall exchange system cannot be avoided. The number of subscriber line interface circuits in use increases as the number of lines that the exchange handles increases. This means that reduction in size and manufacturing cost of the overall enchanger system cannot be realized without reducing the size and the manufacturing cost of the subscriber line interface circuit itself. As mentioned above, a conventional electronic circuit requires elements large in size and number and also a complex control in order for the circuit to provide the terminal impedance and/or various functions, such as the current feed, supervisory and hybrid functions, necessary for a subscriber line interface circuit. With the above situation in mind, it is an object of this invention to provide a subscriber line interface circuit, which eliminates the need to use large elements and ensures large scale integration (LSI) and reduction in size and manufacturing cost, thus contributing to reducing the size and manufacturing of the overall exchange system. The subscriber line interface circuit according to this invention comprises a pair of subscriber nodes, a pair of reception nodes and a pair of transmission nodes, a power feeding unit, first and second adder units, first and second impedance elements, an inverting amplifier, and a feedback element. The subscriber nodes are coupled to a subscriber terminal via a subscriber line, and the reception and transmission nodes are coupled to an exchange via a unilateral reception line and a unilateral transmission line, respectively. The power feeding unit supplies a DC current to the subscriber terminal and controls the current. The first adder unit adds the voltage between the subscriber nodes and the voltage supplied from the reception node.The first impedance element has an impedance corresponding to a real-number multiplication of. the impedance between the subscriber nodes, as observed from the side of the subscriber line, and is applied with the output voltage of the first adder unit. The inverting amplifier is given with the output of the first impedance element. The second impedance element, which is inserted in the feedback path of the inverting amplifier, has an impedance corresponding to a real-number multiplication of the impedances of the subscriber line and the subscriber terminal, as observed from the side of the subscriber nodes. The feedback element supplies, to the power feeding unit, a signal corresponding to the current flowing through the first impedance element as a control signal.The second adder unit adds the output voltage of the inverting amplifier, the output voltage of the first adder unit and the voltage supplied to the reception node, and supplies the resultant signal to the transmission node. A practical example of the subscriber line interface circuit according to this invention has a power feeding unit, which feeds a DC current to the subscriber terminal from a pair of subscriber nodes L, and L2 via the subscriber line. This power feeding unit is capable of controlling the output current in response to a control signal. The voltage between subscriber nodes L, and L2 and the received voltage VRX suplied to the reception node from the exchange via the reception line are each subjected to weighting and are then added together. The resultant voltage VP is supplied to the first impedance element having a complex impedance NZT. The complex impedance NZT equals N (real number) times the impedance ZT of the subscriber line interface circuit, which is measured from the side of the subscriber nodes. The first impedance element is coupled to the inverting input node of a buffer amplifier, which is provided with a negative-feedback by the second impedance element having an impedance MZB. This impedance MZB equals M (real number) times the impedance ZB of the subscriber terminal as measured from the side of the subscriber line interface circuit. The current flowing through the first and second impedance elements is fed back to the power feeding unit as a control signal.(Since the input impedance of the buffer amplifier is sufficiently large, the current flowing through the second impedance element accords with the current flowing through the first impedance element.) According to the subscriber line interface circuit of this invention, the size or the number of the circuit elements can be significantly reduced by detecting a load current from the impedance element provided on the input side of the buffer amplifier or from the impedance element that forms the feedback path of the buffer amplifier. Moreover, since the values of these impedance elements are each a real-number multiplication of the terminal impedance, the value of a capacitor included in each impedance element is a real-number fraction of the terminal impedance. This means that a small capacitor suffices for each impedance element.What is more, according to this subscriber line interface circuit, the detected DC current can be fed back to the power feeding unit without converting it to a voltage. As should be understood from the above description, when the detected DC current is fed back without any conversion to the power feeding unit, it is not necessary to use a resistor with an accurate absolute value, which should be constituted by a discrete element when integrating the subscriber line interface circuit into a circuit. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figs. 1 A and 1 B are diagrams for explaining, the hybrid function of a subscriber line interface circuit; Fig. 2 is a block diagram for explaining the principle of a subscriber line interface circuit according to the first embodiment of this invention; Fig. 3 is a block diagram showing the configuration of the subscriber line interface circuit according to the first embodiment of this invention, which is operated under the principle illustrated in Fig. 2; Fig. 4 is a block diagram showing the configuration of a subscriber line interface circuit according to the second embodiment of this invention; Fig. 5 is a diagram for explaining a current feed function of a subscriber line interface circuit;Fig. 6 is a block diagram exemplifying the configuration of a power feeding circuit used in the subscriber line interface circuit of this invention; Fig. 7 is a block diagram illustrating the configuration of a power feeding circuit used in the embodiment shown in Fig. 3; Fig. 8 is a block diagram illustrating the configuration of a current detection circuit applied to the embodiment of Fig. 3; and Fig. 8 is a block diagram showing the configuration of a subscriber line interface circuit according to the third embodiment of this invention. A subscriber line interface circuit according to the first embodiment of this invention will now be explained. To begin with, the hybrid function and the impedance balancing in a subscriber line interface circuit will be summarized. Referring to Fig. 1 A, 4-to-2 wire conversion is explained below. The 4-to-2 wire conversion is a function, which, in an audio band (0.3 kHz-3.4 kHz), (a) makes the appeared impedance of the subscriber line interface circuit (the right-hand side of the broken line in Fig. 1 A), as measured from the side of a subscriber (the left-hand side of the broken line in the diagram), as ZT, and (b) causes a reception signal VRX from a codec of an exchanger to have a level of {ZB'/(ZT + ZB')}VRX and be transmitted to the subscriber's side, and (c) prevents

Referring now to Fig. 1 B, 2-to-4 wire conversion is explained below. The 2-to-4 wire conversion is a function, which, in the above audio band, (d) makes the appeared impedance of the subscriber line interface circuit, as measured from the subscriber's side, as a predetermined value ZT, which can externally be set, and (e) prevents a signal voltage VR from the subscriber terminal (which may be generated by a speech made by a subscriber) from being transmitted, as a transmission signal VTX, to the codec of the exchange. The following explains the principle of the subscriber line interface circuit according to the first embodiment of this invention, which satisfies these conditions (a) to (e), with reference to Fig. 2. The subscriber line interface circuit shown in Fig. 2 comprises current sources 1 and 2, buffer amplifiers 3 to 8, adders 8 and 10 and impedance elements 11 and 12. A subscriber terminal, such as a subscriber telephone set, is coupled to subscriber nodes L, and L2 via a subscriber line. In Fig. 2, the left-hand side of subscriber nodes L, and L2 is the subscriber's side (the subscriber line and subscriber terminal), while the right-hand side is the subscriber line interface circuit. The AC voltage between subscriber nodes L, and L2 is Vo, the equivalent impedance (load) of the subscriber's side as measured from subscriber nodes L, and L2 is ZB' and the AC voltage, such as a speech signal, that is generated by the subscriber terminal (or by the subscriber's speech), is VR. AC components H.i of the currents, which are generated from current sources 1 and 2 in the arrow directions in Fig. 2, flow through the subscriber line.(The output currents of these current sources can be controlled.) The current H.i is set to be H times the AC current i that flows through an impedance element 12 (to be described later) with a value MZB, i.e., M times the balancing impedance, where M is a real number. The amplification factors (weighting coefficients) of buffer amplifiers 3-8, which are weighting circuits), are A, to A5, respectively. Although not illustrated, reception node RX and transmission node TX are coupled to the exchange via a unilateral reception line and a unilateral transmission line, respectively. Reception voltage VRX is input to reception node RX from the exchange, while transmission voltage VTX is output to the exchange from transmission node TX.The voltage Vo between subscriber nodes L, and L2 is supplied via buffer amplifier 3 to adder circuit 9, which is supplied with voltage VRX from reception node RX via buffer amplifier 4 having an amplification factor of A2. Consequently, adder circuit 9 performs an addition (or a subtraction) on voltages VO and VRX that have been subjected to a weighting operation. That is, voltages Vo and VRX, which have been weighted respectively by the amplification factors of buffer amplifiers 3 and 4, are added (or subtracted from each other), thus providing voltage Vp. This voltage VP is applied to the inverting input node of buffer amplifier 8 via impedance element 11, which has a complex impedance NZT that equals N (real number) times the impedance ZT of the subscriber line interface circuit as measured from the side of the subscriber terminal.Impedance element 12, which has a complex impedance MZB equal to M times the nominal impedance ZB of the subscriber terminal's side, is provided between the inverting input node and the output node of buffer amplifier 8, thus forming a feedback path. The current i flowing through impedance element 12 is fed back to current sources 1 and 2 to control them so that a current, which is H times current i, is supplied to the subscriber terminal. The output of buffer amplifier 8 is supplied to adder circuit 10 via buffer amplifier 7 with amplification factor A5. Adder circuit 10 is also supplied with voltage VRX via buffer amplifier 5 with amplification factor A3 and voltage VP via buffer amplifier 6 with amplification factor A4.As a result, adder circuit 10 performs an addition (or a subtraction) of the output voltage of buffer amplifier 8, voltage VRX and voltage VP, which have been weighted by amplifiers 7, 5 and 6, respectively. The resultant voltage is supplied to transmission node TX as transmission voltage V TX' The subscriber line interface circuit with the aforementioned configuration is characterized in detecting load current i by the feedback path of buffer amplifier 8. This feature is further explained below. (I) [4-to-2 Wire Conversion/Transmission] First, let us consider the transmission of the unilateral reception voltage VRX received at reception node RX to subscriber nodes L, and L2 (voltage Vo). Here, the subscriber-originated signal voltage VR = 0. Paying attention to voltage Vo and current i, the following equation is yielded using the actual AC impedance ZB' on the subscriber's side.

Rearranging equation (91) yields

Using the terminal complex impedance ZT yields

Substituting equation (2) into equation (3) yields

Rearranging this equation, we obtain

Thus, the impedance of the subscriber's side as measured from subscriber nodes L, and L2 is ZT. (That is, the aforementioned conditions (a) and (b) are satisfied.) Next, let us consider the transmission of the unilateral reception voltage V RX received at reception node RX to the unilateral transmission voltage VTx at transmission node TX. Transmission voltage VTX is expressed by the following equation:

Substituting equation (5) into equation (6) yields

Setting A2 = A1 from the condition to attain equation (5), we obtain the following equation:

Now, let

and substituting the above conditions to equation (7), we obtain

Let M=N and that the impedance balancing is given i.e., ZB = ZB' (The nominal impedance ZB of the subscriber terminal's side is equal to the actual impedance ZB'.) Then,

which means that the mixing of reception voltage VRX into transmission voltage VTX can be. suppressed. (The aforementioned condition (c) is therefore satisfied.) (II) [2-to-4 Wire Conversion/Balancing] First, let us consider the transmission of signal voltage VR (the output of the subscriber terminal) to transmission voltage VTX at transmission node TX. Letting VRx = 0 in equation (6) yields

Also, the following is satisfied:

Eliminating the term i from equation (10) and solving the equation for Vo, we obtain

From equations (11) and (4), we obtain

Therefore, the input impedance of the subscriber line interface circuit as measured from the subscriber's side at the time of signal transmission can also be set to ZT. (That is, the aforementioned condition (d) is satisfied.) Substituting equation (11) into equation (9) yields

Now, substituting equations (4), (14) and (15) given below into equation (13) to set VTX = VR.

then

Therefore, when the impedance balancing is attained, i.e., when ZB = ZB', VTX = VR so that, for example, a speech signal from the subscriber is transmitted onto the unilateral transmission line from transmission node TX without linear distortion. (This satisfies the condition (e).) It is intended that nominal impedance ZB be equal to actual impedance ZB', but, in practice, it is not always possible to establish the relation ZB = ZB' in the audio band. This is why the nominal

distortion compensation is made by the impedance balancing, which means to assuming that ZB = 0 (ZB cannot be set to 0 in an actual circuit), then

Consequently, as is the case for an ordinary balancing circuit, no linear distortion occurs when

occurs. As explained above, according to the circuit shown in Fig. 2, by using an impedance that is N times the supposedly necessary terminal impedance and balancing impedance to set the amplifi-

these impedances can have 1/N of the otherwise necessary values, and the complex terminal impedance and hybrid function that are necessary for the subscriber line interface circuit can also be attained. In addition, since current i flowing through impedance element 12 having impedance MZB is fed back to current sources 1 and 2, the complex terminal impedance and the hybrid function can be realized at the same time. Referring now to Fig. 3, the following explains a subscriber line interface circuit according to the first embodiment of this invention which is designed on the basis of the above-explained principle. For easier understanding and also simplicity, reference numerals used in Fig. 2 are also used in Fig. 3 to denote the corresponding or substantially identical elements. The circuit section constituted by buffer amplifiers 3 and 4 and adder circuit 9 in Fig. 2 is constituted by a buffer amplifier 21, resistors 22-27 and a capacitor 28 in Fig. 3. The circuit section constituted by buffer amplifiers 5-7 and adder circuit 10 in Fig. 2 is constituted by a buffer amplifier 31 and resistors 32-36 in Fig. 3.

expressed by equations (4), (14) and (15) while reducing the number of the actually necessary buffer amplifiers as fewer as possible, these amplification factors need to be set, for example, as follows:

Since the phase of transmission voltage VTX is not so important from the functional view point, the number of the buffer amplifiers can be further reduced by outputting voltage VTX instead of

3 is designed in this manner. The resistances of resistors 22-27, 32-34 and 36 are R and the resistance of resistor 35 is 2R. The elements of this subscriber line interface circuit are arranged in Fig. 3 to show easier correspondences with amplification factors (weighting coefficients) shown in Fig. 2. Further, H = M = N = 100 and ZB = ZB . Since a DC current flows in an actual subscriber line, capacitor 28 is provided on the output side of buffer amplifier 21 to remove the DC component.For this purpose, instead of capacitor 28, capacitors may be inserted respectively between resistor 22 and subscriber node L, and between resistor 23 and subscriber node L2. However, this type of capacitor with a high withstand voltage needs to be large, so that the fewer such capacitors, the better. The circuit of Fig. 3 is designed to fulfill this condition, and therefore requires such a capacitor (28) only in the illustrated location. Subscriber nodes L, and L2 are coupled to currentcontrolled current sources 1 and 2, respectively. Subscriber node L, is coupled to the non-inverting node of buffer amplifier 21 through resistor 22.One end of each of resistors 24 and 26 is coupled in common to the non-inverting node of buffer amplifier 21, while the other end of resistor 24 is coupled to a common potential (ground) and the other end of resistor 26 is coupled to a given, fixed potential. subscriber node L2 is coupled the inverting input node of buffer amplifier 21 through resistor 23. Resistor 25 is coupled between the output node and the inverting input node of buffer amplifier 21, and resistor 27 is coupled between the inverting input node of buffer amplifier 21 and reception node RX. The output node of buffer amplifier 21 is coupled through capacitor 28 to one end of first impedance element 11 having an N-fold terminal impedance (NZT). The other end of impedance element 11 is coupled to the inverting input node of buffer amplifier 8.Second impedance element 12,

input node of buffer amplifier 8. The non-inverting input node of buffer amplifier 8 is coupled to a common potential (ground). Unilateral reception node RX is coupled through resistor 32 to the inverting. input node of buffer amplifier 31. The output node of buffer amplifier 31 is coupled to unilateral transmission node TX, and the inverting input node of buffer amplifier 31 is coupled through resistor 33 to the connecting node between capacitor 28 and first impedance element 11. Resistor 36 is coupled between the output node and the inverting input node of buffer amplifier 31. The noninverting input node of buffer amplifier 31 is coupled through resistor 35 to the output node of buffer amplifier 8, and is also coupled through resistor 34 to a common potential (ground). The following description will be given to show that the subscriber line interface circuit of Fig. 3 functions according to the above-explained principle. First, the aforementioned conditions (a) and (b) are considered. Given that VR = 0, let us now consider the transmission of unilateral reception voltage VRX to voltage Vo between Subscriber nodes L, and L2. From Fig. 3, the following two equations are attained:

Therefore,-the impedance of the subscriber line interface circuit as measured from the subscriber's side is ZT. Next, the aforementioned condition (c) is considered. In order to consider the transmission of unilateral reception voltage VRX to unilateral transmission node TX, transmission voltage VTX at transmission node TX is obtained.

Substituting equation (19) into equation (20) yields

Let us now consider the aforesaid conditions (d) and (e). With respect to the transmission of signal voltage VR, generated in the subscriber terminal, to transmission node TX, the following two equations are derived from Fig. 3.

Solving these two equations (21) and (22) for Vo, we obtain

Thus, the impedance of the subscriber line interface circuit as measured from the subscriber's side can be set to ZT. In this case, from Fig. 3, voltage -VTX of transmission node TX is expressed by the following equation:

From equations (23) and (24), we obtain

As should be clear from the above, signal voltage VR generated in the subscriber terminal is transferred as transmission voltage VTX, irrespective of the phase. According to the subscriber line interface circuit of Fig. 3, therefore, the terminal impedance ZT can be arbitrarily set and the hybrid function can be realized as well. In general, each terminal impedance ZT or ZB is a series circuit of a resistor (R,) and a capacitance. Since M-fold balancing impedance MZB is inserted in the feedback path of buffer amplifier 8, the DC feedback cannot be achieved by the feedback of a series circuit of a resistor and a capacitance alone. In

provided in parallel to MZB. According to the embodiment shown in Fig. 3, by setting H = N = M = 100, i.e., by using an impedance 100 times impedance ZB, the capacitance can be reduced to 1/100, thus making the overall subscriber line interface circuit compact, which is very advantageous in reducing the size through an LSI. A subscriber line interface circuit according to the second embodiment of this invention will now be explained with reference to Fig. 4. The circuit of Fig. 4 differs from that of Fig. 3 only in that the amplification factors of the

A1-A5 can be set to any value as long as the conditions given in equations (4), (14) and (15) are satisfied.) This means that the values of resistors 25, 26 and 33 and the value of resistor 35 in Fig. 3 are simply changed to R/2 and R, respectively, in Fig. 4. In this respect, therefore, the same reference numerals used in Fig. 3 are also used in Fig. 4. In the circuit of Fig. 4, amplification factor 41 is smaller than the one shown in Fig. 3. This is because due to a relatively high voltage applied between subscriber nodes L, and L2, the dynamic range of the subsequent line or circuit is considered. In the above embodiment, every resistor has either an integer multiplication or an integer fraction of a standard value R. This is because when realizing IC, it is easier to attain a high accuracy by using the same resistance for a plurality of resistors. Therefore, in practice, the values for a plurality of resistors used in this circuit need not be in an integer ratio; any

necessary accuracy. The DC current feeding function of the subscriber line interface circuit of this invention will now be explained, referring to Fig. 5. The subscriber line interface circuit SL includes a power feeding circuit not shown in Fig. 5. This power feeding circuit is provided to feed a constant current to a telephone set TP, which is typically used as a subscriber terminal coupled to subscriber nodes L, and L2 via a subscriber line, so as to drive an acoustic transducer, such as a carbon microphone used in the telephone set. The current IL flowing through the subscriber line can be set, as desired, by reference voltage Vref that is supplied to subscriber line interface circuit SI through resistor Rf.

A practical example of the above power feeding circuit will be explained, referring to Fig. 6. The power feeding circuit of Fig. 6 has amplifiers 51-54, current detection impedance elements 55 and 56 and resistors 57-62. Power feeding amplifier 52 is coupled to one of subscriber nodes, L,, through current impedance element 55. Subscriber node L, is also coupled to one end of impedance ZB' (as a load) of the subscriber terminal. Power feeding amplifier 53, which outputs a current of opposite phase to the phase of the current output by amplifier 52, is coupled to the other subscriber node L2 through current detection impedance element 56. Subscriber node L2 is also coupled to the other end of impedance ZB'. A series circuit of resistors 59 and 58 is coupled between the output node of amplifier 52 and subscriber node L2, as illustrated. A series circuit of resistors 57 and 60 is coupled between subscriber node L, and the output node of amplifier 53 (see Fig. 6).The connecting node between resistors 59 and 58 is coupled to the non-inverting input node of current detection amplifier 54, while the connecting node between resistors 57 and 60 is coupled to the inverting input node of amplifier 51. The inverting input node of amplifier 51 is further coupled to an external reference voltage Vref through resistor Rf. In other words, the inverting input node of amplifier 51 is supplied with a DC current signal I coming from external reference voltage Vref through Rf. A feedback resistor 61 is coupled between the output node and the inverting input node of amplifier 51. The output node of amplifier 51 is further coupled to the input node of amplifier 52 as well as the input node of amplifier 53.

52 and 53, which output currents of the opposite phases, through amplifier 51. The outputs of amplifiers 52 and 53 are supplied to the subscriber's side or impedance ZB' through impedance elements 55 and 56, respectively. At this time, the voltage drops in impedance elements 55 and 56 are added and detected by amplifier 54, and then are fed back to amplifier 51. That is, the signal resulting from the addition of the output of amplifier 54 and reference signal I (DC current) is fed back to amplifiers 52 and 53, so that a current proportional to signal I is supplied to impedance ZB'. In Fig. 6, given that resistors 57-60 are set to have the same value, and that the potentials at both ends of each of impedance elements 55 and 56 are Va and Vb or Vc and Vd, as illustrated, output voltage Ve of amplifier 54 is expressed as follows:

When this voltage V. is fed back to amplifier 51 and the gain for the feedback loop is sufficiently large, the power feeding is controlled to satisfy the following condition:

As a result, the output current IL with respect to load impedance ZB' becomes constant, thus maintaining the constant current characteristic. When a common-mode disturbance occurs in a load or on the subscriber's side, the impedance for the common mode as measured from the load is a parallel impedance of RM1 and RM2. This means that the subscriber line is terminated with the parallel impedance. In this case, since

use a particular circuit for the common-mode feedback, thus providing a power feeding circuit that is unlikely to be influenced by an external disturbance. Referring now to Fig. 7, the following explains a practical structure of the power feeding circuit of Fig. 6, when utilized in the circuit according to the first embodiment of Fig. 3. Signal nodes L, and L2 shown in Fig. 7 are respectively connected to resistors 22 and 23 of Fig. 3, and the power feeding circuit of Fig. 7 serves as current-controlled current sources 1 and 2 of Fig. 3. Current i (AC current) corresponding to the feed-back current of buffer amplifier 8 of Fig. 3 is supplied to signal line L3, through which DC current I flows, so that current i is added to DC current I. The current i is generated in a current detection circuit (Fig. 8). Accordingly, the current flowing through load impedance ZB' is H.(i + I). Although the power feeding circuit of Fig. 7 uses amplifiers 52-54, which are given, when needed, with the feedback resistance and the input resistance, it is substantially the same as the circuit shown in Fig. 6 used to explain the principle of this invention. In the above manner, the detection and supply of the current flowing through a load impedance ZB' would be carried out. The power feeding circuit of Fig. 7 can apply, by itself, to the subscriber line interface circuit according to the second embodiment of this invention (see Fig. 4). Fig. 8 illustrates a practical circuit for detecting current i flowing through feedback impedance MZB of buffer amplifier 8 and feeding back this current to the power feeding circuit of Fig. 7 via signal line Lc. An output circuit including a current amplifier circuit CA is provided on the output side of buffer amplifier 8. The output circuit supplies the output voltage of buffer amplifier 8 to buffer amplifier 31 through resistor 35, as well as to one end of impedance element 12 which is in the feedback loop. The output circuit further outputs from node To a current signal corresponding to the current flowing through impedance element 12 without impairing the aforementioned functions thereof. Current amplifier circuit CA comprises a pair of transistors Q, and Q2 and a pair of currentmirror circuits CM, and CM2. Current-mirror circuits CM, and CM2 provide, from the output side, those currents which are n times the currents respectively flowing through transistors Q, and Q2 (input side). The output circuit further includes a pair of transistors Q3 and Q4, a pair of diode-

buffer amplifier 8 is, and a. current source CS. Transistors Q,, Q3 and Q5 have their bases commonly coupled, and transistors Q2, Q4 and Q6 have their bases commonly coupled. Transistors Q3 and Q4 have their emitters coupled together and have their collectors coupled to source potentials Vp and VN, respectively.A voltage corresponding to the voltage produced at the output node of buffer amplifier 8 is produced at the connecting node between transistors Q3 and Q4, and is supplied to buffer amplifier 31 through resistor 35. Current source CS, diode-

series between source potentials VP and VN, and supply a bias potential to the bases of

coupled together and have their collectors respectively coupled to the inputs of current-mirror circuits CM, and CM2. One end of impedance element 12 is coupled to the connecting node between the emitters of transistors Q, and O2, The outputs of current-mirror circuits CM, and CM2 are commonly coupled to output current signal io to the inverting input node of amplifier 51 of the power feeding circuit from node To. When current i equal to the current flowing through impedance element 11 flows from impedance element 12 to the connecting node of the emitters of transistors Q, and Q2, current amplifier circuit CA draws the current io = n.i to node To. When current i is drawn from the connecting node between the emitters of transistors Q, and Q2, current amplifier circuit CA outputs current io = n-i from node To. In other words, when current i flowing through impedance ZT as measured from the subscriber's side, is supplied to current amplifier circuit CA that has a current ratio of n of current-mirror circuits CM, and CM2, current io = n-i is supplied from node To to amplifier 51 of the power feeding circuit as a control signal. The output circuit of Fig. 8 can also apply to the subscriber line interface circuit according to the second embodiment of this invention shown in Fig. 4. A subscriber line interface circuit according to the third embodiment of this invention will now be explained with reference to Fig. 9. In this embodiment, current i flowing through impedance element 11 provided on the input side of buffer amplifier 8 is detected at proximity of impedance element 11 by a voltage and is fed back to the control current source. The subscriber line interface circuit shown in Fig. 9 has buffer amplifier 8 and 101-110, impedance elements 11 and 12, adders 111-113, resistors 114 116, a capacitor 117 and a voltage source 118. Buffer amplifier 8 and impedance elements 11 and 12 in Fig. 9 have the same configuration as those shown in Fig. 3 or 4, except that impedance elements 11 and 12 in Fig. 9 have the same impedance NZT. The amplification factors of buffer amplifiers 101 and 102 are 1/10 and -10, respectively, and the amplification factors of buffer amplifiers 103, 105-107 and 110 are 1. The amplification factors of buffer amplifiers 104, 108 and 109 are Ao, A1 and -1, respectively. Resistors 114, 115 and 116 have resistances of R,, R2 and R3, respectively. The inverting and non-inverting input nodes of amplifier 101 are coupled to subscriber nodes L, and L2f respectively.Adder 111 is supplied with reception voltage VRX, and subtracts this voltage VRX from the output of amplifier 101 that is received through capacitor 117. The output of adder 111 is supplied to inverting amplifier 102, whose output is supplied to the inverting input node of buffer amplifier 8 through a series circuit of current detection resistor 114 and impedance element 11. Adder 112 adds reception voltage VRX and the output of buffer amplifier 102. The output of buffer amplifier 8 having the feedback impedance is input to buffer amplifier 103, and is added to the output of adder 112. The resultant voltage is output as transmission voltage VTX. The voltage drop caused in resistor 114 by current i is detected by buffer amplifier 104, amplified there, and is supplied to adder 1 13. The output node of buffer amplifier 109 is coupled to node L, through resistor 1 15.The input node of buffer amplifier 110 is coupled to node L2 through resistor 116. The voltage drop in resistor 115 is detected by buffer amplifier 105, and the voltage drop in resistor 116 is detected by buffer amplifier 106. The outputs of buffer amplifiers 105 and 106 are added in buffer amplifier 107, and the resultant output is supplied to adder 113. Adder 113 subtracts the output voltages of amplifier 107 and voltage source 118 from the output voltage of amplifier 104, and supplies the resultant voltage to the inverting input node of buffer amplifier 108. The output of buffer amplifier 108 is input to both of buffer amplifiers 109 and 110. Paying attention to amplification factors Ao and A, and letting is be the AC current flowing through the subscriber terminal, then we obtain

Letting A, be about 100, which is nearly an infinite value, we obtain

When a signal from the exchange is received, the output impedance of the subscriber line interface circuit as measured from subscriber nodes L, and L2 is obtained. Assuming that only a load of impedance ZB' is coupled between nodes L, and L2, then

From equations (26) and (27), we obtain

Now, letting R, be sufficiently small as compared with NZT, the approximation of the above equation will be given below:

Setting Ao/R1/(R2 + R3) = N and substituting equation (25) into the equation above yields

Thus,

Therefore, the output impedance as measured from nodes L, and L2 is

At this time, output signal VTX is expressed as:

Disregarding R1, the following equation will be obtained from equation (28):

Letting ZB = ZB' yields

When VRX = 0, input impedance ZIN can be obtained as:

and from equation (27), ZIN can be rewritten as:

Now, setting R, sufficiently small as compared with NZT, we obtain the following approximation:

impedance:

Transmission voltage VTX at this time is expressed as:

When the total impedance of the subscriber line interface circuit coupled to subscriber nodes L, and L2 is ZB' and the output signal from the subscriber terminal is VR, the following equation is derived from equation (29):

Substituting this equation into equation (6) and disregarding R1, we obtain

. Setting ZB = ZB' yields

Claims (10)

1. A subscriber line interface circuit, coupled to a subscriber terminal and an exchange, for coupling said subscriber terminal and said exchange, comprising: a pair of subscriber nodes for coupling said subscriber line interface circuit with a subscriber terminal through a subscriber line; a pair of reception nodes and a pair of transmission nodes, for coupling said subscriber line interface circuit with said exchange through a unilateral reception line and a unilateral transmission line; power feeding means for feeding a DC current-to said subscriber terminal through said subscriber nodes and for controlling said DC current; first adder means for adding a voltage between said pair of subscriber nodes and a voltage supplied between said pair of reception nodes; first impedance means having an impedance corresponding to a real-number multiplication of an impedance between said subscriber nodes, as observed from the side of said subscriber line and receiving an output voltage of said first adder means; inverting amplifier means which receives an output of said first impedance means; second impedance means having an impedance corresponding to a real-number multiplication of an impedance of said subscriber line and subscriber terminal, as observed from said subscriber nodes and inserted into a feedback path of said inverting amplifier means; feedback means for feeding a signal corresponding to a current flowing through said first impedance means, to said power feeding means as a control signal; and second adder means for adding an output voltage of said inverting amplifier means, an output voltage of said first adder means and a voltage supplied between said pair of reception nodes, and for supplying a resultant voltage between said pair of transmission nodes.

2. The circuit according to claim 1, wherein said feedback means includes direct detection means for detecting a current flowing through said first impedance means.

3. The circuit according to claim 2, wherein said direct detection means includes a resistor element coupled in series to said first impedance means, and potential difference detection means for detecting a voltage drop caused by said resistor element.

4. The circuit according to claim 1, wherein said feedback means includes indirect detection means for detecting a current flowing through said second impedance means, said current corresponding to a current flowing through said first impedance means.

5. The circuit according to claim 4, wherein said indirect detection means includes current generation means, provided on an output portion of said inverting amplifier means, for providing a current signal corresponding to said current flowing through said second impedance means.

6. A subscriber line interface circuit, coupled to a subscriber terminal and an exchange, for coupling said subscriber terminal and said exchange, comprising: a pair of subscriber nodes for coupling said subscriber line interface circuit with a subscriber terminal through a subscriber line; a pair of reception nodes and a pair of transmission nodes, for coupling said subscriber line interface circuit with said exchange through a unilateral reception line and a unilateral transmission line; power feeding means for feeding a DC current to said subscriber terminal through said subscriber nodes and for controlling said DC current; first adder means for adding a voltage between said pair of subscriber nodes and a voltage supplied between said pair of reception nodes; first impedance means having an impedance corresponding to a real-number multiplication of an impedance between said subscriber nodes, as observed from the side of said subscriber line and receiving an output voltage of said first adder means; inverting amplifier means which receives an output of said first impedance means; second impedance means having an impedance corresponding to a real-number multiplication of an impedance of said subscriber line and subscriber terminal, as observed from said subscriber nodes and inserted into a feedback path of said inverting amplifier means; feedback means for detecting a current flowing through said second impedance to provide a detection signal and feeding said detection signal to said power feeding means as a control signal; and second adder means for adding an output voltage of said inverting amplifier means, an output voltage of said first adder means and a voltage supplied between said pair of reception nodes, and for supplying a resultant voltage between said pair of transmission nodes.

7. The circuit according to claim 6, wherein said first adder means comprises one buffer amplifier having an ipverting input node coupled to one of said subscriber nodes and one of said reception nodes through resistors and having a non-inverting input node coupled to the other subscriber node through a resistor.

8. The circuit according to claim 6, wherein said second adder means is a weighting adder circuit comprising one buffer amplifier.

9. A subscriber line interface circuit, coupled to a subscriber terminal and an exchange, for coupling said subscriber terminal and said exchange, comprising: a pair of subscriber nodes L1, L2 for coupling said subscriber line interface circuit with a subscriber terminal through a subscriber line; a pair of reception nodes and a pair of transmission nodes, for coupling said subscriber line interface circuit to said exchange through a unilateral reception line and a unilateral transmission line; first means for adding a voltage Vo between said subscriber nodes L, and L2 and a reception voltage VRX; a load R1 + NZT to which a voltage obtained by said first means is applied; second means for amplifying said voltage obtained by said first means by a factor of NZB/(R1 + NZT); third means for subtracting VRx from a sum of said voltage Vo and said reception voltage VRX and for calculating a difference between the subtraction result and the amplified result to provide a transmission voltage VTX; fourth means for amplifying a potential difference that is said sum of said voltages Vo and VRX. which is divided by NZT and appears across a load R1, by a factor of Ao; fifth and sixth means for converting currents flowing through said subscriber nodes L, and L2 into voltages using loads R2 and R3, respectively; seventh means for adding voltages obtained by said fifth and sixth means; eighth means for adding a voltage obtained by said seventh means, a voltage obtained by said fourth means and a reference voltage for determining a DC power-feeding current and for amplifying a resultant voltage by a factor of A,; and ninth means for supplying a voltage obtained by said eighth means to said loads R2 and R3.

10. A subscriber line interface circuit, substantially as hereinbefore described with reference to the accompanying drawings.