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GB2174538A - Semiconductor package - Google Patents

Semiconductor package Download PDF

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Publication number
GB2174538A
GB2174538A GB08510434A GB8510434A GB2174538A GB 2174538 A GB2174538 A GB 2174538A GB 08510434 A GB08510434 A GB 08510434A GB 8510434 A GB8510434 A GB 8510434A GB 2174538 A GB2174538 A GB 2174538A
Authority
GB
United Kingdom
Prior art keywords
package
leadframe
die
section
ring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB08510434A
Other versions
GB8510434D0 (en
Inventor
Stanley Bracey
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to GB08510434A priority Critical patent/GB2174538A/en
Publication of GB8510434D0 publication Critical patent/GB8510434D0/en
Publication of GB2174538A publication Critical patent/GB2174538A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861Lead-frames fixed on or encapsulated in insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A package for a semiconductor die comprises a lead frame (4) fixed in an insulating frame (5), a die mounting section, and a cover. The die mounting section can incorporate a die attach pad which passes through the mounting section or one which is stuck to the mounting section by adhesive. The package may incorporate more than one lead frame. A heat sink may be provided to cool the die in operation. <IMAGE>

Description

SPECIFICATION D pack The present invention relates in general to the connection and packaging of semiconductor devices.
More particularly the invention relates to semiconductor packages that include an interconnect pattern or leadframe and a partthereofwhich may be used independently as a connection ring for semiconductor devices when mounted within a sub or main assembly without a total package.
The invention also includes novel techniques for thermal dissipation, and is aimed at packaging requirements needing thermal dissipation greater than can be achieved by simple plastic encapsulation, though in its simplest form can be used in low thermal dissipation cases.
Currently, packages are manufactured specifically to suit a particular application, either as a single stamping with leadframe and die attach pad for plastic encapsulation, or for mounting in a ceramic substrate that normally has a well where the die attach pad is located. Such an approach leads to several packages with common features, also the adding of additional coatings to the leadframe involves selectively plating or coating those areas at a relatively high cost.
With the high cost of tooling and the ever increasing range of packaging requirements brought about by the demands of industry and the continuing trends to increase the density of circuit per unit of silicon for integrated circuit die, leading to a wide range of lead counts from single numbers to several hundred, and the wide range of thermal dissipation requirements, package users are faced with a perplexing range of choice.
The specific aim of the invention is to provide a more flexible packaging system that aids the major semiconductor device manufacturer, the custom packaging house and the electronic sub assembly manufacturer and which lowers costs.
Primarily the package is divided into several constituant sections which normally would be separate until used, though the user may request sections pre-joined by the manufacturer.
These sections consist of a leadframe with or without a TAB bonding pattern at the inner end of the leadframe and suitable for TAB (a semiconductor connection method where a leadframe pattern is bonded to the die) andior wire bonding attachment to a die or multiplicity of die. It will be mounted or encapsulated in a ring of insulating material which will form part or all of the side wall of the package.
Ideally the ring would be of plastic or ceramic. The outer ends of the leadframe would be of sufficient strength to hold their form but would be capable of being formed in a direction up or down from the plane of the ring.
The leadframe would normally be manufactured by chemical or mechanical means from a suitably electrically conductive material.
The preferred, though not essential, method of manufactureforthe leadframe would be in continuous strips containing the leadframe pattern normally required on one of the sides of the package linked by a tie bar at the outer end, thus enabling additional plating or coating to be achieved by simple part dipping of the leadframe in a process bath.Exception to this would be where the inner end of the leadframe also contains the TAB pattern, when an inner tie bar is also desirable and/or where the outer ends of the leadframefollow a castellated package outline in which case it may be necessary to use more than one piece per side and carry out some preforming of the outer end of the lead during the production of this part of the package, this will also be the case if the leads are to emerge from the ring in a direction perpendicular to the plane of the ring.
It is preferable, but not essential, that within the initially formed leadframe part a means of alignment such as accurately placed jig holes are incorporated.
Following the manufacture of the leadframe, the parts as necessary would be arranged in a suitable tool for the desired insulating ring to be formed or attached to the leadframe and which becomes the wall in a total package.
This tool may act as a mould or forming tool for the ring material and may also remove unwanted parts of the leadframe, usually only the tie bar. The ideal finished part would consist of a total leadframe held in place by an insulating ring of plastic with the leadframe waste removed and plastic link bars suitably formed for ease of removal joining each of the rings to form a continuous strip containing a plurality thereof though with other materials leaving all or part of the leadframe tie bar may be preferable, for instance if the ring was formed of a ceramic material.
It is the preferred style of the invention that the ring should have a maximum thickness of .625mm and the leadframe a thickness of .1 25mm with the leadframe passing through the ring centrally between upper and lower surface and that in the case of a leadframe for wire bonding or separate TAB pattern bonding would have the lower half of the ring supporting fully the inner parts of the leadframe while above the leadframe would stop at least .375mm from the inner end ofthe leadframe. In the case of a leadframe with integral TAB pattern the ring would enclose the leadframe equally to give the inner dimension at least 0.5mm bigger than the semiconductor die in that direction. It is possible that this arrangement may also find application on its own to provide a removable bonding frame for a die mounted on a main assembly.
With the appearance of die with more than one row of bonding pads around their peripheral it would also be intended that a leadframe could be stacked on another. In this case the lower pation of the second ring from its inner surface would, in a preferred style, have a relatively thin projection to act as an insulator between the first and second or subsequent connections to the die. With the preferred dimensions it gives a level bond between leadframe and die surface, and for the second ring suitable height for bonds to go over the first set (outer on die) from inner die pads to outer package bond pads, likewise when TAB is used a similar situation would occur.
This first section of the package may, in addition to being combined with other sections of the package, be directly used to provide a leadframe bonding ring around a die mounted on a main assembly and gives very improced repairability to that assembly.
One exception exists to the foregoing description of the first section of the package and that is where the leadframe must emerge from the upper or lower surface of the ring, in which case the leadframe parts will be pre-formed to give the necessary bond areas or position of TAB pattern priortothe ring being formed or added to it so that they are located in the necessary position.
It is important to note that one leadframe may be capable of providing a wide variety of lead out configurations or footprints.
The second section of the package would be the part containing, where necessary, the normally electrically conductive die mounting pad. This part would normally be considered the package base but because the package leads may be formed in either direction, likewise the package will be mountable either way up. When thermal dissipation is low this ability is relatively unimportant but with high thermal dissipation it enables heat sink facilities to be either above or below the package.
This part will consist of, in its simplest form, an insulating plate of, for example, plastic in its preferred form, .25mm thick and around its peripheral may contain an adhesive strip which will bond it to the leadframe ring with suitable processing. Sometimes it would be desirable that this plate was formed integrally with the leadframe ring, except where an integral TAB pattern exists.
The next form will include as required one or several die bond areas consisting of an electrically conductive material which are arranged in the surface of the plate and normally level with its surface as required. ideally this would be ^.125mum thick. This plate could also be formed with the leadframe ring except where an integral TAB pattern exists with the leadframe. Such pads may also be adhesively attached to the surface of the plate. When this plate and the leadframe are formed together suitable tooling will enable a multiplicity of die pad arrangements to be combined with a comon leadframe, but this is not a preferred approach.
These pads may be fabricated by, for example, chemical or mechanical means ideally as a continuous strip linked by a suitable tie bar. Where a multiplicity of pads exist in a certain package it may need to compromise of more than one strip if plating or coating is required to the base material.
Where the pad is to be electrically attached to one of the leads of the leadframe a possible method of achieving this is by including, where possible, a projection from the pad which will emerge in line with the desired leads when this part and the leadframe are joined, and in the case of a continuous strip, processing may comprise part of the link to the tie bar. Alternatively, allowance in the die pad design enabling it to be connected to the particular lead within the package by wire bonding or other suitable means such as conductive epoxies, should be employed. Care should be taken in deciding where these link bars are to be removed after the pad has been joined or moulded into or on the plate.
The final form of this plate would be when high thermal dissipation is required. Here the die attach elements pass through the plate, again they would ideally be level with the upper surface of the plate where the die is to be mounted but this may not necessarily be true in multiple die packages where thickness variations of the die make it desirable to vary the height of the pads. On the lower surface the pads may be level with that surface or project. When projectiong they may be formed with fins or studs as necessary to enable, for instance, direct attachment to a PCB heat sink when this provides the base for the package or provides the heatsinking or means of attachment to additional heat sink when the package is inverted.Again the pads/thermal pillars may be formed as a continuous strip or strips, depending on number and application, by any suitable means such as chemical or mechanical methods and where electrical attachment is desired wuitable provision made as previously mentioned. Again except when an integral TAB pattern exists in the leadframe this may be formed integrally with the leadframe ring, though this approach is not preferred.
The final section of the package is the cover for the attached die. This will be a simple plate which may have raised sides that may also contain an adhesive ring which, with suitable processing, enables itto be attached to the leadframe ring. This may also be used in conjunction with the leadframe (section 1) in enclosing die mounted directly on a main assembly.
In combining the possible lead configurations that may be grouped together it is often necessary to consider where the lead, when it has been finally formed on the outer end, outside the ring, is required to be flush with the surface of the ring and other sections of the surface of the package. This may be achieved by forming in the leadframe ring, cover plate and die attach plate indents on the outer surfaces to accept the lead so formed.
This will give an advantage over many of the conventional packaging styles that have flush lead connections in that it is not rigidly held in the package material and can thus absorb effects caused by thermal mismatch between material. In all cases adhesive, joining or sealing layers can be included in the fabrication of a particular part to facilitate ease of joining and., when required, sealing the relative parts together.
The present invention is not specifically tied to a particular style of packaging, nor is it fixed in application to a particular outline being emminently suitable to all packaging lead out styles (footprints) whether pin out be from one or more sides of the package or perpendicular to the plane of the leadframe ring, nor is it specifically intended for packages where the lead outs are arranged in linear rows, castellated or circular lead configurations are also accommodated.
Embodiments of the invention will now be described solely by way of example and with reference to the accompanying drawings.
Figure 1 A simple two sided leadframe in a ring.
Figure 2 A two sided TAB leadframe in a ring.
Figure 3 Cross section of leadframe with two sided leads.
Figure 4 Cross section of two sided leadframe when TAB pattern is integral with leads.
Figure 5 Cross section of leadframe and ring with leads perpendicular to plane of ring.
Figure 6 Cross section of a two sided leadframe in ring when intended for stacking on another leadframe, which is also shown.
Figure 7 First style of forming castellated lead out and ring.
Figure 8 Alternative method of forming castellated leadout ring.
Figure 9 Simple second section of package. Figure 10 Second version of die attach plate.
Figure 11 Third version of die attach plate.
Figure 12a,b,c,d Some alternative profiles for die attach thermal dissipation parts.
Figure 13 The cover cross sections.
Figure 14 An assembled package.
Figure 15 Modifications to package when directly on a main assembly.
Detailed description of drawings Figure 1 shows a typical 2 sided leadframe and ring being manufactured in the preferred manner of two separate leaframe parts comprising 1 and 4 prior to separation, which are then encased by the ring 5 which is linked to a tie bar framework 3.
Accurate location of the leadframe parts is enabled by the jig holes 2 in the leadframe tie bar 1 which is removed after the leads 4 are encased in the ring.
Area 6 of the leadframe is where wire bonding or separate TAB interconnect leadframe will be bonded. The inner end of the leadframe 6 will normally be finished with a gold or silver layer while the outer end 4 would normally be tin/tin lead coated.
Figure 2 shows a similar arrangement to Figure 1 except that the TAB interconnect 7 has been incorporated into the main leadframe.
Figure 3 is a typical cross section of a leadframe and ring. Note the indent 8 to enable flush lead configuration, 9 is the bond area.
Figure 4 shows the proposed but not essential modification when the TAB pattern 10 is incorporated into the leadframe. Note there is no longer a step in the ring 11.
Figure 5 shows a cross section of one style of package where the pins 13 are perpendicular to the ring. Note that part of pin 12 progresses at an angle through the ring to the bond area 14.
Figure 6 shows a second layer leadframe and ring 15 in place on a first layer ring 16. Note the short protrusion 17 from the second ring giving protection against electrical shorts between the first and second layer connections.
Figure 7 shows a castellated pin out with a simple ring in plan and end view.
Figure 8 shows the preferred method of producing a castellated pin outline. Note that the varieties of final formation of the leads is also shown. 18 is an outward facing surface mounted. 19 is an insert formation and 20 is inward facing surface mounted, the latter being equivalent to a leadless chip carrier but with improved themal mismatch capabilities.
Figure 9 shows the simple part for the die mounting base when no thermal or electrical conductivities are required. 21 is the adhesive layer. 22 is the indent to accommodate a flush formed lead.
Figure 10 is as Figure 9 but where a simple electrically conductive die pad is present. 23 is contained, 24 may be fixed by adhesive.
Figure 11 is as Figure 10 but where high thermal dissipation is required from the die mounting area 25 through to the outside of the package 26.
Figure 12 a - d shows alternative cross sections of the die thermal pillar pads.
a is either in one or two parts b is in one piece c is a one ortwo part d is for attachment to an auxillary heat sink.
Figure 13 is the cross section of the third section of the package the optional cover, which may include an optical window 27.
Figure 14 shows a cross section of a two layer leadframe package and details the alternative lead configurations possible.
Figure 15 shows the leadframe and cover used within a main assembly 28.

Claims (14)

1. A package for semiconductor die which consists of several parts which includes a cover section, a leadframe section and a die mounting section and is constructed of a combination of electrically conductive and insulating parts.
2. A package as claimed in claim 1 except that the die mounting section is part of a main assembly to which the die and leadframe assembly are attached.
3. A package as claimed in claim 2 where the cover is not used.
4. A package as claimed in any of the preceding claims in which the leadframe incorporates a TAB interconnect pattern.
5. A package as claimed in any of the preceding claims in which an optical window is incorporated in the cover.
6. A package as claimed in any of the preceding claims formed to any pinout (footprint) option in its final state.
7. A package as claimed in any of the preceding claims where the die attach pad is stuck by adhesive to the die attach section of the package.
8. A package as claimed in any of the preceding claims where the die attach pad is incorporated into the die attach section insulating material.
9. A package as claimed in any of the preceding claims where the die attach pad passes through from die attach face to opposite face of the die attach section.
10. A package as claimed in claim 9 which contains a heat sink or means to attach additional heat sink mechanism on the outer surface.
11. A package as claimed in any of the preceding claims which incorporates more than one leadframe section.
12. A package as claimed in claim 11 wherethe leadframe section incorporates an insulating protection for connections to the die previously made to another leadframe section.
13. A package as claimed in any of the preceding claims where the leadframe section and the die attach section are formed as one piece without the need for attaching both by adhesive or other mechanism after being fabricated separately.
14. A package as hereinbefore substantially described with reference to the accompanying drawings and text.
GB08510434A 1985-04-24 1985-04-24 Semiconductor package Withdrawn GB2174538A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB08510434A GB2174538A (en) 1985-04-24 1985-04-24 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB08510434A GB2174538A (en) 1985-04-24 1985-04-24 Semiconductor package

Publications (2)

Publication Number Publication Date
GB8510434D0 GB8510434D0 (en) 1985-05-30
GB2174538A true GB2174538A (en) 1986-11-05

Family

ID=10578125

Family Applications (1)

Application Number Title Priority Date Filing Date
GB08510434A Withdrawn GB2174538A (en) 1985-04-24 1985-04-24 Semiconductor package

Country Status (1)

Country Link
GB (1) GB2174538A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2647958A1 (en) * 1989-05-30 1990-12-07 Thomson Composants Militaires Plastic housing for integrated circuit with staggered grids on two levels and method of manufacture
EP0474469A1 (en) * 1990-09-04 1992-03-11 Shinko Electric Industries Co. Ltd. Multi-layer lead frame for a semiconductor device
WO1995024733A1 (en) * 1994-03-11 1995-09-14 The Panda Project Prefabricated semiconductor chip carrier
EP0654821A3 (en) * 1993-11-23 1995-10-11 Motorola Inc Electronic device with coplanar heat sink and electrical contacts.
GB2293918A (en) * 1994-10-06 1996-04-10 Ibm Electronic circuit packaging
EP0681741A4 (en) * 1993-11-29 1996-06-05 Rogers Corp ENCLOSURE FOR AN ELECTRONIC CHIP CARRIER AND PRODUCTION METHOD.
US5821457A (en) * 1994-03-11 1998-10-13 The Panda Project Semiconductor die carrier having a dielectric epoxy between adjacent leads
US5824950A (en) * 1994-03-11 1998-10-20 The Panda Project Low profile semiconductor die carrier
US6078102A (en) * 1998-03-03 2000-06-20 Silicon Bandwidth, Inc. Semiconductor die package for mounting in horizontal and upright configurations
WO2003098666A3 (en) * 2002-05-22 2004-02-19 Infineon Technologies Ag High-frequency power semiconductor module with a hollow housing and method for the production thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4012766A (en) * 1973-08-28 1977-03-15 Western Digital Corporation Semiconductor package and method of manufacture thereof
GB1503136A (en) * 1975-08-01 1978-03-08 Owens Illinois Inc Semiconductor device assembly
GB1524776A (en) * 1976-07-30 1978-09-13 Amp Inc Integrated circuit package
GB2057757A (en) * 1979-08-30 1981-04-01 Burr Brown Res Corp Moulded lead frame dual in-line package and fabrication method therefor
GB2084796A (en) * 1980-09-17 1982-04-15 Hitachi Ltd Mounting and cooling arrangements for semiconductor devices
US4400870A (en) * 1980-10-06 1983-08-30 Texas Instruments Incorporated Method of hermetically encapsulating a semiconductor device by laser irradiation

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4012766A (en) * 1973-08-28 1977-03-15 Western Digital Corporation Semiconductor package and method of manufacture thereof
GB1503136A (en) * 1975-08-01 1978-03-08 Owens Illinois Inc Semiconductor device assembly
GB1524776A (en) * 1976-07-30 1978-09-13 Amp Inc Integrated circuit package
GB2057757A (en) * 1979-08-30 1981-04-01 Burr Brown Res Corp Moulded lead frame dual in-line package and fabrication method therefor
GB2084796A (en) * 1980-09-17 1982-04-15 Hitachi Ltd Mounting and cooling arrangements for semiconductor devices
US4400870A (en) * 1980-10-06 1983-08-30 Texas Instruments Incorporated Method of hermetically encapsulating a semiconductor device by laser irradiation

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2647958A1 (en) * 1989-05-30 1990-12-07 Thomson Composants Militaires Plastic housing for integrated circuit with staggered grids on two levels and method of manufacture
EP0474469A1 (en) * 1990-09-04 1992-03-11 Shinko Electric Industries Co. Ltd. Multi-layer lead frame for a semiconductor device
EP0654821A3 (en) * 1993-11-23 1995-10-11 Motorola Inc Electronic device with coplanar heat sink and electrical contacts.
EP0681741A4 (en) * 1993-11-29 1996-06-05 Rogers Corp ENCLOSURE FOR AN ELECTRONIC CHIP CARRIER AND PRODUCTION METHOD.
US5821457A (en) * 1994-03-11 1998-10-13 The Panda Project Semiconductor die carrier having a dielectric epoxy between adjacent leads
WO1995024733A1 (en) * 1994-03-11 1995-09-14 The Panda Project Prefabricated semiconductor chip carrier
US5819403A (en) * 1994-03-11 1998-10-13 The Panda Project Method of manufacturing a semiconductor chip carrier
US5824950A (en) * 1994-03-11 1998-10-20 The Panda Project Low profile semiconductor die carrier
US6339191B1 (en) 1994-03-11 2002-01-15 Silicon Bandwidth Inc. Prefabricated semiconductor chip carrier
US6828511B2 (en) 1994-03-11 2004-12-07 Silicon Bandwidth Inc. Prefabricated semiconductor chip carrier
US6977432B2 (en) 1994-03-11 2005-12-20 Quantum Leap Packaging, Inc. Prefabricated semiconductor chip carrier
GB2293918A (en) * 1994-10-06 1996-04-10 Ibm Electronic circuit packaging
US6078102A (en) * 1998-03-03 2000-06-20 Silicon Bandwidth, Inc. Semiconductor die package for mounting in horizontal and upright configurations
WO2003098666A3 (en) * 2002-05-22 2004-02-19 Infineon Technologies Ag High-frequency power semiconductor module with a hollow housing and method for the production thereof
US7417198B2 (en) 2002-05-22 2008-08-26 Infineon Technologies Ag Radiofrequency power semiconductor module with cavity housing, and method for producing it

Also Published As

Publication number Publication date
GB8510434D0 (en) 1985-05-30

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