GB2160375A - Phase controlled oscillator and a data demodulator including said oscillator - Google Patents

Abstract

A phase controlled oscillator which is particularly useful as a clock signal generator for a data demodulator, and is suitable for implementing in CMOS technology. The oscillator comprises an EPROM (20), storing a plurality of sets of n regularly spaced voltage samples, each set corresponding to a different relative phase of the oscillator output. In operation, when a sequence of addresses corresponding to a set of samples is applied at n times the data to the EPROM (20), the digital values of the voltage samples are applied sequentially to a digital-to-analogue converter (22), whose output is applied to a low pass filter (24), which produces a sine wave of constant frequency and predetermined phase. The phase is changed by selecting another set of digital voltage samples. As the change of phase is effected digitally, then it can be accomplished substantially instantaneously. The phase controlled oscillator is used in a PLL for a fast acquisition data demodulator. <IMAGE>

Description

SPECIFICATION Phase Controlled Oscillator and a Data Demodulator Including said Oscillator The present invention relates to a phase controlled oscillator and to a data demodulator including the phase controlled oscillator.

In a data demodulator it is necessary to lock the frequency and phase of a receiver clock oscillator with the frequency and phase of the transmitter clock. This locking operation has to be carried out quickly so that the demodulator can achieve fast acquisition. Presently known demodulators require clocks which are locked to the received data by means of phase locked loops. In the prior art it is known to have phase locked loops which include a wideband voltage controlled oscillator, the frequency of which is controlled in order to adjust the phase. A disadvantage of this method is that in order to achieve fast acquisition, it is necessary to correct the clock frequency before achieving phase locking. This tuning technique is expensive to implement and has a poor medium to long term stability.It is also known to provide an oscillator whose maximum frequency is a large multiple of the data rate, the data rate may be for example of the order of 72k bitsisecond in a practical application such as cordless telephones. Oscillators having such a high fundamental frequency do not lend themselves to integration using CMOS techniques.

An object of the present invention is to provide a high stability, variable phase oscillator, which is capable of being implemented as an integrated circuit.

According to one aspect of the present invention there is provided a phase controlled oscillator in which an analogue waveform of predetermined relative phase is regenerated from a set of n (where n is 2 or more) periodic regularly spaced, digitally stored voltage samples, the oscillator comprising digital data storage means storing a plurality of sets of n periodic, regularly spaced, digitally stored voltage samples, each set corresponding to a different relative phase of the analogue waveform, and means for applying a sequence of addresses corresponding to one set of the voltage samples to the storage means at n times the frequency of the analogue waveform.

In an embodiment of the present invention the sets of digital samples are used to generate voltages which in turn are used to produce a clock waveform. By keeping the relative instants of sampling constant, then the phase of the produced clock waveform can be changed by selecting a suitable set of digital samples. The sampling instants are determined by a stable master oscillator, which runs at a frequency n times higher than the required clock frequency, where for example n may equal 4. Thus the master oscillator and other components lend themselves to fabrication as an integrated circuit in CMOS technology. If the data rate should be altered, the master oscillator frequency should be changed also, so that the ratio of the master clock oscillator frequency to the receiver clock frequency is constant.

As the phase shift is effected digitally, then each phase change can be effected within one sample period, which enables fast acquisition to be achieved.

A low pass filter may be coupled to the output of a digital-to-analogue converter to regenerate the phase demodulator reference clock signal. This is in contrast to known phase locked loop circuits in which a low pass filter is connected between a phase detector (or comparator) and a control input of the voltage controlled oscillator. In this latter position the low pass filter causes a loop delay, which leads to a long settling time and hence detracts from the required fast acquisition.

According to another aspect of the present invention, there is provided a data demodulator circuit including a phase controlled oscillator comprising digital data storage means storing a plurality of sets of n (where n is 2 or more) periodic, regularly spaced, digitally stored voltage samples, each set corresponding to a different relative phase of an analogue waveform, means for applying a sequence of addresses corresponding to one set of the voltage samples to the storage means at n times the frequency of the analogue waveform, means for regenerating the analogue waveform of selected relative phase from the sequence of digital values read.outfrom the storage means, hard limiting means for limiting the analogue waveform, a data recovery circuit having a clock input coupled to an output of the hard limiting means, a phase comparator having inputs for receiving the recovered data and the hard limited analogue waveform and an output for a phase correction signal, and means for producing a phase correction by generating a new sequence of addresses corresponding to another set of said digitally stored voltage samples.

The present invention will now be described, by way of example, with reference to the accompanying drawings, wherein: Figure 1 is a timing diagram of an arbitrary reference clock signal, Figure 2 is a timing diagram of a master clock oscillator output, Figure 3A, 3B and 3C are diagrams showing the generation from different sets of four digital samples of sine waves of the same frequency but different relative phase, the sine wave of Figure 3A has a relative phase of 1 , that of Figure 3B has a relative phase of 600 and that of Figure 3C has a relative phase of 1500, Figure 4 is a block schematic circuit diagram of a phase controlled oscillator, and Figure 5 is a block schematic diagram of a data receiver, which diagram shows in greater detail a clock generator for a fast acquisition demodulator.

Referring initially to Figures 1 to 3 of the drawings, the oscillator made in accordance with the present invention is intended to produce an analogue waveform, for example a sine wave, of substantially constant frequency but of any desired phase by constructing the waveform from a plurality of regularly spaced voltage samples in one cycle of the reference clock signal shown in Figure 1. At least two samples are required and, in the present embodiment, four samples will be used. In order to produce a set of sine waves having a relative phase shift of 10 between one set and the next, then it is necessary to provide 360 sets of four regularly spaced voltage samples, and to select the particular set at will.The samples in each set correspond to the quarter points in the waveform to be produced, for example 0 , 90 , 1800 and 270 , or 15 , 1050, 1950 and 2850.

To generate a sine wave, the samples have to be produced at a frequency four times that of the sine wave being produced. This is done using a master, crystal controlled oscillator, whose output is of constant frequency and phase. The actual output of the master oscillator is a square wave but as the leading edges are used, only these have been shown in Figure 2.

In order to illustrate this method of generating a phase controlled signal, reference is made to Figures 3A to 3C which show the voltage samples in broken lines, the sine waves in dotted lines and the hard limited sine waves in continuous lines. In each of these Figures the abscissa represents time Tin arbitrary units and the ordinate represents the amplitude A which is in arbitrary units ranging from -100 to +100. By comparing Figures 3A, 3B and 3C with each other, it will be noted that the sampling intervals are constant, but the amplitudes of the samples differ. However, because the relative phase shift between Figures 3B and 3C is 90 , it will be noted that the voltage samples of corresponding amplitude have moved one place to the left in Figure 3C.

For the sake of completeness, a tabular summary is given below of the amplitudes of the voltage samples in a set to generate sine waves having a number of different relative phase shifts with respect to the datum (0 ).

Relative Phase Shift Sample No. 10 200 400 600 1050 1500 2050 305o 1 1.67 9.17 64.17 86.67 96.67 50.00 -41.67 -81.67 2 100.00 93.33 76.67 50.00 -25.00 -86.67 -90.00 57.50 3 -1.67 -9.17 -64.17 -86.67 -96.67 -50.00 41.67 81.67 4 -100.00 -93.33 -76.67 -50.00 25.00 86.67 90.00 ~57.50 The sine waves shown in Figures 3A to 3C are derived by applying the voltage samples of each set successively to a low pass filter which yields an analogue signal with a defined frequency and phase. The reference clock signal is then generated by hard limiting the analogue signal. In a phase demodulator it is the timing of the zero crossings which are of interest, and the relative shifts can be seen clearly by comparing Figures 3A, 3B and 3C with each other.

Figure 4 is a block schematic circuit diagram of a phase controlled oscillator which comprises a look-up table in the form of an electrically programmable read only memory (EPROM) 20, which stores the sets of four voltage samples as digital values. In effect, the EPROM 20 acts as a look-up table. The addressing of the EPROM 20 is controlled by an address pointer 18 which, on an input 10, receives a signal indicative of the relative phase of the oscillations to be produced, which signal will be referred to as the index. A master crystal oscillator 12, having an output frequency four times that of the oscillator output frequency, is connected to a counter 14, which supplies sequentially the base address to another input 16 of the address pointer 18. The address pointer 18, in response to the index signal, produces the sequence of four addresses which are applied in turn to the EPROM 20.The digital values of the set of voltage samples are applied to a digital-to-analogue converter 22, to produce the voltage samples shown in broken lines in Figure 3A to 3C, which are applied to a low pass filter 24, having selected time and frequency domain characteristics, to produce a sine wave as shown in dotted lines in Figures 3A to 3C by interpolation. It will be appreciated from the foregoing description that by changing the index, a new set of digital values is read out from the EPROM 20, and is used to produce a sine wave of the same frequency but of different phase. A change of phase can be effected rapidly, within one cycle of the phase demodulator clock, merely by changing the index applied to the input 10.

Figure 5 illustrates a data receiver including the phase controlled oscillator shown in Figure 4. The data receiver includes an r.f. stage 30, which is coupled to a data recovery circuit 32, which is able to recover the data signal in the received signal. The recovered data signal is applied to an input 34 of a fast phase comparator 36, where its phase is compared to the phase of the clock signal derived from a hard limiter 40, whose input is connected to the low pass filter 24, and whose output is connected to an input 38 of the comparator 36. The data recovery circuit 32 and the phase comparator 36 may use the techniques disclosed in British Patent Specification 2 124 840 A (PHB 32891), details of which are incorporated by way of reference.

A phase correction signal derived from the comparator 36 is applied to an analogue-to-digital converter 42. The digital representation of the phase correction signal is scaled appropriately in value and applied to an accumulator 44, which stores the relative phase correction being applied as the index to the input 10 of the address pointer 18. The phase correction signal is an indication of the correction which has been noted and, as an example, the phase correction signal may be 10 . When digitised, a fraction of this value, up to a maximum of the whole value, is added to the currently held value, say 139 in the accumulator 44 to produce a new index.Thus if this fraction is, for example, one half, then with the values quoted the new index will be indicative of a relative phase of 18% The fraction actually used in a given receiver will be determined by considerations of stability and speed.

The remainder of the circuit is as described with reference to Figure 4, and in the interest of brevity the description will not be repeated.

The output of the hard limiter 40 is applied as the clock signal to the data recovery circuit 32, in order to recover the received data which is applied to an output terminal 46.

If the data rate of the transmitted signal is changed, then the master clock frequency has to be altered to maintain the same ratio with the reference clock frequency.

Unlike a conventional phase locked loop, in which the loop filter is connected between the phase comparator and the voltage controlled oscillator, the low pass filter 24 is connected after the devices for producing the voltage samples which are used to produce the phase controlled sine wave. This means the oscillator loop can operate much faster and typically has a time constant equivalent to one bit period or less.

The oscillator circuit, in accordance with the present invention, can be readily implemented in CMOS technology because the frequencies, including that of the master oscillator, are sufficiently low for this technology to be used.

Claims (6)

1. A phase controlled oscillator in which an analogue waveform of predetermined relative phase is regenerated from a set of n (where n is 2 or more) periodic, regularly spaced, digitally stored voltage samples, the oscillator comprising digital data storage means storing a plurality of sets of n periodic, regularly spaced, digitally stored voltage samples, each set corresponding to a different relative phase of the analogue waveform, and means for applying a sequence of addresses corresponding to one set of the voltage samples to the storage means at n times the frequency of the analogue waveform.

2. An oscillator as claimed in Claim 1, further comprising a digital-to-analogue converter coupled to the output of the storage means to produce analogue equivalents to the digitally stored voltage samples, and means to integrate said analogue equivalents to produce the analogue waveform.

3. A phase controlled oscillator constructed and arranged to operate substantially as hereinbefore described with reference to and as shown in Figures 1 to 4 of the accompanying drawings.

4. A data demodulator circuit including a phase controlled oscillator, comprising digital data storage means storing a plurality of sets of n (where n is 2 or more) periodic, regularly spaced, digitally stored voltage samples, each set corresponding to a different relative phase of an analogue waveform, means for applying a sequence of addresses corresponding to one set of voltage samples to the storage means at n times the frequency of the analogue waveform, means for regenerating the analogue waveform of selected relative phase from the sequence of digital values read-out from the storage means, hard limiting means for limiting the analogue waveform, a data recovery circuit having a clock input coupled to an output of the hard limiting means, a phase comparator having inputs for receiving the recovered data and the hard limited analogue waveform and an output for a phase correction signal, and means for producing a phase correction by generating a new sequence of addresses corresponding to another set of said digitally stored voltage samples.

5. A circuit as claimed in Claim 4, wherein the means for generating the analogue waveform comprises a digital-to-analogue converter for producing analogue voltage samples from the digital values and a low pass filter having an input connected to the digital-to-analogue converter and an output connected to the hard limiting means.

6. A data demodulator circuit constructed and arranged to operate substantially as hereinbefore described with reference to and as shown in Figure 5 of the accompanying drawings.