GB2160061A - Solid state imaging apparatus - Google Patents

Abstract

Solid state imaging apparatus comprising a charge-coupled device having a plurality of photosites 10 and a transport shift register 15 includes exposure control gate 13, and sink diode 14 for controlling the integration time of the photosites to be a constant selected as desired independent of the exposure period. The charge-coupled device may include a charge well 11, between each photosite and the corresponding section of the transport shift register, the constant integration time being provided by only allowing charge to build up in the charge wells after an initial period of time during each scan period. The required initial exposure control period is determined by means of counters (20, 26; Figure 3). The imaging apparatus is useful in telcines which may be run according to various T.V. Line standards. <IMAGE>

Description

SPECIFICATION Solid state imaging apparatus This invention relates to exposure control for solid state imaging apparatus comprising a charge-coupled line or area array sensor and circuitry connected to the sensor to extract a signal representing the incident light intensity over the sensor.

Such apparatus is used in telecines, that is equipment for generating a video signal from cinematographic film. Papers on the principles of operation of charge-coupled devices and their use in image sensing are reproduced in Fairchild CCD Imaging and Signal Processing Product Catalogue, published 1981 by Electronic 2000 for Fairchild CCD Imaging, 4001 Miranda Avenue, Palo Alto, California 94304, United States of America.

One particular problem with such solid state imaging apparatus is to accommodate changes in the overall level of incident illumination, namely to provide a means of controlling the exposure. Exposure control for line array telecines presents different problems to those experienced with either flying spot or cathode ray tube telecines. The problems are basically due to the fact that the line array charge-coupled device (CCD) cannot handle any condition involving exposure levels above its saturation level. Any over-exposure exhibits itself as what is termed "blooming". Blooming occurs when the size of the photo-electrically generated charge packets is too large to be accommodated by the shift register wells of the device. Overloaded wells overflow into adjacent wells which thereby receive information which does not originate from their associated photosites.This has disastrous results on the output picture.

There are two known techniques for overcoming this, but each has its own limitations. The first method uses a neutral density filter wheel or wedge which is inserted in the light path so as to increase or decrease the amount of light falling on the CCD array. The disadvantage of this system is its slow operation due to the mechanical inertia of the disc and its associated drive components, which effectively rules out this form of light control in applications which involve any form of pre-programming. Ideally, in any pre-programme operation all corrections should be completed in a frame blanking period. Since the neutral density filter typically takes several frames to complete a desired correction, the effect of having the filter will be observable in operation.

In the second method a fixed neutral density filter is used such that under the worst expected conditions the array can never be overexposed, thus eliminating the blooming effect. If this is employed then the exposure control becomes a gain control in the video processing channel connected to the output of the CCD array. This eliminates the response speed defect but does, in fact, mean that under a large variety of film speed conditions the array is not operating near its optimum light input level, and hence could give rise to increased noise level at the telecine output.

Another problem with solid state imaging apparatus is the effect of variations in the scan period on the amplitude of the output of the CCD.

In essence, a CCD line array consists of a line of light-sensitive photosites, typically 1024 of them.

These are exposed to light for a period of time during which they convert the light energy into "packets" of charge under each photosite. At the end of this period, normally referred to as the scan period, these charge packets are transferred to a shift register, known as the transport register, and clocked along the shift register to the output, where each charge packet is individually converted to a voltage signal and subsequently amplified.

Due to this method of operation, the minimum scan period is the shift register clock period multiplied by the number of elements in the shift register (typically about 50 Fas). When a CCD array is used in a continuous-motion telecine system this means that the maximum film speed is related to the number of lines of information required per film frame (dictated by the line standard of the T.V.

system employed) and the time that one frame takes to pass over the CCD array.

It will be appreciated that not all film is run such that the speed of the film passing the CCD allows the minimum scan period to be met precisely. That is, if the film speed is too high then not enough line information is read off the film, and if the film speed is too low then too many lines are read from the film to satisfy the T.V. line standard. Hence there is a requirement to control the rate at which line scans are requested at the sensor. However, if the line period (hence the time per line) varies, the output level varies due to the fact that the sensor is subject to a longer exposure period (normally referred to as the integration time).

Figure 1 shows at (a) to (d) various waveforms illustrating the operation of a conventional CCD image sensor. At (a) are shown a series of scan request pulses which are assumed to occur at intervals which are equal to the minimum scan period (MSP), namely the time taken to unload the transport register. The integration time (IT) available for the photosites is also shown. The pulse train output from the CCD will depend on the light falling on the array but will typically take the form shown at (b).

If for any reason the frequency of scan request pulses is reduced, then the integration time is correspondingly increased. As shown at (c), the scan period is doubled and the integration time is correspondingly increased, so that the CCD output shown at (d) is substantially doubled in amplitude.

We have appreciated that if the exposure could be controlled such that the integration time is constant independent of the exposure period then the CCD output would be constant independently of the scan request period.

This control may be achieved by adjustment of the exposure control voltage as shown in Figures 1e to g. Since the device is clocked regularly, the integration time may be defined as a number of clock cycles, and counting techniques may be em ployed to control this period. It will be appreciated that the control of integration time should also obviate the problem of blooming.

Exposure control in accordance with this invention may be achieved using a modified charge-coupled device which includes a charge well between each photosite and the corresponding section of the transport register. Data is moved along the transport register by the alternate application of voltages V1 and V2 at the scan clock rate. However, the charge built up on the photosites is not transferred directly into the transport register as is conventional. Instead of the usual single transfer gate, two transfer gates are provided. The charge well is dependent upon the voltage applied to the transfer gates such as to allow charge to build up in the charge well under the photosites or not. So as to provide a constant integration time, charge is only allowed to build up after an initial period of time during the scan period.

Figure 2 shows, schematically, the layout of part of a CCD for use in accordance with the invention.

Charge generated at each photosite 10 is transferred via photogate 11. A well is created under the photogate 11 by voltages which exist on both transfer gate 12 and an exposure control gate 13 effectively in parallel with the transfer gate. The capacity of the well can be controlled solely by the potential of the exposure gate with any surplus charge flowing into sink diode 14.

If, in operation, the voltage on the exposure gate is controlled so that it only reaches a more negative level than the photogate voltage for a fixed period before completion of the transfer of charge to the transport register 15 then that fixed period is equal to the integration time and may be selected as desired.

In other words, the output of the CCD may be controlled to take account of variations in incident light level by appropriate selection of the integration time. The integration time should, of course, be selected to be equal to or less than the minimum scan period.

Figure 3 shows a circuit used to drive the CCD array of Figure 2. The circuit includes an Up counter 20 which is loaded with data corresponding to the number of scan clock pulses required for the desired integration time at the end of the scan request pulse. The scan clock pulses are (or are derived from) the pulses used to drive the transport shift register in the CCD. The data is loaded negatively, in that the counter is loaded with the difference between its maximum count and the number of scan pulses required for the integrating time.

The counter 20 then counts up at the scan clock rate until the next scan request pulse, when the data is reloaded and the count cycle is repeated.

During this count cycle, after the number of clocks corresponding to the integration time, a pulse is output on its 'CARRY OUT' line to a latch control circuit 22. This enabling pulse, together with the next scan request pulse, is used to generate a 'Latch control' pulse to activate a latch circuit 24.

At the next scan request pulse, the count in counter 20 will represent the excess of the interval between consecutive scan request pulses over the desired integration time, i.e., the time for which the CCD must be disabled to give correct exposure.

The latch 24 passes the count at the time the next scan request pulse is present as a preload data value to a down counter 26. This counter 26 is loaded in response to a pulse derived from the scan request pulse, and counts down at scan clock rate to derive the end of an exposure control pulse.

An exposure control pulse generator 28 creates the required exposure control pulse from a start pulse, derived elsewhere (but timed accurately to the scan request pulse) and the end pulse derived from the 'CARRY OUT' of the down counter 26.

The integration period then starts at the end of the exposure control pulse and continues until the next scan request pulse.

This may be more readily seen from the waveforms in Figure 4. At (a) are shown the scan request pulses and at (b) are indicated the scan clock pulses, at a much higher frequency. The Up counter 20 provides a carry out pulse as shown at (c) after the integration time TINT. The latch control output is shown at (d). The down counter 26 counts for the residue of the scan period so as to provide pulses as at (e) which precede the next scan request pulse by the desired integration time.

The exposure start pulses are shown at (f) and the exposure pulses generated by the circuit of Figure 3 are shown at (g).

The exposure pulses are applied to the second transfer gate so as to clear the contents of the charge well and permit subsequent integration for the correct integration time.

The system illustrated works maintaining a constant integration time for repetition rates of scan request which are in excess of the minimum scan rate provided that the two counters 20 and 26 count enough 'bits' to cover the scan repetition period in terms of the number of scan clocks. if the maximum period for scan request pulses is equivalent to 2048 scan clocks then the two counters should have a capability of counting to at least 2050, but preferably higher, e.g. 4096.

Claims (4)

1. Solid state imaging apparatus comprising a charge-coupled device having a plurality of photosites and a transport shift register, scan request means for generating scan request pulses at a frequency representative of the desired scan rate, clock means for generating scan clock pulses to drive the transport shift register, and control means for applying control voltages to the chargecoupled device, and wherein the control means comprises counter means for counting count pulses derived from the clock means and for enabling the charge-coupled device in response thereto to permit integration of the output of the photosites for a predetermined number of count pulses whereby the integration time is controlled at a desired value.

2. Apparatus according to claim 1, in which the charge-coupled device includes a charge well be tween each photosite and the corresponding section of the transport shift register, the desired integration time being provided by only allowing charge to build up in the charge wells after an initial period of time during each scan period.

3. Apparatus according to claim 2, in which charge wells are created by voltages on transfer gates between photogates for the photosites and the transport shift register and on exposure control gates in parallel with the transfer gates, the capacity of the wells being controlled by the potential of the exposure gate with any surplus charge flowing into a sink diode and wherein the voltage on the exposure gate is controlled so that it only reaches a more negative level than the photogate voltage for a fixed period before completion of the transfer of charge to the transport shift register.

4. Apparatus according to claim 1, in which the counter means comprises a first counter for counting count pulses to produce a count representating the difference between the interval between successive scan request pulses and the desired integration time, and a second counter for counting count pulses for a duration dependent upon the output of the first counter to define a delay period before integration commences.