GB2036345A

GB2036345A - Digital exposure control system for a camera

Info

Publication number: GB2036345A
Application number: GB7847873A
Authority: GB
Original assignee: Canon Inc
Current assignee: Canon Inc
Priority date: 1978-12-09
Filing date: 1978-12-09
Publication date: 1980-06-25
Also published as: GB2036345B

Abstract

The system has a first counter (CT1 Fig. 13 not shown) for storage of a digital shutter-time signal and a second counter (CT2) for producing pulses for sequence control. When self-timer operation is required, pulses from the last bit of the second counter (CT2) are gated into the clock pulse input (CP) of the first counter (CT1) so that the two counters are in effect arranged in series to allow a relatively long self-timer period to be determined. Once timed, the two counters revert to their normal operation for exposure control. The control system may operate in a diaphragm-priority automatic exposure mode, in which case an analog photometric measurement is made and converted to a digital shutter time value in the first counter (CT1). If a flash gun is used, the flash duration is controlled photoelectrically. However if the storage capacitor is not fully charged, a daylight exposure is automatically selected upon shutter release, a check current is fed to an electromagnet for 8 ms to test battery potential. If too low (or if the film is not wound on) release is prevented.

Description

SPECIFICATION Digital exposure control system for a camera This invention relates to a digital control system for a camera and in particular -- but not exclusively - to a control system which may cause an associated camera to effect automatic exposures in a diaphragm-priority mode, either with or without a self-timer operation. The invention extends to a camera incorporating such a digital control system.

In known control systems especially for single-lens reflex cameras which use digital control for diaphragm-priority automatic exposures, shutter time information is obtained as a result of analog computation on a light value measurement and on other set photographic information. This is converted to a digital signal as shutter time information, which is stored and expanded to real time in response to operation of the camera shutter release. The shutter is then controlled to be open for the real time period assessed.

Such a digital control system for a camera makes possible the automation, reduction in size and enhancement of the accuracy of the camera incorporating the system. However, in addition to an enhancement of the accuracy, the cost of the camera must also be lowered.

A camera using a digital control system as just-described has been designed with a counter arranged to perform digital sequence control over various parts of the camera and another counter to carry out the analog-to-digital conversion for the photometric shutter-time computation. A reduction in the number of steps in these counters can greatly contribute to a reduction in cost. Digital electronic cameras in general use a plurality of integrated circuits (ICs) and the cost of the ICs falls as the area of the IC chips is made smaller. Accordingly, in order to lower the cost, the number of gates must be reduced, even by one. Each step of a counter requires about 10 gates and a reduction in the number of counter steps, therefore, greatly contributes to a reduction in cost.

In a camera control system, it is only a self-timer which requires a long time period, excepting unusually long time-exposures which are not commonly found on cameras. If a counter in a digital control system is especially to be arranged for self-timer control, this counter must have many stages including about 20 stages just for the self-timer operation. The provision of a self-timer has thus been a great obstacle to cost reduction in a digital control system.

According to this invention, there is provided a digital control system for a camera, comprising: a first counter in which may be stored digital information indicative of a required shutter time; a second counter arranged to generate pulses for the sequence control of the control system; first switch means to initiate operation of a control sequence; second switch means to allow selection ofa particular operational mode of the control system; signal generating means responsive to the operation of the first and second switch means, to produce either a shutter release signal on operation of only the first switch means or a timer signal on operation of the first and second switch means; gate means to transfer pulses from the second counter to the first counter for counting therein on production of the timer signal by the signal generating means;; means responsive to a preset count in the first counter then to cause the cessation of the timer signal and the production of the shutter release signal; and shutter time means responsive to the shutter release signal to cause storage in the first counter of the information indicative of the required shutter time, whereafter an output is provided to open the camera shutter for a period dependent upon the stored information.

Preferably a clock pulse source supplies pulses to a pulse input of the second counter which serves successively to divide the frequency of the clock pulse source, whereby a plurality of pulse outputs of different frequencies is available from the successive bits of the second counter.

It will be appreciated that in the control system of this invention, two digital counters are provided, the first of which is normally associated with shutter time information storage -- including the production of digital shutter time information when operating in an automatic-exposure diaphragm priority mode - and the second of which normally provides pulses for sequence control of the control system as a whole. However, when set to the self-timer mode, the first and second counters together serve to determine the self-timer period, and after the lapse thereof, the counters revert to their normal operation for an exposure to be made.By connecting the pulse input of the first counter through the said gate means to the lowest-frequency output of the second counter in the self-timer mode, the two counters are in effect arranged in series and a relatively long time interval can be determined thereby, even though neither counter individually could be used for determining a sufficiently long delay time for self-timer operation.

The shutter time means may select a pulse output from the second counter dependent upon the stored value in the first counter, and the said output for opening the shutter allows the shutter to remain open for a preset number of pulses from the selected output of the second counter. The said output may drive a first electromagnet for association with the camera shutter, thereby to release the shutter for opening movement, and a second electromagnet for association with the camera shutter at the end of the shutter time period, to effect closing movement of the shutter.The first switch means preferably comprises a release for the camera, and may be associated with further switch means which further switch means is automatically operated prior to operation of the first switch means on actuating the camera release, the further switch means serving to allow light measurement to be effected without generating the shutter release signal. The second switch means may serve to set the control system in a self-timer mode, whereby the shutter release signal is not generated until after the lapse of a predetermined self-timer interval.

The stored information in the first counter can be generated directly by means of a manuallyoperable shutter speed control. Alternatively, the stored information can be generated indirectly, by computation on the amount of light received from an object to be photographed, also taking into account film sensitivity and selected lens aperture of a camera used with the control system.

Further gate means can be provided to apply a re-setting input to the first counter, the further gate means being arranged to reset the first counter when the second switch is operated and to release the first counter reset when the first switch is operated.

Preferably, shutter time correction means are provided to delay the commencement of counting of pulses from the selected output of the second counter but following the production of the output allowing the camera shutter to open.

The control system may be arranged automatically to check that sufficient battery power is available to perform an exposure operation, and to inhibit operation if insufficient power is available. For example, current may be passed through a shutter-controlling electromagnet for a relatively short period prior to release proper, and only if sufficient current passes through the electromagnet is the exposure operation allowed to proceed.

It is preferred for the control system to include a flash circuit adapted for use with an electronic flash gun, which circuit automatically causes information indicative of a suitable shutter time for flash photography to be stored in the first counter on production of the shutter release signal when the circuit senses that an associated flash gun is charged ready for operation.

The control system may automatically set itself for a flash exposure if the flash circuit senses that an associated flash gun is charged up to the time at which the release signal is generated, but if prior to the production of the release signal the flash circuit has not detected the flash gun charge, subsequent detection is ignored until an exposure operation is completed.

This invention extends to a camera whenever incorporating a digital control system as described above.

By way of example only, one specific embodiment of a camera incorporating a control system according to this invention will now be described, reference being made to the accompanying drawings, in which: Figures 1 a and 1 b together show a circuit diagram of an exposure control circuit for a camera according to this invention; Figure 2 is an exploded view of the inner structural arrangement of a camera to be equipped with the circuitry shown in Figures 1 a and 1 b; Figure 3 is a circuit diagram of a flash device for mounting on the camera shown in Figures 1 a, 1 b and 2; and Figure 4 is a timing chart for various elements shown in the circuitry of Figures 1 a and 1 b.

In Figure 1, which shows the exposure control circuitry for a diaphragm-priority-type of single-lens reflex camera of this invention, various parts are enclosed within dotted lines. Part A shows a photometric circuit, part B an exposure computing circuit, part C an exposure display circuit, part D an analog-to-digital conversion circuit, part E a storage circuit, part F a time mode selection circuit, part G a self-timer display circuit, part H a real time extension circuit, part I a clock signal generating circuit, part J an electromagnetic release circuit, part K a magnet control circuit arranged to control a magnet provided for shutter time control, part L a switch operation control circuit for controlling the operation of various switches, part M an out-of photometric range display circuit, part N a time correction circuit, part 0 a power supply circuit and part P a flash circuit.

The power supply circuit 0 will be described first.

A power source battery BTT supplies electrical power to the circuit through SW3 having three fixed contacts: ON, OFF and BC (battery check). Power is removed from each part when switch SW3 is shifted to the OFF position, but can be supplied to each part when the power source switch SW3 is shifted to the ON contact. A battery check is performed when the switch SW3 is shifted to the BC contact. A power supply control transistor TR1 is connected between the ON contact and supply terminal El, a capacitor C1 being provided to smooth the voltage at El.

A switch SW1 is arranged to be opened by the first pressure on a shutter release button (not shown) and transistor TR1 and another transistor TR3 are controlled by opening and closing of this switch SW1. Voltage VBAT is supplied to the various parts when the switch SW3 is shifted to the ON contact, and when the switch SW1 is closed, a voltage builds up across the capacitor C1 and also is applied to various parts, as well as to a comparator CP3. A voltage divider serves to divide the voltage appearing at El and the divided voltage is impressed on the comparator CP3. Also, a reference voltage VC (derived from a constant voltage circuit VC' is applied to the comparator CP3, the output from which is applied to an OR gate G72 through an inhibit AND gate G73. Capacitor C10 and resistor R10 are connected in series with each other and capacitor C10 is also connected to point Eel A signal PUC is taken out from the common point of the capacitor C10 and the resistor R10, through two inverters in series.

The photometric circuit A comprises operational amplifiers OP 1, OP2 and OP3. The operational amplifier OP2 is of a MOS type having a high input impedance and has connected across its two inputs a light-measurement element P 1 of a TTL-compatible type to measure through a camera lens (not shown) the brightness of an object to be photographed. In the feedback path of the operational amplifier OP2, there is inserted a logarithmic compression diode D2, so that the output voltage of the operational amplifier corresponds logarithmically to the brightness of the object; i.e. a brightness value Bv on the APEX system. The operational amplifier OP 1 is provided to supply a voltage to the non-inverting input of the light measuring operational amplifier OP2.

The output of the amplifier OP2 is applied to the inverting input of amplifier OP3 and the reference voltage VC is applied to its non-inverting input, whereby the amplifier may operate thereon.

The computing circuit B comprises the constant voltage circuit VC' which produces the reference voltage VC, an operational amplifier OP4 which receives the reference voltage VC and produces a voltage KVC which is higher than the reference voltage VC, and an operational amplifier OP5 which also receives the reference voltage VC at its non-inverting input and receives stop and correction information at its inverting input, from variable resistances ACV and AAV to compute with them. The circuit B further comprises an operational amplifier OP6 the inverting input of which receives the output of the operational amplifier OP5 and film sensitivity information from variable resistance SV and the noninverting input of which is connected to the reference voltage VC, so that time information is produced, corresponding to the brightness of an object to be photographed.Operation amplifier OP7 also is connected to the reference voltage VC and produces time information for flash photography. Analog switches AS 1 and AS2 are provided for selectively applying the output of one of the operational amplifiers OP6 and OP7 to the next stage. A switch SW6 is opened at the time of stopped-down light measurement; and a switch SW10 is provided for effecting a correction in the case of a back-lighted object, or the like. When this switch SW10 is closed, the output of the operational amplifier OP6 is corrected by a factor a, discussed below.

In the display circuit C, a meter MET indicates time information received through the analog switches AS 1 or AS2, and also is used for battery checking. A diode D3 is provided to prevent a time information signal being applied to a resistor RL of the battery check circuit when the power source switch SW3 is in the ON position.

In the analog-to-digital conversion circuit D, the time information selected by analog switch AS1 or AS2 is fed to a buffer amplifier OP8, and the voltage KVC is fed to another buffer amplifier OP9. An operational amplifier OP 10 has the reference voltage VC applied to its non-inverting input, and the outputs of amplifiers OP8 and OP9 are applied to its inverting input This operational amplifier OP 10 is provided with a capacitor C2 and diode D5 in its feedback path to form a mirror integration circuit. A comparator CP 1 is provided for comparing the output of the amplifier OP 10 with the reference voltage VC.

In the storage circuit E, the output of an OR gate G3 is applied to the clock input terminal CP of an 8-bit counter CT1. The output of an OR gate G5 is applied to the reset terminal R of the counter CT1, while the output of an AND gate G 18 is arranged to be applied to a preset enable terminal PE of the counter CTl . The output of the comparator CPl of the analog-to-digital conversion circuit is fed to an inverting input of gate Gl,which gate together with gate G2 are arranged to apply pulses obtained from a counter frequency divider CT2 to the OR gate G3. The output of a gate G4 is applied to the OR gate G5, whereas the output SLFM of an OR gate G7 is arranged to be applied to the gates G1, G2, G4 and an OR gate G4.The output 8MSE of the eighth bit of the counter CTl is also applied to the OR gate G6, the output from which is applied both to the buffer amplifier OP8 and to the buffer amplifier OP9 through an inverter. The bits 1, 2, 3 and 7 of the counter CTl are grounded.

In the time mode selection circuit F, brushes S1, S2 and S3 are selectively arranged to be grounded dependent upon the rotation of a shutter time dial Dug1, the brushes being connected to the bits 4, 5 and 6 of the counter CT1. These bits 4, 5 and 6 of the counter CTl are arranged to have a voltage El impressed thereon through respective pull-up resistors when the brushes are not grounded and also are connected to a NAND gate G 16 and a gate G 17. The output of the NAND gate G 16 is applied to the AND gate G 18 as an AUTO signal. The output of the gate G 1 7 serves as a BULB signal; and M3EN and CCEF signals are fed to the other inputs of the AND gate G 18.

In the self-timer display circuit G, the outputs of bits 4 and 6 of the counter CT1 are applied to an AND gate G9, the output from which is combined in OR gate G8 with the signal PUC, to be applied to the reset terminal R of a D type flip-flop Fl. A SLFS signal and a RELS signal are applied to the inputs D and CP of the flip-flop F1 and a SLFA signal is taken out from the Qoutputoftheflip-flop,to be applied to the OR gate G7. A SLFR signal is also applied to the OR gate G7. The 6-bit output of the counter CT1, the SLFA signal, and 16 Hz and 8 Hz pulses from the counter frequency divider CT2 are all applied to a gate G 19. The 1-bit output of the counter CT1, the SLFA signal, and the 4 Hz and 2 Hz pulses from the counter frequency divider CT2 are all applied to a gate G20. The outputs from gates G 19 and G20 are combined in an NOR gate G2 1, which drives through a buffer amplifier a light emitting diode LED 1, to which a voltage VBAT is connected.

In the real time extension circuit H, a 4 to 16 line decoder DE1 receives the outputs of the 4, 5, 6 and 7-bits of the counter CTl while the outputs 0, 1 , 2 10 of the decoder DEl are supplied to one input of two-input AND gates G35, G34............ G34 G25 respectively while the 8192 Hz, 4096 Hz .... . . .. . . 8 Hz pulses of the counter frequency divider CT2 are applied respectively to other inputs of the AND gates G35, G34 . . . .. .. . . G25. The outputs 12, 13, 14 and 1 5 of the decoder DEl are applied through an OR gate 22 to an OR gate 23, the gate output 22 also being taken out as an OV4S signal. In addition, the output 11 of the decoder DE1 is applied to the OR gate G23 and the output from which is applied to an AND gate G24.The 4 Hz pulse of the counter frequency divider CT2 is applied to the other input of the AND gate G24. The outputs of all the AND gates G24, G25 .......... G35 are applied to the clock pulse input CP of a counter CT3, through an OR gate G36.

The output of a NAND gate G37, the inputs of which receive the S4SW and PRCT signals, is supplied to the reset terminal R of the counter CT3. Each output bit of the counter CT3 is applied respectively to each of EX-OR gates G38, G39, G40, gate G41 and AND gate G42. On the other hand, the 1,2 and 3 bit outputs of the counter CTl are applied to other input terminals of the gates G38, G39 and G40. The outputs of these gates G38, G39 and G40 are applied to the gate 041. The other input of the AND gate G42 receives the OV4S signal, and its output is applied to an OR gate G43, as is the output of gate G41.

The output of the OR gate G43 is taken out as a CNTE signal.

In the switch operation control circuit L, which controls the operation of various switches, switches SW2, SW5 and SW7 are connected in parallel with each other. One side of each of these switches is grounded while the other side is arranged to have the voltage El impressed thereon through a resistor. The switch SW2 is arranged to be closed by a second pressure on the shutter release button.

The switch SW5 is arranged to be moved on completion of film winding to shift from the illustrated position to its other contact. A film winder (not illustrated) can be operated when the switch SW5 is in the illustrated condition. The switch SW7 is closed when a self-timer is used. A switch SW17 is connected in parallel with the switch SW2 to permit remote control of the self-timer. These switches SW17 and SW2 are connected to the emitter of the transistor Tr3 through a diode D4. A signal in response to the opening and closing of the switch SW5 is applied through an inverter to the D input of a flip-flop F7 while a signal in response to the opening and closing of the switch SW5 is applied through the OR gate G72 to the reset terminal R of the flip-flop F7.A signal corresponding to the opening and closing of the switch SW2 is applied through a NOR gate G70 and a delay circuit DL1 to the CP input of the flip-flop F7 and is also applied to one input of an AND gate 071. The above-mentioned PUC signal is also applied to these gates G70 and G72, while the BULB signal is applied to the AND gate G71. A signal which corresponds to the opening and closing of the switch SW7 is taken out through an inverter as the SLFS signal and is also applied to a NAND gate G68, to produce the SLFR signal after combining with the RELS signal. The Q output of the flip-flop F7 is connected to the base of the transistor Tr3, while the Q output is connected to gates G61, G62, G63 and G67 and to a delay circuit DL2 respectively.

In the out-of-photometric range display circuit M, a comparator CP2 compares a signal BVO with the reference voltage VC. The output of the comparator CP2 is applied to the gate G67 together with the output of the AND gate G66 to which the 4 Hz and 8 Hz pulses of the counter frequency divider CT2 are supplied. The output terminal of the gate G67 is arranged to be connected through a buffer amplifier to a light emitting diode LED2 on which the voltage VBAT is impressed.

In the shutter time control magnet controlling circuit K, there is shown a shutter time control magnet MG3; a switching transistor TR4 which controls current flow from VBAT through the magnet MG3; and flipflops F4 and F5. The M3EN signal is taken from the 0 output of the flip-flop F4 and is applied through a NOR gate G64 to the base of the transistor TR4. The output of an inhibit AND gate G47 on which the CNTE and BULB signals are impressed is supplied through the OR gate G46 to the reset terminal R of the flip-flop F4. Also, the PUC signal is applied to the OR gate G46. The reset terminal R of the flip-flop F5 is connected through an inverter to the Q output of the flip-flop F7.The output of the AND gate G62 is applied to the D input of the flip-flop F5 while the output of an AND gate G60 is applied to the CP input of the flip-flop F5. The collector of the transistor Tr4 is connected to the input terminal of the AND gate G62 while the 64 Hz pulse of the counter frequency divider CT2 is applied to the AND gate G60. A signal from the Q output of the flip-flop F5 is applied to the NOR gate G64 through the AND gate G63, while a signal from the Q output of the flip-flop F5 is taken out as the RELS signal.

In the electromagnetic release circuit J, an electromagnetic releasing magnet MG2 has a diode connected in parallel therewith and is connected to the common point between a resistor on which the voltage VBAT is impressed and a capacitor. The output of the OR gate G7 is supplied to one input of each of gates G14 and G 1 5. The other input of gate 614 receives an 8 Hz pulse from the counter frequency divider CT2 and the output of this gate G14 is applied to the S input of the flip-flop F2; while the other input of the OR gate G15 receives the PUC signal and the output of this gate G15 is applied to the reset terminal R of the flip-flop F2. The Q output of the flip-flop F2 is connected to a NAND gate G13 which also receives the RELS signal.The output of the NAND gate G 13 is applied to the gate G4 and is also applied through an inverter to the D input of a flip-flop F3. The output of an AND gate G12 is applied to the CP input of the flip-flop F3 while the output of an OR gate G 11 is applied to the reset terminal R of the flip-flop F3. To the AND gate G12 are applied the output of the comparator CP 1, the 8bit output of the counter CTl and the 8MSE signal, while the PUC signal is applied to the OR gate G1 1.

The 0 output of the flip-flop F3 is applied to an AND gate G10 and to the S input of the flip-flop F4 and is also supplied through an inverter and a buffer amplifier to the magnet MG2, which is provided for electromagnetic release. The AND gate G10 receives the 64 Hz pulse of the counter frequency divider CT2 and the output thereof is applied to the OR gate G1 1.

In the clock signal generating circuit I, the 14-bit counter frequency divider CT2 generates pulses of 22 to 214 Hz. This circuit I includes delay circuits DL2, DL3 and DL5, inhibit AND gates G45, G61 and G73. The output of the AND gate G12 is directly applied to the gate G45 and is also indirectly applied thereto through the delay circuit DL3. The output of the delay circuit DL3 is also applied to the AND gate G1 O. The output of the delay circuit DL2 is applied to the gate G60 and to the gate G61. To the gate G73 are applied the output of the delay circuit DL5 and a signal from the 0 output of a flip-flop F6. This O output also is applied to the delay circuit DL5, and is taken out as a PRCT signal.An OR gate G44 has its inputs connected to the outputs of the gates G45, G61 and G73, the PUC signal and the output of an inhibit gate G59. The output of the OR gate G44 is applied to the reset terminal R of the counter frequency divider CT2.

In the time correction circuit N, one end of each of shutter time correcting switches SW15 and Sol 6 is grounded while the voltage El is applied through a resistor to the other end thereof. A signal corresponding to the opening and closing of the switch Sol 5 is applied to gates G50, G51,G52 and G54. A signal corresponding to the opening and closing of the switch SW16 is applied to the gates G52 and G54. The output of the OR gate G54 is applied to gates G48 and G49 while the 1024 Hz pulse of the counter frequency divider CT2 is also applied to these gates G48 and G49. The 2048 Hz pulse of the counter frequency divider CT2 is applied to the inhibit AND gates G50 and G51.The output of the AND gate G 52 and the 512 Hz pulse of the counter frequency divider CT2 are applied to an AND gate G 53.

The outputs of the gates G48 and G49 are applied to an OR gate 055. The outputs of the gates G50 and G51 are applied to an OR gate G56. The outputs of these gates G52, G55 and G56 are applied through an AND gate G57 to an OR gate G58. The output of the AND gate G53 is also applied to the other input of this OR gate G58 and the output of the gate G58 is applied to the CP input of the flip-flop F6. The voltage El is impressed on one side of a count switch SW4 through a resistor while the other side thereof is grounded. A signal corresponding to the opening and closing of the count switch SW4 is applied to a delay circuit DL4 and to the inhibit AND gate G59; it is also taken out as the S4SW signal.

The output of the delay circuit DL4 is also applied to the gate G59. The output of the gate G59 is applied to the reset terminal R of the flip-flop F6 while the voltage El is impressed on the D input of the flip-flop F6.

In the flash circuit P, an accessory shoe AC is provided with terminals TC', TX' and TA'. Switch SW14 indicates an X-synchronised contact which is provided between the terminals TA' and TX'; a transistor TR2 has its base connected to the terminal TC' while its emitter is arranged to have the output of a NAND gate G65 applied thereto. The collector of the transistor TR2 is grounded through a resistor. A signal from the collector of the transistor TR2 is applied through an inverter to the gate G65 and is also taken out as the CCEF signal. The M3EN signal is applied through an inverter to the gate G65 while the 128 Hz pulse of the counter frequency divider CT2 is also applied to the gate G65. The signal from the collector of the transistor TR2 is applied to the analog switch AS 1 and is also applied through an inverter to the analog switch AS2.The signal is further arranged to be applied through a buffer amplifier to the light emitting diode LED3.

Figure 2 shows the internal mechanism of a camera which is equipped with the exposure control circuit shown in Figure 1. In Figure 2, like parts with those of Figure 1 are given like reference characters. Light transmitted through a photograph-taking lens (not shown) is sighted by a photographer via an eye-piece 1 05, the light being directed on to a reflecting mirror 101, and thence through a screen 102, condenser lens 103 and penta-prism 104, one after the other. Part of the light coming from the penta-prism is incident upon the light receiving element Pi, in the form of a silicon photo-diode or similar element. The accessory shoe AC is arranged on the camera body (not shown) above the penta-prism, and includes the synchronising contact TX', the flash control signal contact TC', and a grounding part TA.Meter MET displays shutter time inside a view finder the deflection of the meter pointer indicating the shutter time to be used for photographing displayed against a shutter time graduation disposed in a peripheral portion of the view finder. The light emitting diode LED3 provided for indicating a flash-light photographic mode also serves.to illuminate the meter. Switches SW1 and SW2 are arranged to be turned on respectively by the first and second depression pressures of a shutter release button 106.

On 9 shutter time selection dial 107, there are engraved markings BC for battery check, OFF for cutting off the power supply, AUT for automatic exposure, B for bulb photography and manually selectable shutter times 30, 60 1000. The required marking is aligned with an index 1 07a. On the shaft of the dial 107, there is provided a slider plate 108 which is provided with three brushes S1, S2 and S3 and a further brush 110. On a base plate 111, there is provided a grounded conductor pattern DG1 which is arranged as shown in Figure 1 and the contacts BC, OFF and ON of the switch SW3, also shown in Figure 1.When the dial 107 is rotated, the brushes S1, S2 and S3 brush the conductor pattern DG1 while the further brush 110 brushes over the contacts BC, OFF and ON of the switch SW3. A film sensitivity (ASA) setting dial 112 is disposed coaxially with but separately from the dial 107; this dial 112 has film sensitivity values engraved thereon for setting against an index 11 3a on an index plate 11 3. A brush 114 is interlocked with the dial 112, to wipe resistor element SV disposed on the base plate 111.

A diaphragm aperture ring 200 has aperture values engraved thereon and has a lug 200a; the ring 200 can be turned to place a selected aperture value against an index 201. An aperture preset ring 202 is urged by a spring 202a to rotate clockwise and is provided with a lug 202b arranged to co-operated with the lug 200a of the aperture ring 200, to prevent clockwise rotation of the aperture preset ring 202 under the action of the spring 202a. The aperture ring 200 is given sufficient frictional force so that rotation thereof is possible only by manual operation. The aperture preset ring 203 has an arm 202c extending back into the camera body and a lever 202d extending towards the diaphragm (not shown) to determine the rotation of a bell crank and aperture setting cam ring, neither of which is shown in the drawing.The bell crank is provided to define the rotation of a diaphragm driving ring (not shown) which determines the diaphragm aperture. A pin 203 is secured to the diaphragm driving ring, and the free end thereof engages with an automatic stop lever 205 which is urged to rotate counterclockwise by a spring 205a of an automatic stop unit Ad. This automatic stop lever 205 is provided with a depending leg 205b.

The automatic stop lever 205 is provided with an automatic stop force accumulator lever 206 which is rotatable coaxially with the lever 205 and which is urged by a spring 206a to rotate clockwise.

In the middle portion of one side of the lever 206, there is provided a shaft 207 which rotatably mounts a common lever 209 urged by a spring 208. One end of the common lever 209 engages with the leg 205b of the automatic stop lever 205, the common lever 209 also having a pin 209a. The automatic stop force accumulator lever 206 is also provided with an engaging claw for resisting the pulling force of the spring 206a. An automatic stop return signal lever 1 has one end disposed in a position to engage the pin 209a of the common lever 209. The range of angular movement of the automatic stop force accumulator lever 206 is defined by a stop-pin 212.

The automatic stop force accumulator lever 206 is cocked against the force of spring 206a by a charge lever 213 having a pin 21 3a engageable with one end of the lever 206. The mechanism is cocked when a film wind lever (not shown) is operated, the winding lever driving a shaft 214 having a charge cam 215 affixed thereto. A roller 217 on a charge transmission lever 216 engages the cam 215, lever 21 6 having a pin 21 6a secured thereto. An intermediate lever 21 8 is provided in a position opposite to the charge transmission lever 21 6 and is coupled to the lever 21 6 through a link member (not shown). A pin 21 8a is secured to one end of the intermediate lever 218, while a magnet charge plate 21 8b formed of a resilient material is secured to the middle part of the lever 21 8.A release lever 221 is urged to rotate counterclockwise by a spring 221 a, and co-operates with lever 210 engageable with the claw part of lever 206.

In the stop control unit Ad, there is also provided a sector gear 223 which has a slider cooperating with a resistance AAV. The sector gear 223 is urged by a spring 223a to rotate counterclockwise, which spring 223a exerts a weaker force than the spring 202a. A transmission lever 224 is provided with a slider co-operating with a resistance AVC and is urged by a spring 224a to rotate clockwise. The transmission lever 224 is rotated against the force of spring 224a in response to a fullaperture correction pin 225 within the objective lens, to set the resistance value AVC. Switch SW6 is provided to select between full-aperture light measurement and stopped-down light measurement, and is operated when a lever 226 serving as a moving contact is driven by movement of an operating lever LEV.The switch SW6 is turned on for full-aperture light measurement and is opened for stopped-down light measurement. In other words, in the case of full-aperture light measurement, the variable resistances AVC and bAV are connected to a circuit as shown in Figure 1 and the full-aperture F-value and a stopped-down value of the lens are set.

A signal lever 231 has one end engaged with the arm 202c of the aperture preset ring 202. A pin 223b is secured to the sector gear 223 and is arranged pivotally to support the middle part of the signal lever 231. The other end of the signal lever 231 is pivotally connected to a supporting lever 232. In a mirror lifting mechanism unit Mi, there is provided a mirror driving lever 234 which engages the tip portion 206b of the above-mentioned automatic stop force accumulator lever 206. The upper, bent end portion of the lever 234 is urged by a spring 234a to rotate counterclockwise. A mirror spring-up lever 235 is pivotally arranged on a mirror driving lever 234 and engages with a hook portion 236a of a spring-up locking claw 236 pivotally connected to the shaft (not shown) of the mirror driving lever 234.

The spring-up locking claw 236 is urged to rotate clockwise by a spring 236b. The mirror spring-up lever 235 engages a pin secured to one end of an intermediate spring-up lever 237. The other end of the lever 237 engages a pin 238a secured to a mirror receiving plate 238, pivotally mounted on shaft 238b.

The mirror driving lever 234 is provided with a protrusion 234d, which engages with one end 239a of a front shutter curtain locking lever 239. The other end is in engagement with an upstanding portion of the front curtain release lever 240 urged to rotate clockwise by a spring 240a. The upper end of the front curtain release lever 240 engages with front curtain clamping lever 241. The front curtain clamping lever is urged by a spring 241 a to rotate clockwise while the tip of the lever 241 is in engagement with a pin 251a secured to a front curtain gear 251. Count switch SW4 is normally closed and is arranged to be opened by rotation of the front curtain clamping lever 241. The front curtain gear 251 engages with a front curtain pinion 252 of a front curtain drum (not shown). A rear curtain gear 253 is provided coaxially with but separately from the front curtain gear 251.This rear curtain gear 253 is in engagement with a rear curtain pinion 254 of a rear curtain drum (not shown).

Pins 253a and 253b are secured to the rear curtain gear 253. An attraction lever 255 is arranged to be moved by the pin 253a and is arranged to be attracted to a shutter controlling magnet MG3 by its polepiece 255a. A rear curtain signal lever 242 is rotatable by the pin 252b but is urged by a spring 242a to rotate counterclockwise. The other end of the rear curtain signal lever 242 engages with one end of a lever 243 while the other end of the lever 243 is in engagement with an upper end of a mirror return signal lever 244. A pin 244a, which is secured to the middle part of the mirror return signal lever 244, engages the end portion of the spring-up locking claw 236. Furthermore, the lower end portion of the mirror return signal lever 244 also engages with the end portion of an automatic stop return signal lever 211 of the above-mentioned unit Ad.

In a camera release unit Sm, there is provided an electromagnetic releasing magnet MG2, which includes a permanent magnet 245. An armature holding lever 246 holds an armature 247, and is urged counterclockwise by a spring 246a which exerts a stronger force than the spring 221 a of the abovementioned release lever 221 but a weaker force than the attracting force of the permanent magnet 245.

A start lever 249 is coaxially connected to the armature holding lever 246, and is provided with pins 249a and 249b. The pin 249a engages the release lever 221 while the pin 249b is arranged to be pushed by the resilient charge plate 218b.

In Figure 3, which shows the circuit of a flash device mountable on the camers shown in Figures 1 and 2, there is shown a power source 1; a booster circuit 2 to boost the voltage of the power source 1; a main capacitor 3 provided for the accumulation of flash discharge energy; a voltage detecting circuit 4 which comprises voltage dividing resistors 40 and 41 and which is arranged to detect the voltage across the main capacitor 3; and a display circuit 5 which detects the charging of the main capacitor 3 to a predetermined voltage and to display this on completion. The display circuit is a known arrangement including a neon tube 51, and thus the details of the circuit are not here described.

A trigger circuit 6 is driven by a trigger control circuit 61, arranged as follows. The base of a transistor 62 is connected to the display circuit 5 through a resistor 63. The emitter of the transistor 62 is connected to a terminal TX through a diode 72. The collector of the transistor 62 is connected to the base of a transistor 66 through a resistor 67 while the collector of the transistor 66 is connected to the trigger circuit. The emitter of the transistor 66 is connected to a common point between a resistor 61 connected in series with the power source 1 and a capacitor 65. This common point is also connected through resistor 6-8 to the base of the transistor 66.The trigger circuit 6 is arranged to operate only when the display circuit 5 is in an operative state; transistors 74 and 77 which will be described later are in their off conditions; and the synchronising contact TX' shown in Figure 1 is turned on.

A flash discharge tube 7 generates flash-light when a trigger signal from the trigger circuit 6 allows capacitor 3 to discharge through the tube 7. A known form of discharge control circuit 8 is connected in series with the flash discharge tube 7, the discharge control circuit 8 being composed of a thyristor connected in series with the discharge tube 7, a capacitor and so on. A light receiving element 9, such as a photo-cell or the like, is arrange to receive light reflected from an object and originating from the flash discharge tube 7; and an integration circuit 10 integrates the output of the light receiving element 9 to form in combination with the light receiving element 9 a known light adjusting circuit and an aperture information input circuit which supplies aperture information for flash light photography to the light adjusting circuit.The aperture information corresponds to a set camera aperture value and is supplied to the integration element of the light adjusting circuit, to vary the integration.

A transistor 1 3 has its base connected to the display circuit 5, to the common point of resistors 54 and 55 so that the transistor 1 3 is turned on when the neon tube 51 of the display circuit is lit. A resistor R1 is provided to transmit a flash photography shifting signal to a control circuit of the camera, automatically to control the shutter time to values suitable for flash photography.

A power source switch 1 5 for the flash device is selectively connectible to terminals 15a and 1 5b.

The switch 1 5 is interlocked with a selection switch 1 6 having terminals 1 6a and 16b. Another selection switch 1 7 having terminals 17a, 17b and 1 7c is provided for control of the operation of the light adjusting circuit and an aperture value for the light adjustment. The flash device has a grounding terminal TA and a flash control signal terminal TC in addition to the synchronising contact TX. A resistor 42 is connected to the collector of the transistor 13 and also to the base of a transistor 74, to prevent an erroneous action. The collector of a transistor 73 is connected to the low voltage side of the neon tube 51, and the base of a transistor 78 is connected to the TX contact through diodes 71 and 72 while its emitter is connected to the collector of the transistor 1 3 through a high resistance 79. The collector of the transistor 78 is connected to the bases of transistors 75 and 77. The collector of the transistor 75 is connected to the base of the transistor 74 and the collector of the transistor 77 to the collector of the transistor 74 respectively.

The described structurai arrangement of the camera and of the flash device operates as follows.

When a desired aperture value is set by turning the aperture ring 200 relative to the index 201, the spring 202a causes the aperture preset ring 202 to follow the rotation of the aperture ring 200. This rotation is transmitted to the sector gear 223 to set a resistance value of the variable resistance hAV according to the aperture value. The resistance of the variable resistance AVC is determined by the transmission lever 224, rotated in response to the full-aperture correction pin 225 which adjusts the camera in correspondence to the full-aperture of the lens mounted on the camera. When the dial 112 is adjusted against the index 11 3a according to the sensitivity of a film loaded in the camera, a resistance value corresponding to the film sensitivity is set on the variable resistance SV.When the marking AUT on the dial 107 is adjusted to the index 107a, the contacts S1, S2 and S3 are turned off, according to the conductor pattern shown in Figure 1. Concurrently with this, the brush 110 turns the switch SW3 ON. This causes VBAT to be applied to the various parts shown in Figure 1.

The first pressure on the release button 106 causes the switch SW1 to close and the transistor TR1 is accordingly turned on. As a result of this, voltage El appears across the capacitor C1, and is applied to the various parts and circuits including gates, amplifiers and flip-flops, shown in Figure 1.

Then, the operational amplifier OP2 produces brightness information corresponding to the output of the light receiving element P 1 which receives light from the object through the photograph-taking lens; i.e.

there is produced a voltage corresponding to the value Bron the APEX system. The amplifier OP1 receives the reference voltage VC from the constant voltage circuit VC' and a voltage KVC which is higher than the reference voltage VC and supplies a current of KVC-VC RBV to the feedback diode D1 of the amplifier OP 1 , to determine thereby the potential at the non-inverting input of the amplifier OP2.By selecting the value of the resistance RBV, the output of the amplifier OP2 can be set to be: VC + (B,,oK1)Vstep (1 wherein B,, = B,, A,,0 A,,c and V,, A,, and AVC respectively represent brightness information, objective lens full-aperture F number information, and lens curvature compensation and so on information, on the APEX system; K1 represents a constant; and Vstep represents difference in the output according to the varying steps of brightness of an object to be photographed.The inverting input of the amplifier OP3 thus receives the signal of VC + (B,, -- K1)V,,, of formula (1) and computes it with the reference voltage VC to obtain at its output (assuming the number of steps is 14): VC VC-(B,,0-K1) 14 (2) The amplifier OP4 is an operational amplifier which receives the reference voltage VC and produces a voltage KVC which is higher than the voltage VC. The output of the operational amplifier OP4 is supplied to the amplifier OP 1 and to the amplifier OPS which computes AVC and AAV. hAV is an APEX value indicative of the aperture value of a lens stopped-down from the full-open position thereof.

The non-inverting input of the amplifier OPS receives the reference voltage VC; and the amplifier OP5 performs a computation on the AVC and hAV information setting values to produce the following at its output: V VC + (AV-AVC + K2).

14 (3) The above stated formula (2) output of the photometric circuit, the formula (3) output of the information setting circuit and film sensitivity information SV are impressed on the inverting input of the amplifier OP6 which computes them with the reference voltage VC supplied to its non-inverting input, to produce the APEX value for time information as its output, as shown below: VC VC VO ((B,, + K1)--- -- (hAV - AVC + K2) + (SV + K3)} x x 2+ VC 2 x2+VC 14 14 14 VC =(BV-AVO-#AV+ SV+ K) +VC 7 VC VC -(BV-AV+SV+ + K) + VC = (TV + K) +VC + VC (4) 7 7 wherein K represents a constant equal to K 1 - K2 + K3; AV = AVO + AAV; and TV = BV -AV + SV.

The switch SW6 is opened for stopped-down light measurement. The switch SW10 is provided for correction in the case of a backlighted object, and so on, and when this switch is turned on, the output of the amplifier OP6 can be corrected as much as a factor a such that the APEX time value becomes VC (TV+K-a) +VC.

7 In the stopped-down light measuring mode with the switch SW6 opened, since the output of the amplifier OP3 is VC VC-(BV-AV+KI) 14 the value of the feedback element of the amplifier OP5 is selected in such a manner as to make its output VC VC + K2 14 Then, the output of the amplifier OP6 becomes: VC VC VC+(BV-AV+Kl -K2+SV+K3)-=VC+(W+K)- 7 7 and a computation output similar to formula (4) can be obtained.

By means of the above mentioned processes, an analog time information TV under daylight conditions is produced from the amplifier OP6 to be displayed on the meter MET inside the view finder through the analog switch AS 1 and, at the same time, is supplied to the analog-to-digital conversion circuit D of the next stage.

Referring now to Figure 4 which shows a timing chart, the operation of the circuit after the analogto-digital conversion circuit but without the use of a self-timer is shown and is described below: When the switch SW1 is turned on, the eighth bit of the storage counter CTl is at logic level "0" (hereinafter referred to simply as '0' and the 8MSE signal is '0'. Since the self-timer switch SW7 is off, the output SLFM of the gate G7 is 'O' and the output of the gate G6 to which these signals are applied also is 'O'. This '0' signal then makes the buffer amplifier OP8 operative and the other buffer amplifier OP9 inoperative. Under this condition, the output of the amplifier OP9 presents an infinite impedance and, when the amplifier OP8 is arranged to produce a signal of VC (W-1O) +VC, 14 the output of the amplifier OP 10 increases linearly, as shown in Figure 4, because the amplifier OP 10 constitutes a mirror integration circuit which has a capacitor C2 in its feedback path (Time a to time b).

This signal is supplied to the comparator CP 1 and is compared with the reference voltage VC which is supplied to its non-inverting input. Since the output voltage of the amplifier OP 10 is higher than voltage VC, the output ADE of the comparator CP 1 goes low. Since the SLFM signal is 'O' when the self-timer is not used as mentioned in the foregoing, the gate G 1 allows the 1 6384 Hz pulse from the counter frequency divider CT2 to pass and supplies it to the gate G3. At this time, the gate G2 is inhibited, because the SLFM signal is '0'. Therefore, the 16384 Hz pulse is supplied to the clock input CP of the counter CT1.Then, if the shutter information manual setting dial 107 is in the AUT position, all of the inputs to the gate G1 6 are at logic level "1" (hereinafter referred to simply as '1'). Therefore, the AUTO output from the gate G 1 6 goes low and is supplied to the preset-enable input PE of the counter CT1, to inhibit presetting of the counter CT1 The counter thus simply counts clock pulses. In other words, the counter CT1 counts in synchronism with the fall of the clock input, and the time lapse before the output 8MSE of the eighth bit of the counter CTl goes high is about 8 ms.

Referring to trace C of Figure 4, showing OP 10 output, the capacitor C2 of the integration circuit which is charged from time a to time b begins to discharge at point b because voltage KVC is impressed on the amplifier OP 10 from the amplifier OP9, because when the 8MSE goes high, so does gate G6 output, thereby inhibiting amplifier OP8 but connecting amplifier OP9.

This causes the output of the amplifier OP 10 to drop as shown in Figure 4, C, but when this output becomes lower than the voltage VC (point c), the output ADE from the comparator CPl goes high. ADE is supplied to the gate G4, and because this gate also receives a low SLFM signal and MEOK at '1' a signal ADR at '1' is produced at the output of the gate G4. Since the SLFR signal is low, the ADR signal passes through the gate G5 and is supplied to the reset input R of the counter CT1, to reset the count the instant (Figure 4, E) the ADR signal goes high. Accordingly, the output 8MSE of the eighth bit then goes low and the integration capacitor C2 is again charged, as shown in Figure 4, C. This cycle is repeated.Under this condition, the counter CTl does not store information but continues to count the digital clock pulse input repeatedly. During this, the waveform due to charging and discharging of the capacitor C2 varies according to the brightness information, as shown in Figure 4.

To take a photograph, a second pressure is applied to the shutter release button to close switch SW2. Provided the film has been wound on, the switch SW5 is closed so that the signal SW5S becomes '0', and when the release switch SW2 is closed, the signal SW2S also becomes '0'. While the switch SW2 is off, the flip-flop F7 is reset by the power-up clear signal PUC applied to the gate G72, and the Q output of the flip-flop F7 isO'. When the switch SW5 is closed, a '1' is supplied to the input terminal D of the flip-flop F7; the input PUC to the gate G70 goes low and the signal SW2S also goes low. The signal applied to the clock input CP of flip-flop F7 is delayed by a predetermined period by the delay circuit DL1 but a '1' is eventually passed to that input.Since the shutter time selection dial 107 is not set for bulb exposure, the BULB signal, which is one of the inputs to the gate G71, is low.

Furthermore, the output of the comparator CP3 is also '0' when the power source voltage El exceeds a preset inhibiting voltage value, the output of the gate G72 goes low. Accordingly, the Q output of the D type flip-flop F7 becomes '1' in synchronism with the rise of the input CP. (See Figure 4, G. H and I).

When the film winding action has not been completed, the switch SW5 is open and the signal SW5S is high. Therefore, even when the release switch SW2 is turned on, the input D to the flip-flop F7 is still low and the 0 output of the flip-flop does not go high. Even should winding be completed while the release switch SW2 remains closed, the Q output of flip-flop F7 still does not become '1' because the CP input remains at '1' when the input D of the flip-flop F7 goes high. Therefore, where an automatic film winding device is employed, automatic winding does not cause an immediate shutter release, so long as both release switches SW1 and SW2 remain closed. This condition continues indefinitely and to take the next photograph the switch SW2 must be opened and then closed again.

The switch SW17 is a remote control release switch which is provided for the purpose of releasing the shutter from a point remote from the camera. When the power source switch is on, turning on switch 17 causes the transistor TR1 to be turned on through the diode D4 in the same manner as if the release switch SW1 were turned on. The power source holding circuit is turned on by this, and if at that moment film winding has been completed, the D input to the flip-flop F7 goes high concurrently with the turning-on of the power source. The output of the gate G70 will thus rise after the time delay of the power-up clear signal PUC and then the output of the gate G70 is supplied to the CP input of the flipflop F7, which has again been delayed by the delay circuit DL1.When reset of the initial PUC is stabilised, a trigger signal is applied to the CP input of the flip-flop F7 and the 0 output of the flip-flop F7 becomes '1'. Once this condition has been reached, even if the switch SW1 7 is now turned off, the transistor TR3 remains on to latch the power source because the Q output of the flip-flop is 'O'. In cases where the power source voltage drops to a value below a preset value, the output of the comparator CP3 of the inhibit circuit goes high to reset flip-flop F7 through gates G72 and G73, so that the output Q of the flip-flop F7 is reset toO' before a signal RELS, which causes storing of the computed value TV to begin as will be described hereinafter, goes high.

The output 0 of the flip-flop F7 is one of the inputs to the gate G61 The other input of the gate G61 has impressed thereon the 0 output of the flip-flop F7 through the delay circuit DL2. Therefore, as shown in Figure 4, I and J, the output of the gate G61 produces an instantaneous signal RELR in synchronism with the rise of the 0 output of the flip-flop F7. The RELR signal serves to reset the frequency dividing counter CT2 through the gate G44. Furthermore, the 0 output of the flip-flop F7 is supplied to the reset input R of the D type flip-flop F5, through an inverter. By this, the flip-flop F5 is always reset when the Q output of the flip-flop F7 is low.When the Q output of the flip-flop F7 becomes '1', the output of the gate G63 of the control circuit K for the shutter time controlling magnet goes high, and this is supplied to the transistor TR4 to turn it on through the gate G64, thus energising the magnet MG3. The signal M3EN, which is one of the inputs to the gate G64, is initially arranged to be 'O' as will be described hereinafter. When the power is supplied to the magnet MG3, the MG3S signal goes high and the output of the gate G62 becomes '1', and is supplied to the D output of the flip-flop F5. The two inputs to the gate G60, which is connected to the CP input of the flip-flop F5, are respectively the output from the delay circuit DL2 and the 64 Hz output of the counter CT2, so that the gate G60 produces a 64 Hz output after the counter CT2 has been completely reset.Accordingly, the 0 output RELS of the flip-flop F5 becomes '1' after the rise of the 64 Hz pulse, i.e. about 8 ms after resetting of the flip-flop F5. This makes Q(F5) go low at this point, so that the power is supplied to the magnet just for 8 ms. At this moment, if the power source voltage drops below an inhibit voltage, the 0 output of the flip-flop F7 goes low to terminate here all of the sequence of actions. Also, should the coil of the magnet go open circuit by some cause, the Q output of the fli-p-flop F5 never becomes '1', because no current flows through the magnet.

The Q output of the flip-flop F5 serves as a release signal RELS, to begin the next sequence of actions. The gate G73 is arranged in such a way that, even should the power source voltage fall to a great degree as might be the case with a long exposure, the system can be still operated.

The following description concerns the storage of digitised exposure information and the operation of the electromagnetic release magnet. The SR type flip-flop F2 is reset by the power-up clear signal PUC, when the power source is turned on. On the other hand, the counter CT2 is reset by the PUC signal through the gate G44. Since no self-timer is used, the SLFM signal, which is one of inputs to the gate Gl 4, is '0'. The gate G 14 passes a '1' to the S input of flip-flop F2 when the 8 Hz signal from the counter CT2 goes high. In other words, the Q output of the flip-flop F2 goes high about 60 ms after the power source is turned on.This means that, even when the switches SW1 and SW2 are instantaneously turned on by a quick depression of the shutter button, the storage action described below can be performed only after a minimum period of time of 60 ms. This arrangement ensures that the storage action can be performed without fail, even in cases where the brightness of an object to be photographed is low and a longer period is required before the output of the operational amplifier OP2 becomes -stable.

When the release signal RELS goes high 60 ms after the power source is turned on, as mentioned above, the output MEOK of the gate G 13 becomes '0' and is supplied to the gate G4, to inhibit that gate. The output signal ADR of the gate G4, therefore, cannot go high, even at the time of completion of the A-D conversion by means of which .the output signal ADE of the A-D converting comparator CPl goes high. Accordingly, resetting of the counter CT1 through gate G5 is not performed. Furthermore, since the singa I ADE under this condition is '1', the output of the gate G 1 goes low and the A-D conversion information is stored by the counter CT1. This condition is shown in Figure 4, D, E and M as timing diagrams for these parts.

On the other hand, since both the inputs 8MSE and ADE to the gate G12 are high, the gate G45 produces a short pulse MG2R, which serves to reset the counter CT2 through the gate G44 (Figure 4, N). The D type flip-flop F3 receives at its D input the MEOK signal which is '1' and in synchronism with the output of the gate G 12 going high, the Q output of the flip-flop F3 becomes '1'. The output from the gate G 1 0 to which this 0 output of the flip-flop F3 is supplied is inhibited while the counter CT2 is reset by the output of DL3. Then the gate G 10 goes low until the 64 Hz signal is produced from the counter CT2. The output of the gate G 10 goes high when the 64 Hz signal from the counter CT2 goes high, i.e.

after about 8 ms, and the flip-flop F3 is reset through the gate G 11. In other words, the Q output MG2S of the flip-flop F3 is high just for a period of 8 ms (Figure 4, 0).

The 0 output MG2S of the flip-flop F3 energises the magnet MG2 through an inverter and a buffer. This causes a current to flow through the coil of the magnet, to counteract the force of the permanent magnet 245, thereby to release the armature 247 to move with the armature holding lever 246 under the action of spring 246a. The signal start lever 249 and thus the release lever 221 both rotate. The operation of the release lever 221 causes the locking claw lever 210 to turn counterclockwise, to unlock the automatic stop force accumulator lever 206 which is then caused by the spring 206a to rotate clockwise. With the lever 206 rotated, the automatic stop lever 205 rotates clockwise together with the lever 206 through the common lever 209. This allows the pin 203 of the aperture driving ring within the lens to move, to stop down the diaphragm blades (not shown}.Also, since the tip portion 206b of the automatic stop force accumulator lever 206 moves away from the mirror driving lever 234, the spring 234a causes the mirror driving lever to rotate counterclockwise. The mirror spring-up lever 235 which is pivoted on the mirror driving lever 234 moves in the same direction, together with the part 236a of the spring-up locking claw 236. This causes the spring-up intermediate lever 237 to rotate couterclockwise, which in turn causes the mirror receiving plate 238 to spring up on its shaft 238b, by engagement with the pin 238a. Furthermore, with the mirror driving lever 234 rotated, its protrusion 234d causes the end portion 239a of the front curtain locking lever 239 to rotate clockwise, while a hooked portion thereof comes off the upstanding portion of the front curtain release lever 240. Then, the spring 240a causes the release lever 240 to rotate the front curtain clamping lever 241. The rotation of the lever 241 then opens the count switch SW4 and, at the same time, allows the front curtain of a shutter mechanism (not shown) to start running.

The 0 output MG2S of the flip-flop F3 is led to the set input S of the RS flip-flop F4 to set the flipflop F4. This flip-flop has been reset by the PUC input to the gate G46 when the power source was turned on. The Q output M3EN of the flip-flop F4 goes high, so that a '0' is supplied to the gate G65 of the flash control circuit P, to inhibit the flash device charging completion signal CCEF. The '1' signal M3EN also is transferred through the gate G64 to cause a resumption of the supply of power to the shutter time controlling magnet MG3 (Figure 4, Land P).

The output of the gate G47 is supplied to the reset input R of the flip-flop F4 through the gate G46.

When the exposure time completion signal CNTE, which is one of the inputs to the gate G47, goes high, the flip-flop F4 is reset and the shutter time controlling magnet MG3 is turned off. This causes the rear curtain gear 253 to rotate running the rear curtain, the pin 253b driving the lever 242 also to rotate clockwise. The rotation of the lever 242 in turn causes the signal lever 243 to rotate counterclockwise, and then the mirror return signal lever 244 rotates clockwise. The pin 244a rotates the mirror spring-up locking claw 236 counterclockwise to unlock the mirror spring-up lever 235. The mirror receiving plate 238 is released from its sprung-up condition. The mirror is brought back down into its lowered position, by a spring (not shown).The lower end portion of the mirror return signal lever 244 rotates the automatic stop return signal lever 211 counterclockwise to cause the pin 209a of the common lever to rotate counterclockwise and thus to unlock the dependent leg 205b of the automatic stop lever 205.

The returning spring 205a then rotates the automatic stop lever 205 counterclockwise. A spring (not shown) then causes the pin 203 of the diaphragm driving ring within the lens to follow the rotation of the automatic stop lever 205, to open the diaphragm aperture blades and the photographing operation is completed.

When the dial 107 has been set to the bulb mode, the output BULB of the gate Gel 7 is high.

Therefore, the CNTE input of the gate G47 is inhibited. When the switch SW2, which is operated by the second pressure on the shutter release button, is opened after having been closed, the output of the gate G7 1 goes high. Then, when the power source latch is removed and the switch SWl is turned off to turn off the power source, the rear shutter curtain runs down to complete a bulb photographing operation.

When the above-mentioned exposure information is stored, the output 8MSE of the eighth bit of the counter CT1 is always '1'. Therefore, the inverting input of the amplifier OP 10 at this point is connected to the amplifier OP9 and the capacitor C2 is charged in the reverse sense to the sense when integrating. However, when the voltage across the capacitor C2 becomes a preset value, the charging current flows through the diode D5 and the capacitor C2 is prevented from being charged further through the action of this diode D5.

The digital information (time) stored in the storing counter CT1 is read out by the real-timeexpansion and time-correction circuits in the next stage, to determine a shutter time. As shown in Table 1 below, four bits of the counter CTl may store digital information of the shutter time values from 1/1000 sec. to 4 sec.

TABLE 1 B8 B4 B2 B1 Shutter time (sec.) 0 0 0 0 1/1000 0 0 0 1 1/500 0 0 1 0 1/250 0 0 1 1 1/125 0 1 0 O 1/60 o 1 0 1 1/30 ~0 1 1 0 1/15 0 1 1 1 1/8 1 0 0 0 1/4 1 0 0 1 1/2 1 0 1 0 1 1 0 1 1 2 1 1 0 0 4 1 1 0 1 4 1 1 1 0 4 1 1 1 1 4 As shown in Table 1, the shutter time value is arranged not to exceed 4 sec. for a reason mentioned hereinafter. The first, second and third bits B 1/8, B1/4 and B 1/2 of the counter are arranged by dividing information of one step by 8.Unless the dial 107 is set to the AUT position, the stored digital information from the A-D conversion is cleared by a signal from the gate G 18 when the magnet MG2 is energised, so that the shutter time can be directly preset by the conductor pattern DG1 on presenting a '1' at counter input PE. Unless in the bulb photography mode, with flash photography since the signal CCEF becomes '0' upon completion of charging of the flash device, the gate G 18 is inhibited and analog switch AS2 conducts so the output of the amplifier 0P7, arraged exclusively for flash light photography, causes a camera shutter time of 1/60 sec. to be stored.

After the magnet MG2 (electromagnetic release) is released, the mechanical sequence of actions mentioned in the foregoing causes the front shutter curtain to run, and then the count switch SW4 is turned off. Through the delay circuit DL4 and the gate G59, the gate G44 produces a short pulse to reset the counter CT2 (Figure 4, 0 and R). Then, if both of the time correction switches Sol 5 and SW16 are closed, gates G49 and G50 may pass pulses on their other inputs. The 1024 Hz and 2048 Hz signals from the counter CT2 are thus supplied to the gate G57 through the gates G55 and G56.

Accordingly, the output of the gate G57 is supplied to the CP input of the D type flip-flop F6 through the gate G58. This clock pulse input to the Rip-flop F6 is set at the next leading edge of the waveform (1024 Hz x 2048 Hz) after the reset input of the flip-flop returns to '0'. The length of time required for this is about 250 ,us (Figure 4, S). The instant the 0 output PRCT of the flip4lop F6 becomes '1', the delay circuit DL5 and the gate G73 cause the gate G73 to produce a reset pulse PRER, by which the counter CT2 is again reset through the gate G44 (Figure 4, T).

TABLE 2 P1 (SW15) P2 (SW1 6) Correction time O 0 250,us 1 0 500 yes 0 1 750 1 1 1 ms Table 2 shows the time periods for shutter time correction obtainable by use of the shutter time correction switches SW15 and SW16. As shown in Table 2, the time correction obtainable from the switches SW15 and SW16 is not continuous and may require fine adjustment, which can be performed by means of a mechanical governor (not shown).In such a case, the use of a small mechanical member in the governor will suffice, because the required adjustment is within 250,us. Thus continuous correction over a wide range from 250,us to 1250,us may be possible by the use of such a mechanical member in combination with the electrical correction circuit.

When the counter CT2 is reset by the signal PRER from the gate G73, the real shutter time is counted, according to the information in the counter CT1. For example, let the information stored in the counter CT1 be 0, 0, 1,0, 0, 0, O in sequence from the first bit to the seventh bit. Then, a 'O' at output line 0 of the decoder DE1 becomes '1', to allow gate G35 to pass 8192 Hz pulses from the counter CT2 to the counter CT3 through the gate G36. In the counter CT3, the count occurs in synchronism with the falling edges of the pulses from the gate G36. When the count reaches 8, the output CT8E at terminal 8 becomes '1 '. Then, when 4 further pulses are counted, the two inputs to each of the three EX-OR gates G38, G39 and G40 coincide. Bpcause of this, the output from the gate G41 goes high and the output CNTE of the gate G43 also goes high.In this way, the RS flip-flop F4 is reset, and this causes the shutter time controlling magnet MG3 to be de-energised, to end an exposure. In this example, the real shutter time becomes: 1 1 12= sec.

8192 683 The real time counting circuit can be expressed by the following formula: Assuming that the integral part of the memory at the counter CTl is 10-A and the decimal part thereof is B, TV becomes B o 8 and then the real time becomes (8 x B), 8 x 2A wherein A is-2 < A < 10 while B isO < B 7.

The reset input is removed from the counter CT3 by gate G37 when the signal PRCT becomes a '1' after exposure time correction counting. Furthermore, when the output of the decoder DE1 exceeds 12, an output OV4S from the gate G22 is '1' and, after the counter CT3 has counted 1 6 of the 4 Hz pulses (i.e. after 4 seconds), the signal CNTE goes high. Thus, the exposure time never exceeds 4 seconds according to this arrangement as shown in Table 1.

If the self-timer is not used, the circuitry shown in Figure 1 operates as described in the foregoing.

For photography with the self-timer, the circuitry of Figure 1 operates as described below: When the self-timer is to be used, the switch SW7 is turned on. When the switch SW1 is turned on by the first pressure on the shutter release button, the signal SW1 S goes low, and at this moment, the switch SW2 is off and the signal SW2S is high. With the switch SW7 turned on, the SW7S signal goes low and causes the output SLFR of the gate G68 to go high. This signal is supplied to one of the inputs of the gate G5 of the A-D conversion circuit, so that the output of gate G5 completely resets the counter CT1. In other words, the analog-to-digital conversion is inhibited under this condition.

Concurrently with this, the outputs of the gates G7 and G6 go high. The inverting input of the amplifier OP 10 of the mirror integration circuit is thus connected to the amplifier OP9 and, as mentioined in the foregoing, the output of the amplifier OP 10 is held at a preset voltage lower than the reference voltage VC by the action of the diode D5.

Following this, when the switch SW2 is turned on by a second pressure on the shutter release button, both signals SW S and SW2S become a '0' and, as described in the foregoing, an electric current is allowed to flow to the shutter time controlling magnet MG3 for 8 ms. The 0 output RELS of the flipflop F5 goes high if there is no inhibiting action. This output RELS going high causes the Q output SLFA of the D type flip-flop F1 also to go high, (Figure 4, V, W, X, Y). Concurrently with this, the gate G68 is inhibited by this high RELS signal and the output SLFR of the gate G68 goes low.However, though the output of the gate G7 still remains at '1' because the SLFA signal has gone high, the counter CTl is released from its reset state because both inputs to gate G5 are low. With the signal SLFM at '1', a 4 Hz signal is transferred to the counter CTi through the gates G2 and G3. On the other hand, at the counter CT2, only the 64 Hz bit has become a '1' the instant the 0 output RELS of the flip-flop F5 has become a '1'. Accordingly, the count begins from this state one after another.When the bits of B1 and B4 of the counter CT1 have gone high, i.e. after a period of about 1 0 seconds, the outputs of the gates G9 and G8 go high to reset the flip-flop F1 and the Q output SLFA thereof becomes an 'O'. This period of time, i.e. the period during which the signal SLFA remains high, is the self-timer period.

During this self-timer period, the gates G19 and G20 receive the high signal SLFA; the gates are also connected to bit B4 of counter CT1 . Two further inputs of gate G20 are connected respectively to the 4 Hz output of counter CT2 and to bit B 1/8 of counter CT1, this latter bit serving as a 2 Hz output.

Two further inputs of gate G19 are connected respectively to the 8 and 1 6 Hz outputs of counter CT2.

In this way, for the first 8 seconds of self-timer operation, a 2 Hz signal with a duty cycle of 1/4 is passed through gate G20 to gate G21, and for the last 2 seconds of self-timer operation, an 8 Hz signal with a duty cycle of 1/4 is passed through gate G19 to gate G21. The light-emitting diode LED1 for selftimer operation display is driven by the output of gate G21 through a buffer amplifier.

Upon expiration of the self-timer period, the signal SLFA goes low to permit the same sequence of actions as in the case of the operation without the self-timer. In addition, in the counter CT2 when the Q output SLFA of the flip-flop F1 goes low, i.e. when the self-timer period has expired, the outputs of all bits are at 'O'. The flip-flop F2 therefore, is not set until the output of 8 Hz bit next goes high - about 60 ms. Accordingly, about 60 ms after expiration of the self-timer period, the D input MEOK to the flip-flop F3 goes high to permit the storing and exposure control sequence of actions.

Next, the operation of the out-of-photometric range display circuit M will be described. When a film of high sensitivity is used for the camera, for performing stopped-down light measurement photography and so on, the light actually received by a photo-electric element (such as SPC) is sometimes very weak, even when the correct exposure time is within a normal range. In case of such weak light, the light receiving element in general has a poor photometric accuracy and thus makes it difficult to carry out photography with a correct exposure value.

In such a case, a warning is displayed by the display element LED2 which is provided in the display circuit M shown in Figure 1 .A photoelectric signal BVO coming from the photometric circuit A and the computation circuits is impressed on the inverting input of the comparator CP2 of the display circuit M and is compared with the reference voltage VC supplied to the non-inverting input thereof. When the light incident upon the light receiving element P1 is weak, the voltage at the non-inverting input of the comparator CP2 becomes higher than that at the inverting input, to cause the output of the comparator CP2 to go high. The gate G66 receives signals of 4 Hz and 8 Hz from the counter CT2 to produce at its output terminal a signal of 4 Hz with a duty cycle of 1/4.When the output of the comparator CP2 is high, the output of the gate G67 drives the display element LED2 to give a flickering display. Also, the Q output of the flip-flop F7 is supplied to the gate G67 and, when the switch SW2 is turned on by the second pressure of the shutter release button to cause the camera to take an exposure, the warning display by the display element LED2 is cancelled.

In the flash photography mode, the flash device charging completion signal circuit operates in the following manner. To carry out flash photography, the automatic light-adjusting flash device shown in Figure 3 is mounted on the "hot shoe" accessory shoe 11 of the camera. The automatic light-adjusting flash device automatically adjusts the quantity of light issuing from the flash tube by operating on the light reflected from an object to be photographed. The circuitry in the camera is automatically set to the flash photography mode by a signal produced upon completion of charging of the main capacitor of the flash device. If the main capacitor of the flash device has not been charged completely when the release switch SW1 is turned on, no control signal from the control terminal TC' is supplied to the base of the transistor TR2, and the transistor remains off. The collector output CCEF of the transistor, therefore, is at 'O'. Since the M3EN signal isO', the NAND gate G65 allows the 128 Hz pulse from the counter frequency divider CT2 to pass therethrough and the 128 Hz pulse is thus applied to the base of the transistor TR2. When the terminal voltage of the main capacitor of the flash device (Figure 3) reaches a given level, the transistor 13 shown in Figure 3 is turned on in synchronism with the 128 Hz pulse supplied to the control terminal TC' being high. Then, a control signal from the flash device is impressed on the base of the transistor TR2 shown in Figure 1 , through the terminal TC' of the hot shoe. This turns the transistor TR2 on and the output signal CCEF of the transistor goes high.The output of the gate G65 is kept high by this signal CCEF, which is latched at '1' to bring the camera into a charging completion mode.

Should the electromagnetic releasing magnet MG2 be excited to bring the shutter into an operative state before charging is completed, the signal M3EN goes high. This keeps the output of the gate G65 high. After this, when the main capacitor 3 of the flash device is charged, the transistor 74 is turned on. The base potential of the transistor 1 3 no longer increases and the transistor 13 turns off.

Therefore, the transistor TR2 in the camera does not turn on and, accordingly, the output CCEF remains at 'O'; thus the charging completion mode is not obtained. Under this condition, the camera operates in an AE (automatic exposure) mode for daylight photography.

When the X contact is turned off after the rear curtain of the shutter has run down, the transistor 75 of the flash device circuit is turned off. Although, in response to this, the transistor 74 tries to turn on, time delay caused by the capacitor 76 prevents the transistor from turning on immediately and thus the transistor 1 3 is turned on prior to the transistor 74. This causes the base of the transistor 74 to be held low, and the transistor does not turn on. Accordingly, the transistor TR2 in the camera is turned on and the camera is brought into the charging completion mode. When the charging completion mode is obtained in this manner, the output CCEF of the transistor TR2 goes high. The analog switches of the computing circuit B are operated to turn off AS 1 and to turn on AS2.By this action, the flash photography time information which has been preset at the amplifier OP7 is suppled to the analog-todigital converter of the next stage, instead of the time information TV which is obtained at the output of the amplifier OP6. At the same time, the flash photography time information is displayed by the display meter MET. The amplifier OP7 is set to produce a signal of VC (6 - K) + VC, i.e. TV = 6 (1/60 sec.).

7 Concurrently with this, the signal CCEF is connected through a buffer to drive the light emitting diode LED3, provided to indicate the flash mode is set, and to illuminate the meter pointer at the indication of 1/60 sec.

After an exposure has been taken, the film winding and cocking operation is performed in the following manner. The winding shaft 214 and the charge cam 21 5, which are interlocked with a winding lever (not shown), are rotated in the direction of the arrow, so that the charge transmission lever 21 6 is moved clockwise. The intermediate lever 218 which is connected to the lever 21 6 is also rotated clockwise. This causes the charge lever 21 3 to rotate clockwise, by means of pin 21 8a. Then, the stepped part 21 3a cocks the automatic stop force accumulator lever 206 by turning it counterclockwise against the spring 206a until it is locked by the locking claw lever 210.During this, the tip portion of the automatic stop force accumulating lever 206 forces the mirror driving lever 234 to rotate clockwise. Since the mirror driving lever 234 is locked by the locking claw lever 210 acting on the lever 206, the mirror driving lever is locked in its cocked state. In response to the rotation of the mirror driving lever 234, the spring-up locking claw 236 also rotates in the same direction until the claw 236 engages the mirror spring-up lever 235. In addition a film winding mechanism (not shown), a set lever (also not shown) rotates the front curtain release lever against the force of spring 240a until the set lever comes to engage the front curtain locking lever 239.

The above stated rotation of the intermediate lever 218 also performs a charging function, to allow the armature 247 to be attracted by the permanent magnet 245 of the camera release unit Sm.

The magnet charge plate 21 8b of the intermediate lever 218 causes the pin 249b of the start signal lever 249 to rotate clockwise. The armature holding lever 246 which is fixed in relation to the lever 249 moves in the same direction against a spring 246a, to allow the armature to be attracted by the permanent magnet 245. Since the attraction of the armature 247 depends on the degree of rotation of the intermediate lever 218, the magnet charge plate 21 8b is made of a resilient material to absorb variations in the degree of rotation of the lever 218, leaving an ample allowance for the armature to be moved to a position at which it is attracted by the permanent magnet.

In the embodiment of camera control system of the present invention as described in the foregoing, the shutter time is obtained by A-D conversion of an analog time, and the digital value is stored, and then expanded digitally to real time during an exposure. The shutter time obtained in this manner is very accurate. In addition to that, in the case of a self-timer operation, the operation is performed with two counters connected in series these counters being separate from each other for different operations. The overall arrangement is very effective. Each circuit of the system is supplied with power only for the minimum period of time required for its action, so that the use of battery power can be held to a minimum. In addition, there is provided a check which is used during every photographic operation to ensure the action of each part is normal. When the flash device is used, the required elements are set automatically to the flash photography mode when the flash device has been completely charged. These conditions are clearly displayed within the view finder field. In accordance with the present invention, therefore, a camera can be arranged to perform very accurately automatic exposure control in all its photographic modes.

Claims

1. A digital control system for a camera, comprising: a first counter in which may be stored digital information indicative of a required shutter time; a second counter arranged to generate pulses for the sequence control of the control system; first switch means to initiate operation of a control sequence; second switch means to allow selection of a particuiar operational mode of the control system; signal generating means responsive to the operation of the first and second switch means, to produce either a shutter release signal on operation of only the first switch means or a timer signal on operation of the first and second switch means; gate means to transfer pulses from the second counter to the first counter for counting therein on production of the timer signal by the signal generating means;; means responsive to a preset count in the first counter then to cause the cessation of the timer signal and the production of the shutter release signal; and shutter time means responsive to the shutter release signal to cause storage in the first counter of the information indicative of the required shutter time, whereafter an output is provided to open the camera shutter for a period dependent upon the stored information.

2. A digital control system as claimed in claim 1, wherein a clock pulse source supplies pulses to a pulse input of the second counter which serves successively to divide the frequency of the clock pulse source, whereby a plurality of pulse outputs of different frequencies is available from the successive bits of the second counter.

3. A digital control system as claimed in claim 2, wherein the shutter time means selects a pulse output from the second counter dependent upon the stored value in the first counter, and the said output for opening the shutter allows the shutter to remain open for a preset number of pulses from the selected output of the second counter.

4. A digital control system as claimed in any of claims 1 to 3, wherein the said output drives a first electromagnet for association with the camera shutter, thereby to release the shutter for opening movement.

5. A digital control system as claimed in claim 4, wherein the said output drives a second electromagnet for association with the camera shutter at the end of the shutter time period, to effect closing movement of the shutter.

6. A digital control system as claimed in any of the preceding claims, wherein the first switch means comprises a release for the camera.

7. A digital control system as claimed in claim 6, wherein the first switch means is associated with further switch means which further switch means is automatically operated prior to operation of the first switch means on actuating the camera release, the further switch means serving to allow light measurement to be effected without generating the shutter release signal.

8. A digital control system as claimed in any of the preceding claims, wherein the second switch means serves to set the control system in a self-timer mode, whereby the shutter release signal is not generated until after the lapse of a predetermined self-timer interval.

9. A digital control system as claimed in any of the preceding claims, wherein the stored information in the first counter is generated directly by means of a manually-operable shutter speed control.

1 0. A digital control system as claimed in any of claims 1 to 8, wherein the stored information is generated indirectly, by computation on the amount of light received from an object to be photographed.

11. A digital control system as claimed in claim 10, wherein a light-sensitive element is included to detect light reflected from an object to be photographed, and the output from the element is integrated to obtain light value data.

12. A digital control system as claimed in claim 11, wherein the output from the element is integrated for a fixed time whereafter the integrated output is reduced at a fixed rate to preset value, and the first counter is arranged to count pulses from the second counter from the commencement of integration until the integrated output falls to the preset value, the final count being the stored information indicative of the required shutter time.

13. A digital control system as claimed in claim 11 or claim 12, wherein the output from the light element is modified prior to integration to take into account film sensitivity and selected lens aperture of a camera used with the control system.

14. A digital control system as claimed in any of the preceding claims, wherein further gate means is provided to apply a re-setting input to the first counter, the further gate means being arranged to reset the first counter when the second switch is operated and to release the first counter reset when the first switch is operated.

1 5. A digital control system as claimed in claim 3 or any claim appendent thereto, wherein time correction means are provided to delay the commencement of counting of pulses from the selected output of the second counter but following the production of the output allowing the camera shutter to open.

1 6. A digital control system as claimed in claim 15, wherein the time correction means includes two selectively-operable switches to give four different correction delays.

1 7. A digital control system as claimed in claim 16, wherein the four delays range from 250 ys to 1 us.

1 8. A digital control system as claimed in any of the preceding claims, wherein there is provided a flash circuit adapted for use with an electronic flash gun, which circuit automatically causes information indicative of a suitable shutter time for flash photograpy to be stored in the first counter on production of the shutter release signal when the circuit senses that an associated flash gun is charged ready for operation.

1 9. A digital control system for a camera and substantially as hereinbefore described with reference to and as illustrated in Figures 1 and 4 of the accompanying drawings.

20. A camera whenever incorporating a digital control system as claimed in any of claims 1 to 19.

21. A camera as claimed in claim 20, and substantially as hereinbefore described with reference to and as illustrated in Figure 2 of the accompanying drawings.

22. A camera as claimed in claim 20 or claim 21 in combination with a flash gun substantially as described hereinbefore with reference to and as illustrated in Figure 3 of the accompanying drawings.

23. A camera capable of digitally performing exposure control comprising: a first counter for analog-to-digital conversion for a light measuring purpose; a second counter for sequence control of each part of the camera; first signal generating means having a first switch and being arranged to generate an electrical signal according to opening and closing of said first switch; second signal generating means having a second switch and being arranged to generate an electrical signal according to opening and closing of said second switch; signal selecting means which generates a release signal when the electrical signal from the first signal generating means is applied thereto and generates a time defining signal when both of the electrical signals from said first and second signal generating means are applied thereto; said signal selecting means being arranged to stop the generation of said time defining signal and to generate said release signal when a predetermined output signal of the first counter is applied thereto; and gate means for applying a predetermined pulse output from the second counter to the first counter when said time defining signal is applied thereto, said first and second counters being arranged to jointly define predetermined time according to opening and closing of the second switch.

24. A camera according to claim 23 including: electromagnetic release means for actuating the internal mechanism of the camera, said means being operated by said release signal.

25. A camera according to claim 24 wherein said first switch opens and closes in response to the operation of a release button; and said second switch is provided for the use of a self-timer.

26. A camera according to claim 25 further including: another gate means for producing a reset signal for said first counter and for receiving electrical signals from said first and second signal generating means, said gate means being arranged to reset the first counter when the electrical signal from the second signal generating means is applied thereto and, after that, releases the first counter from its reset state when the electrical signal from the first signal generating means is applied thereto.

27. An automatic exposure control device for a camera comprising: exposure computing means for daylight photograpy being arranged to generate an exposure signal corresponding to the brightness of an object to be photographed; exposure computing means for flash light photography being arranged to generate an exposure signal suitable for a flash photographing operation; exposure control means for performing exposure control in response to one of the exposure signals of the daylight photographing exposure computing means and the flash photographing exposure computing means; change-over means for applying one of the exposure signals of the daylight photographing exposure computing means and the flash photographing exposure computing means to said exposure control means;; electromagnetic release means for actuating the internal mechanism of the camera, the release means being arranged to produce an electrical signal when it operates; a charge completion signal receiving terminal; change-over control means for shifting said change-over means in such a manner that the exposure signal of the daylight photographing exposure computing means is applied to the exposure control means when a charge completion signal is not applied to said terminal and that the exposure signal of the flash photographing exposure computing means is applied to the exposure control means when the charge completion signal is applied to said terminal;

and inhibiting means for inhibiting the change-over controlling action of said change-over control means, the inhibiting means being arranged to be operated by the electrical signal from said electromagnetic release means to inhibit the action of the change-over control means.

28. An automatic exposure control device for a camera comprising: shutter holding means; supply means for supplying an electric current to said shutter holding means;

detecting means for detecting electric current flow to said shutter holding means, said detecting means being arranged to generate an electrical signal upon detection of the current flow to the shutter holding means; signal generating means provided with a switch which closes in response to a release operation, said signal generating means being arranged to generate an electrical signal when said switch closes: : control means for generating a release signal and a check signal, said control means being arranged to generate the check signal for a preset period of time to actuate said supply means when the electrical signal from said signal generating means is applied thereto and to generate the release signal when the electrical signal from said detecting means is applied thereto; and electromagnetic release means arranged to be operated by said release signal only when an electrical current flow to said shutter holding means is detected.