[go: up one dir, main page]

GB201913353D0 - Method for designing accelerator hardware - Google Patents

Method for designing accelerator hardware

Info

Publication number
GB201913353D0
GB201913353D0 GB201913353A GB201913353A GB201913353D0 GB 201913353 D0 GB201913353 D0 GB 201913353D0 GB 201913353 A GB201913353 A GB 201913353A GB 201913353 A GB201913353 A GB 201913353A GB 201913353 D0 GB201913353 D0 GB 201913353D0
Authority
GB
United Kingdom
Prior art keywords
designing
accelerator hardware
accelerator
hardware
designing accelerator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB201913353A
Other versions
GB2587032B (en
GB2587032A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Priority to GB1913353.7A priority Critical patent/GB2587032B/en
Publication of GB201913353D0 publication Critical patent/GB201913353D0/en
Priority to KR1020200034093A priority patent/KR102859775B1/en
Priority to CN202080052984.1A priority patent/CN114144794B/en
Priority to PCT/KR2020/010741 priority patent/WO2021054614A1/en
Priority to EP20865553.0A priority patent/EP3966747B1/en
Priority to US17/015,724 priority patent/US20210081763A1/en
Publication of GB2587032A publication Critical patent/GB2587032A/en
Application granted granted Critical
Publication of GB2587032B publication Critical patent/GB2587032B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/32Circuit design at the digital level
    • G06F30/33Design verification, e.g. functional simulation or model checking
    • G06F30/3308Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/20Design optimisation, verification or simulation
    • G06F30/27Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/34Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/04Architecture, e.g. interconnection topology
    • G06N3/045Combinations of networks
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/04Architecture, e.g. interconnection topology
    • G06N3/0464Convolutional networks [CNN, ConvNet]
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/08Learning methods
    • G06N3/082Learning methods modifying the architecture, e.g. adding, deleting or silencing nodes or connections
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/08Learning methods
    • G06N3/086Learning methods using evolutionary algorithms, e.g. genetic algorithms or genetic programming
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/08Learning methods
    • G06N3/09Supervised learning
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/08Learning methods
    • G06N3/092Reinforcement learning

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Artificial Intelligence (AREA)
  • Computational Linguistics (AREA)
  • Mathematical Physics (AREA)
  • Molecular Biology (AREA)
  • General Health & Medical Sciences (AREA)
  • Computing Systems (AREA)
  • Data Mining & Analysis (AREA)
  • Geometry (AREA)
  • Neurology (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Medical Informatics (AREA)
  • Bioinformatics & Cheminformatics (AREA)
  • Bioinformatics & Computational Biology (AREA)
  • Evolutionary Biology (AREA)
  • Physiology (AREA)
  • Image Analysis (AREA)
  • Complex Calculations (AREA)
  • Feedback Control In General (AREA)
GB1913353.7A 2019-09-16 2019-09-16 Method for designing accelerator hardware Expired - Fee Related GB2587032B (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
GB1913353.7A GB2587032B (en) 2019-09-16 2019-09-16 Method for designing accelerator hardware
KR1020200034093A KR102859775B1 (en) 2019-09-16 2020-03-19 Electronic device and Method for controlling the electronic device thereof
EP20865553.0A EP3966747B1 (en) 2019-09-16 2020-08-13 Electronic device and method for controlling the electronic device thereof
PCT/KR2020/010741 WO2021054614A1 (en) 2019-09-16 2020-08-13 Electronic device and method for controlling the electronic device thereof
CN202080052984.1A CN114144794B (en) 2019-09-16 2020-08-13 Electronic device and method for controlling the same
US17/015,724 US20210081763A1 (en) 2019-09-16 2020-09-09 Electronic device and method for controlling the electronic device thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB1913353.7A GB2587032B (en) 2019-09-16 2019-09-16 Method for designing accelerator hardware

Publications (3)

Publication Number Publication Date
GB201913353D0 true GB201913353D0 (en) 2019-10-30
GB2587032A GB2587032A (en) 2021-03-17
GB2587032B GB2587032B (en) 2022-03-16

Family

ID=68315417

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1913353.7A Expired - Fee Related GB2587032B (en) 2019-09-16 2019-09-16 Method for designing accelerator hardware

Country Status (2)

Country Link
KR (1) KR102859775B1 (en)
GB (1) GB2587032B (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111325327A (en) * 2020-03-06 2020-06-23 四川九洲电器集团有限责任公司 Universal convolution neural network operation architecture based on embedded platform and use method
CN111652365A (en) * 2020-04-30 2020-09-11 哈尔滨工业大学 A Hardware Architecture for Accelerating Deep Q-Network Algorithm and Its Design Space Exploration Method
CN112507197A (en) * 2020-12-18 2021-03-16 北京百度网讯科技有限公司 Model searching method, model searching apparatus, electronic device, storage medium, and program product
CN112613598A (en) * 2020-12-10 2021-04-06 上海交通大学 FPGA simulation-based resistive neural network accelerator evaluation method
CN112784954A (en) * 2019-11-08 2021-05-11 华为技术有限公司 Method and device for determining neural network
CN113033784A (en) * 2021-04-18 2021-06-25 沈阳雅译网络技术有限公司 Method for searching neural network structure for CPU and GPU equipment
CN113065639A (en) * 2021-03-08 2021-07-02 深圳云天励飞技术股份有限公司 Operator fusion method, system, device and storage medium
CN113592062A (en) * 2021-06-30 2021-11-02 深圳元戎启行科技有限公司 Neural network configuration method and device, computer equipment and storage medium
CN113592088A (en) * 2021-07-30 2021-11-02 中科亿海微电子科技(苏州)有限公司 Parallelism determination method and system based on fine-grained convolution calculation structure
CN113780542A (en) * 2021-09-08 2021-12-10 北京航空航天大学杭州创新研究院 FPGA-oriented multi-target network structure construction method
CN115099393A (en) * 2022-08-22 2022-09-23 荣耀终端有限公司 Neural network structure search method and related device
CN116245150A (en) * 2023-02-28 2023-06-09 西北工业大学 A Neural Network Reconfigurable Configuration Mapping Method Oriented to FPGA Resources
CN116305817A (en) * 2023-02-13 2023-06-23 北京大学 Accelerator design method based on generator modularization

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20240070376A (en) 2022-11-14 2024-05-21 주식회사 마키나락스 Method for controlling air conditioning device based on delayed reward
KR102531646B1 (en) * 2022-11-14 2023-05-12 주식회사 마키나락스 Method for controlling air conditioning device based on delayed reward

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102731086B1 (en) 2016-12-27 2024-11-18 삼성전자주식회사 A method for input processing using neural network calculator and an apparatus thereof
WO2019112959A1 (en) 2017-12-04 2019-06-13 Optinum Semiconductor Technologies, Inc. System and architecture of neural network accelerator
US11030012B2 (en) 2018-09-28 2021-06-08 Intel Corporation Methods and apparatus for allocating a workload to an accelerator using machine learning

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112784954A (en) * 2019-11-08 2021-05-11 华为技术有限公司 Method and device for determining neural network
CN111325327A (en) * 2020-03-06 2020-06-23 四川九洲电器集团有限责任公司 Universal convolution neural network operation architecture based on embedded platform and use method
CN111652365A (en) * 2020-04-30 2020-09-11 哈尔滨工业大学 A Hardware Architecture for Accelerating Deep Q-Network Algorithm and Its Design Space Exploration Method
CN111652365B (en) * 2020-04-30 2022-05-17 哈尔滨工业大学 A Hardware Architecture for Accelerating Deep Q-Network Algorithm and Its Design Space Exploration Method
CN112613598B (en) * 2020-12-10 2023-04-07 上海交通大学 FPGA simulation-based resistive neural network accelerator evaluation method
CN112613598A (en) * 2020-12-10 2021-04-06 上海交通大学 FPGA simulation-based resistive neural network accelerator evaluation method
CN112507197A (en) * 2020-12-18 2021-03-16 北京百度网讯科技有限公司 Model searching method, model searching apparatus, electronic device, storage medium, and program product
CN112507197B (en) * 2020-12-18 2024-01-19 北京百度网讯科技有限公司 Model searching method, device, electronic equipment, storage medium and program product
CN113065639A (en) * 2021-03-08 2021-07-02 深圳云天励飞技术股份有限公司 Operator fusion method, system, device and storage medium
CN113065639B (en) * 2021-03-08 2023-06-13 深圳云天励飞技术股份有限公司 Operator fusion method, system, equipment and storage medium
CN113033784A (en) * 2021-04-18 2021-06-25 沈阳雅译网络技术有限公司 Method for searching neural network structure for CPU and GPU equipment
CN113592062A (en) * 2021-06-30 2021-11-02 深圳元戎启行科技有限公司 Neural network configuration method and device, computer equipment and storage medium
CN113592088A (en) * 2021-07-30 2021-11-02 中科亿海微电子科技(苏州)有限公司 Parallelism determination method and system based on fine-grained convolution calculation structure
CN113592088B (en) * 2021-07-30 2024-05-28 中科亿海微电子科技(苏州)有限公司 Parallelism determination method and system based on fine-granularity convolution computing structure
CN113780542B (en) * 2021-09-08 2023-09-12 北京航空航天大学杭州创新研究院 A construction method of multi-objective network structure for FPGA
CN113780542A (en) * 2021-09-08 2021-12-10 北京航空航天大学杭州创新研究院 FPGA-oriented multi-target network structure construction method
CN115099393A (en) * 2022-08-22 2022-09-23 荣耀终端有限公司 Neural network structure search method and related device
CN116305817A (en) * 2023-02-13 2023-06-23 北京大学 Accelerator design method based on generator modularization
CN116245150A (en) * 2023-02-28 2023-06-09 西北工业大学 A Neural Network Reconfigurable Configuration Mapping Method Oriented to FPGA Resources

Also Published As

Publication number Publication date
KR20210032266A (en) 2021-03-24
GB2587032B (en) 2022-03-16
GB2587032A (en) 2021-03-17
KR102859775B1 (en) 2025-09-16

Similar Documents

Publication Publication Date Title
GB2587032B (en) Method for designing accelerator hardware
GB201907244D0 (en) Method
GB201911286D0 (en) Method
GB201909562D0 (en) Method
GB201913997D0 (en) Method
GB201910759D0 (en) Method
EP3773693A4 (en) Method for treating autoimmune disease
GB201907782D0 (en) Method
GB201900940D0 (en) Method
GB201900647D0 (en) Method
GB201809704D0 (en) Hardware accelerator
IL287063A (en) Method for producing biotissue-like structure
GB201917742D0 (en) Method
GB201917060D0 (en) Method
GB201900250D0 (en) Method for virus propagation
GB201917638D0 (en) Method
GB201913970D0 (en) Method
GB201910404D0 (en) Method
GB201909131D0 (en) Method
GB201906768D0 (en) Method
GB201901532D0 (en) Method
GB202007297D0 (en) Method
GB201918290D0 (en) Method
GB201917824D0 (en) Method
GB201917806D0 (en) Method

Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20240916