GB1603993A - Lattice filter for waveform or speech synthesis circuits using digital logic - Google Patents

Abstract

The digital filter comprises a memory (31) storing filter coefficients, a multiplier (30) multiplying internal data of the filter by the said filter coefficients, an adder/subtracter (33) adding the results of the multiplications to other data obtained in the filter, a delay circuit (34) connected up to the output of the adder/subtracter, a shift register (35) storing and retrieving at the requisite the time the data coming from the delay circuit, and an interlock output memory (36) storing a datum output by the filter. These various elements are interconnected with the aid of switches (37, 38) in order to perform the successive operations of multiplication and addition during a cycle. This filter, equivalent to a lattice filter, can be used in a voice synthesizer. <IMAGE>

Description

(54) LATTICE FILTER FOR WAVEFORM OR SPEECH SYNTHESIS CIRCUITS USING DIGITAL LOGIC (71) We, TEXAS INSTRUMENTS INCORPORATED, a Corporation organized according to the laws of the State of Delaware, United States of America, of 13500 North Central Expressway, Dallas, Texas, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- This invention relates to the generation of complex waveforms using digital signals and more specifically to the synthesis of speech by digital circuits using linear prediction methods.

Several methods are currently being used and experimented with to digitize human speech. For example, pulse code modulation, differential pulse code modulation, adaptive predictive coding, delta modulation, channel vocoders, cepstrum vocoders, formant vocoders, voice excited vocoders, and linear predictive coding methods of speed digitilization are known. These methods are briefly explained in "Voice Signals: Bit by Bit" at pages 28-34 in the October 1973 issue of IEEE Spectrum Computer simulations of the various speech digitalization methods have generally shown that the linear predictive methods of digitizing speech can produce speech having greater voice naturalness than the previous vocoder systems (i.e., channel vocoders) and at a lower data rate than the pulse coded modulation systems.

As will be seen, the linear predictive systems often make use of a multi-stage digital filter and as the number of stages of the digital filter increases, the more natural sounding becomes the resulting generated speech.

An early application of linear predictive methods to digital speech synthesis occurred in the late 1960's and early 1970's.

A historical analysis of some of this early work is set forth in Markel and Gray, "Linear Prediction of Speech" (Springer Verlag: New York, 1976) at pages 18-20.

The multi-stage digital filter used in linear predictive coding is preferably an all pole filter with all roots preferably occurring within the unit circle lzl=l when the mathematical transfer function of the filter is expressed as a Z-transform. The filter itself may take the form of a lattice filter of the type depicted in Figures 2a and 2b, however, other filters including ladder filters, normalized ladder filters and others are known, as set forth in Chapter 5 of "Linear Prediction of Speech". As will be seen, each stage of the lattice filter requires two addition operations, two multiplication operations and an delay operation. The filter is excited frdm either a periodic digital source for voiced sounds or a random digital source for unvoiced sounds.The filter coefficients are preferably updated every few milliseconds while the excitation signal is updated at a faster rate.

In the prior art, the lattice filter network of Figure 2a has been implemented by appropriately programming large digital computers. Exemplary Fortran programming of a computer for a computer for speech synthesis purposes is set forth in the aforementioned "Linear Prediction of Speech". Given the data rate of the excitation signal and the large number of arithmetic operations, i.e., two multiplications and two additions for each stage of a multi-stage filter and given that increasing the number of stages thereof increases the naturalness of the generated speech, high speed digital computers have been utilized in most speech synthesis work done to date. However, Dr. J. G. Dunn, J.

R. Cowan and A. J. Rusoe of the ITT Defence Communcations Division in Nutley, New Jersey have attempted to implement a multi-stage filter using metal oxide silicon (MOS) large scale integration techniques. They attempted using a multiprocessing approach, wherein many arithmetic units are operated simultaneously; however, this technique requires a very large number of multiplier and adder circuits be implemented on a semiconductor chip. Some discussion of the work done by Dr. Dunn et al is set forth in 'Progress in the Development of Digital Vocoder Employing an Itakura Adaptive Prediction published in 'Telecommunications Conference Records, I.E.E.E. Publ. No. 73' (1973). Replacing the lattic structure of Figure 2a with various adders and multipliers results in a complex and large size semiconductor chip.

It is one object of this invention to provide a system for synthesizing human speech in which the above difficulties are at least to some extent alleviated.

According to a first aspect of the present invention there is provided apparatus for generating data representing the instantaneous values of a signal representing speech from data representing the instantaneous values of an excitation signal the apparatus including (1) a first store for containing digital coefficients, (2) a digital feedback loop including a second store for data to enable data occurring at various different times to be available at other times, multiplier circuit means coupled to the store for multiplying by sequentially applied digital coefficients from the first store data occurring in the loop at respective selected times and producing an output, and an arithmetic unit coupled to the store for additively combining data occurring in the loop at various selected times and producing an output.

(3) means for applying to the loop data representing the instantaneous values of the excitation signal, (4) means for extracting from the loop data representing the instantaneous values of the speech signal, the arrangement being such that in operation the apparatus simulates the effect of a multistage digital filter, the coefficients of which correspond to the stored digital coefficients. The apparatus may include a digital to analogue converter coupled to the extracting means to produce an electrical speech signal. It may be part of apparatus for synthesising a speech signal, in which case it may include generator means coupled to the applying means for generating the data representing the instantaneous values of the excitation signal.This generator means may include switch means for changing the excitation sW Ftsten a voiced and an unvoiced sol as is appropriate to the speech being generated. The apparatus may be integrated on a single integrated circuit, thereby facilitating its use in the communication handling industry, communication equipment (i.e. telephones, voice cryptographic equipment, radios, televisions, etc.), and other equipment which generate the sound of a human's voice.

According to a second aspect of the present invention there is provided a method of generating data representing the instantaneous values of a signal representing speech from data representing the instantaneous values of an excitation signal and from a set of digital filter coefficients the method including the steps of 1. taking a first set of data in sequence, 2. multiplying said data by sequentially applied digital filter co-efficients, 3.Additively combining said data with a second set of data, 4. storing said data to enable data occurring at one time to be available at another time, 5. selectively feeding back said data to provide said first and second sets of data, 6. selectively extracting said data to represent speech, 7. combining data representing the instantaneous values of an excitation signal the arrangement being such that the method simulating the effect of passing the excitation signal through a multistage digital filter the co-efficients of which are the digital co-efficients.

The invention will be best understood by reference to the following detailed description of illustrative embodiments thereof when read in conjunction with the accompanying drawings, wherein: Figure la is a block diagram of the basic elements of a voice synthesizer; Figure lb depicts the presence of the excitation signal and Kn coefficients with respect to time; Figures 2a and 2b shows a typical lattice filter of the type used in speech synthesis circuits; Figure 3 shows a timing arrangement for the generation of intermediate results in a lattice filter having N stages; Figure 4a and 4b depict a timing arrangement for the generation of intermediate results in a lattice filter having ten stages; Figure 5 shows one embodiment of an digital filter equivalent to a lattice filter; ; Figure 6 lists the various intermediate results available in the filter of Figure 5 at various time periods of a cycle; Figure 7 shows another embodiment of a digital filter equivalent to a lattice filter; Figure 8 lists the various intermediate results available in the filter of Figure 7 at various time periods of a cycle; Figure 9 depicts the array multiplifer used in the digital equivalent filter; Figures 10a-lOd are logic diagrams of the various elements depicted in Figure 9; and Figure 11 shows a digital filter equivalent to a lattice filter.

Referring now to Figure la, there is shown, in block diagram form, the basic elements of a voice synthesizer system. The voice synthesis circuit comprises a multistage lattice filter 10, which digitally filters an excitation signal 11 using filter coefficients KlKn. Lattice filter 10 outputs a digital signal 12 which is converted to analog form by a digital/analog converter 13. The output of converter 13 is changed to audible sounds by a speaker 14 or other such sound conversion means; it is to be understood, of course, that an amplifier may be used between converter 13 and speaker 14 to amplify the analog output of converter 13 to levels required by speaker 14.

The excitation signal (U) 11 is generally derived from one of two sources, voicing source 15 or unvoicing source 16. The particular source used is determined by a digital switch 17. Voicing source 15 is utilized when generating those sounds for which the human vocal cords or vocal folds vibrate during speech, such as the sound of the first E in Eve. The rate at which the vocal folds open and close determines the pitch of the sound generated. Unvoicing source 16 is used when generating those sounds, such as the F in Fish, where the vocal folds are held open and air is forced past them to the vocal tract. Thus, the particular source, 15 and 16, utilized depends upon the source to be generated.

Typically, the unvoicing source 16 generates a random digital signal while voicing source 15 generates a periodic digital signal. The digital data supplied by voicing source 15 and unvoicing source 16 may, of course, be merely stored in one or more semiconductor read-only-memories (ROM's). Preferably, however, such data is stored in an encoded format, e.g., as pitch or a code actuating a random number generator. Thus, such data is usually first decoded before the random or periodic data (e.g., Signal V) is supplied to filter 10. Of course, depending on how such data is stored, the need for switch 17 may be eliminated. When the data is stored as pitch/a code activating a random number generator, a amplification factor (A) is preferably also stored in the ROM.

Amplification factor A adjusts the constant amplitude signal (V) from voicing source 15 or unvoicing source 16 to produce the excitation signal (V) for filter 10.

The excitation signal 11, which generally corresponds or mimics the function of the vocal folds, is altered by lattice filter 10.

Lattice filter 10 generally corresponds or mimics the function of the vocal track which filters the sounds generated at the vocal folds. The filter coefficients K1-K, reflect the shape (i.e. the resonances) of the vocal track during speech. Accordingly, coefficients KlKn are periodically updated to reflect the changing shape of the vocal track and may be stored along with the voicing/unvoicing source data in a readonly-memory.

Referring now to Figure Ib, there is shown in graphical form the outputs of unvoicing source 16 and voicing source 15 against time. Here voicing source 16 is shown as outputting an impulse at a five millisecond period, which corresponds to a frequency of 200Hz; this pitch corresponds to voiced sounds in the vocal range of many women. Since men typically have a lower pitch, a man's voicing source would output impulses less frequently.

Voicing source 16 is shown as outputting impulses at a period corresponding to the pitch of the person's voice; it is to be understood, however, that the periodic impulses may be replaced with other periodic functions, such as a decaying sine wave or the so-called "chirp function", which restart with a pitch related period.

Unvoicing source 16 is shown as a random signal.

The coefficients for lattice filter 10 are being shown as being updated every five milliseconds in Figure lb. It is to be understood, however, that the rate of which the coefficients of lattice filter 10 are updated is a design choice. If the coefficients are updated more frequently, the more closely lattice filter 10 wil model the vocal track dynamics, but with a corresponding increase in the amount of data to be stored in the aforementioned ROM. Of course, updating the coefficients less frequently has the opposite effect.

However, it has been found that by updating the coefficients approximately every five microseconds or so results in very high quality human speech being synthesized by lattice filter 10 with reasonable data storage requirements.

The time axis of Figure ib is shown as being divided into a hundred microsecond intervals. These intervals correspond to the data rate from voicing source 15 and unvoicing source 16 as well as the data rate to and from lattice filter 10. Further, while unvoicing source 16 and voicing source 15 may appear to be analog signals in Figure lb, it is to be appreciated that they are in fact digital signals whose magnitudes are as shown and which are updated at the intervals shown along the time axis of Figure lb. For information regarding the derivation of the magnitudes of the filter coefficients, reference should be made to the aforementioned "Linear Prediction of Speech." Thus, in this embodiment, the data rate to converter 13 would be 10KHz and the upper frequency limit of the synthesized speech from converter 13 would be 5KHz. Of course, the data rate may be altered, if desired, as a matter of design choice. For instance a 8KHz data rate would result in a synthesizer having an upper frequency response of 4KHz.

Referring now to Figures 2a and 2b, there is shown a block diagram of lattice filter 10.

In Figure 2a lattice filter 10 is shown as comprising ten stages, S1--S10, each of which is equivalent to the stage depicted in Figure 2b. For ease of illustration, only three of the stages are shown in detail in Figure 2a. The input to the stage S10 is the excitation signal 11 and the output 12 from the stage Sl is applied to converter 13 (Figure la). It will be appreciated by those skilled in the art that the output 17 from the S, stage is not utilized and therefore adder 17a and multiplier 17b in that stage may be deleted, if desired.

Referring now to Figure 2b, there is shown a single stage S, of lattice filter 10.

An input to this stage, Yn+l(i), is applied as one input to an adder 18, the output of which is Y,(i). The other input to adder 18, which is applied to a subtraction input of adder 18, is derived from the output of a multiplier 19 which multiplies the coefficient Kn times the output from a delay circuit 22, which output is b,(i-l). The output from delay circuit 22 is also applied to an adder 21 which also receives as an input the output from a multiplier 20.

Multiplier 20 multiplies the coefficient times the output from adder 18, which is, of course, Yn(i). The output from adder 21 is bn+l(i). As can be seen, the sub subscript of the Y and b data defines the stage in which that data is utilized while the number appearing in the parentheses indicates the cycle in which that data was generated. Delay circuit 22 provides a one time cycle delay function, such as may be supplied by a shift register, for example. Once each time cycle a new data point U(i) (or Yll(i)) is provided to stage Sl0 as the excitation signal 11.Thus, for each stage in lattice filter 10, two multiplications and two additions must be accomplished during each cycle, that is, given the data rates depicted in Figure lb, those four operations must be accomplished in 100 microseconds in each stage of lattice filter 10. As a matter of design choice, lattice filter 10 in Figure 2a is shown as having ten stages; however, it will be appreciated by those skilled in the art, that the number of stages may be varied as a design choice according to the quality of sound desired to be synthesized by lattice filter 10. It has been found that a ten stage lattice filter 10 can synthesize speech which is virtually indistinguishable from actual human speech.

It will be appreciated then that during any given time cycle, the ten stage lattice filter 10 must accomplish twenty multiplications and twenty addltion/subtraction operations.

It should be further appreciated that those operations cannot all be accomplished simultaneously, inasmuch as, Ylo must be calculated before Y9, which must be calculated before Y8, etc., during any given time cycle. Also during the same time cycle, b10-b1 data must be calculated and stored in the delay circuits 22 of each stage for use during the next time cycle. The Y and B data defined with respect to Figure 2b, is also shown for stages Si, S9, and S,, in Figure 2a. Equations expressing the relationship between the various Y and b data are set out in Table I.It should be appreciated that Y and b data as well as the coefficients Kn are multi-digit numbers; that coefficients K1-K10 may vary between a decimal equivalent of plus and minus one and are periodically updated in a manner to be described.

Referring now to Figure 3, there is shown, in representative form, various intermediate results attained from the multipliers and adders of lattice filter having N stages, the horizontal axis depicts time while the vertical axis represents the various stages of an N stage lattice filter 10. In the Nth stage, for example, the intermediate results, Kn.bn and Kn.Yn, which may be generated by multipliers 19 and 20 (Figure 2b), respectively, and intermediate results Y and bn+I, which may be obtained from adders 18 and 19 (Figures 2b), respectively, are shown.Timewise, the intermediate resultKn.bn must be generated before Yn may be obtained; Yn must be generated before Kn.Yn may be generated; and Kn.Yn must be generated before bn+l may be produced. According to the depicted time scale, addition operations are shown as taking a five microsecond time period while the multiplication operations take a longer time period. As to the relationship of the generation of the intermediate results with respect to the different stages, it can be seen that the b1 output from an add operation must be available before the Kn.bn multiply operation is initiated, as is depicted by arrow 25. This fact necessitates that a "no operation" period 23 be inserted between the bn+l add operation and the -Kn.bn multiply operation, if only one add operation and one multiply operation are to be initiated during any given five microsecond time period, as can be seen from Figure 3. "No operation" periods 24 are inserted after the other add operation before the following multiply operation for symmetry purposes. Thus, it can be seen that the operations indicated in all the stages of an N stage lattice filter may be accomplished concurrently in the order depicted in Figure 3 and appropriate intermediate results will become available as needed. Figure 3 depicts the general nature and applicability of the digital implementation of a multi-stage lattice filter to be described.It is to be appreciated that the representation of Figure 3 shows those operations accomplished during one of the aforementioned time cycles. The five microsecond time period for an add operation is selected as a design choice because of its compatibility with P-channel MOS integrated circuits. Of course, other time periods may be used if desired.

Referring now to Figures 4a and 4b, there is shown a representation similar to Figure 3; however, the Figures 4 representation is for a digital implementation of an equivalent ten stage lattice filter 10 and the horizontal time axis has been increased to show more than one time cycle. Further, the time cycle has been broken down into twenty time periods, Tl-T20, each of which preferably has a duration on the order of five microseconds; as has been previously mentioned, other durations may be selected. Also in Figures 4, the time cycles, e.g., i-l, i and i+l, are indicated for ease in comparing the availability of intermediate results in filter 10 with the requirements set out by the mathematical formula representation of filter 10 in Table I.

At the first time period, Tl, the excitation data U is applied as an input; the output of the filter, Yl, becomes available at time period T11. It can be seen by comparing Figures 4 and Table I that the various inputs required for the multiply operations are available when needed and that the various inputs for the add operations are also available when needed. It can further be seen from Figures 4 that an add operation (which preferably takes one time period) is initiated and completed every time period and a multiply operation is similarly initiated (and completed) every time period although the particular multiply operation then being initiated will not be completed for eight time periods. The apparatus for performing these operations will be described in detail with respect to Figures 5, 9 and lOaHI.

It has been mentioned that a multiply and an addition operation are each initiated preferably each time period. In fact, the number of time periods in a cycle preferably equals twice the number o stages in the equivalent lattice filter. Thus for eight or twelve stage lattice filters, the equivalent digital filter preferably has sixteen or twenty-four time periods per cycle, respectively. It should be evident from examining Figures 3 and 4, that the number of time periods allotted for the multiply operation depends, in part, on the number of time periods in a cycle. Thus, eight time periods may be used for multiply operations in a ten stage equivalent digital filter while six time periods may be used for multiply operations in an eight stage equivalent digital filter, if the digital equivalent filter scheme of Figures 3 and 4 is followed.It should be evident to those skilled in the art, however, that the number of time periods for multiply operation tends to dictate the number of bits which may be multiplied, i.e., tends to limit the number of bits used to represent the Kn coefficients. In most applications, the number of bits allotted to the Kn coefficients by following the processing scheme of Figures 3 and 4 will yield very acceptable synthesized speech. If, however, even greater accuracy is desired in representing the Kn coefficients, a multiply and a addition operation may not be initiated every time period of a cycle and some delay should be inserted at some point during the cycle. Of course, then the cycle would take a longer time to complete, thereby lowering the data rate (and frequency response) of the system. system.

As can be seen from Figures 4, and Kio.Yio and Bll intermediate results are obtained or may be obtained; however, as mentioned with respect to Figure 2a, these particular intermediate results are not required for a digital implementation of the lattice filter. It will be seen with respect to Figures 5, however, that the K10.Y10 and b" intermediate results (or some other numbers) are often more easy to generate (and ignore) than it is to be inhibit the apparatus from making these calculations.

Further, it will be subsequently described how the multiply operation performed by multiplier 18 (Figure 1) may be accomplished in lieu of calculating K,,.Y,, by the apparatus.

In Figure 5 there is shown a block diagram of a digital implementation of an equivalent lattice filter 10. The filter includes an array multiplier 30, adder/subtractor circuit 33, one period delay circuit 34, a shift register 35, and a latch member 36. The data inputted to and outputted from these various units at each of the twenty time periods T1--T20 (for an equivalent ten stage lattice filter) are listed in Figure 6.

Referring now to Figures 5 and 6, array multiplier 30 accomplishes the multiplications performed by multipliers 19 and 20 (Figures 2a and 2b) in each of the stages of the lattice filter. The array multiplier receives the coefficients K,--K,,, which are stored in K-stack 31, via lines 32 and either Y or b data via bus 40. K-stack 31 preferably comprises ten shift registers, each of which has ten stages.

The data stored in K-stack 31 is depicted in Table II and transmitted to array multiplier 30 via lines 32. Array multiplier 30 initiates a different multiplication operation every time period (as indicated by Figure 4) i.e., approximately every five microseconds.

Array multiplifier 30, as will be seen with respect to Figure 9 preferably has eight stages; a series of addition and shift operations accomplished as the data propagates through these eight stages, the data is multiplied by the appropriate Kn coefficient stored in K-stack 31. The multiply operation takes 40 microseconds; however, since a new multiplication operation is initiated every five microseconds, eight multiplications are in various stages of completion at any given time. The eight time period computation period of array multiplier 30 can be seen with respect to the multiplier inputs and outputs in Figure 6. For example, the multiplier inputs at time period Tl are outputted from multiplier eight time periods later, at T9. The coefficients stored in Kstack 31 are stored as a nine bit number plus an additional bit for sign information.As aforementioned, these nine bit numbers range from -1 to +1, (decimal equivalents), which, as will be seen, simplifies the structure of array multiplier 30.

The output of array multiplier 30 is applied to adder/subtractor circuit 33. This output, in the preferred embodiment, is a thirteen bit parallel channel: twelve bits of data and one bit for sign information. It will be appreciated those skilled in the art, moreover, that the number of bits in the data channel are a design choice. The other input to adder/subtractor circuit is provided from (1) the excitation signal 11 at time period Tl, the output of adder/subtractor circuit 33 during time periods T2--T10, the output of shift register 35 during time periods TI l-Tl9 and the output of latch 36 at T20.The particular input to adder/subtractor circuit 33 is shown, for ease of illustration, as being controlled by various single-pole, single throw switches 37a-37d; however, it should be appreciated that solid stage switches would preferably be used to perform these switching functions, as well as the other depicted switching functions.

The ouvt of adder/subtractor circuit 33 is applied to switch 37b, switch 38a and as the input to one period delay circuit 34. The output from adder/subtractor circuit 33 is also a thirteen bit wide parallel channel which is delayed by one time period in circuit 34 before being applied as the input to shift register 35 and to switch 38b. Shift register 35 stores the data from the thirteen bit wide channel in thirteen shift registers, each of which as eight stages. Shift register 35 is arranged to perform shift operation only during time periods T12-T2. The output of shift register 35 is applied to switch 37c and switch 39. Switch 39 closes at time period T20 for clocking the output of the filter, Yl, into latch memory 36.The output 12 of latch memory 36 is applied to analog to digital converter 13 (Figure la) and to switches 37d and 38c.

Switch 37b is closed during time periods T2-T10, switch 37c is closed during time periods Tl l-Tl9 and switch 37d is closed at time period T20. Switch 38a is closed during time periods Tl3Tl, switch 38b is closed between time periods T3--T12 and switch 38c is closed for time period T2. The other sides of switches 38a, 38b and 38c are connected to the input to array multiplier 30 via bus 40.

In Figure 6 there is listed the various intermediate results occurring in the circuit of Figure 5 during time periods Tl-T20.

Referring briefly to Figure 6, it can be seen that one of the multiplier inputs is the Kn coefficient information while the other input varies according to which switch 38a-38c is closed. At time period Tl switch 38a is closed, as aforementioned, so that the output of the adder/subtractor 33, in this case b2(i-l), is applied as a multiplier input.

At the same time the other adder input is the excitation signal U(i). At time period T2, the other multiplier input is b1(i-l) which, according to Figure 5, is being loaded from the output of latch 36 via switch 38c. The output of latch 36 according to Figure 6 is then Yi(i-1), but recalling the last entry in Table I, it is to be remembered that Bi(i-l) is set equal to a delayed Yl(i), i.e., Y,(i-l). Also at time period T2, the other adder input is that which is being currently outputted at the adder output, i.e., in this case, Y,,(i). At time period T3 the multiplier inputs are Kic and Yio(i), which is derived from the output of one period delay circuit 34. Of course, the results of this multiplication will not be available until time period Till, at which time it will be provided as one of the inputs to adder/subtractor circuit 33. At time period Tl l the other input to adder/subtractor circuit 33 is taken from the output of shift register 35.The first term loaded from shift register 35 is the b,,(i-l) term which was first outputted from shift register 35 at time period T2 and remainder at the output thereof since register 35, as aforementioned, does not shift between time periods T3 and T11.

At time period T13 the input to array multiplier 30 is again provided from the output of adder/subtractor circuit 33 via switch 38a. At time period T20 the Yl(i) term is outputted to latch memory 36 from shift register 35 and the current output of latch 36, Yi(i-1) is applied to the other input to adder/subtractor circuit 33 via switch 37d for providing the bi(i-l) term, as aforementioned. Latch memory 36 stores the filter output (Yi) for one cycle.

Referring to Figure 11 a filter similar to that of Figure 5 is shown. This filter is equivalent to a N-stage filter but uses an Mstage multiplier (e.g., these may be M+2 bits in the Kn coefficients). A shift register having a delay equivalent to N-M-2 time periods is inserted between adder/subtractor circuit 33 and one period delay circuit 34. The connection to switch 38A is then made from the output of the added shift register and the delay associated with shift register 35 should then be set equal to N+M-l. The embodiment of Figure 5, is in fact a special case of the embodiment of Figure 1 r in which N-M-2 is equal to zero, so no delay is required in that embodiment between the adder subtractor 33 and the one period delay circuit 34.

As can be seen, the equivalent ten stage lattice filter of Figures 5 and 6 performs the filtering operation required by the lattice filter 10 of Figure la at reasonable data rates. For example, in the preferred embodiment, excitation data 11 is applied at a ten kiloherts rate (i.e. every 100 microseconds) and the basic addition operations in adder/subtractor circuit 33 as well as in array multiplier 30 and the shift operations in one period delay circuit 34 and shift register 35 are accomplished in nominal five microsecond time periods. As is well known to those skilled in the art, such speeds are well within the speed capabilities of P-channel MOS large scale integration devices so that the filter of Figure 5 may be incorporated in a relatively inexpensive P-channel MOS LSI speech synthesis or complex waveform generation chip.

It should also be evident to those skilled in the art, that the basic arrangement of the ten stage equivalent lattice filter of Figure 5 is also applicable to digital filters equivalent to lattice filters having other numbers of stages. Ten stages were selected for the preferred embodiment of the filter, inasmuch as ten stage lattice filters for linear predictive coding speech synthesis circuits have been selected as the standard for use by the Department of Defense of the United States Government. However, should those wishing to practice this invention desire to utilize a digital lattice filter having a different number of equivalent stages, it is noted that the number of time periods into which a cycle is divided should at least equal to twice the number of equivalent stages.Thus, in the preferred embodiment, the number of time periods (twenty) equals twice the number of equivalent stages (ten). The, for example, if a twelve stage equivalent filter were desired, the number of time periods per cycle should be at least twenty-four and the basic design heretofore described would merely be expanded. It is noted that for a twelve stage equivalent digital lattice filter that the array multiplier 30 thereof could utilize ten time periods to complete a multiplication if the basic scheme heretofore described is followed i.e., one addition and one multiplication operation is initiated each time period. This can be seen from Figure 3 by setting N equal to twelve and completing the Figure 3 diagram accordingly.Of course, if the five microsecond period for each time period were maintained, the data rates which may be accommodated by the twelve stage version would be less than that for the ten stage version of the filter. It should be also noted that by increasing the delay time through the array multiplier 30, that the number of bits in the K1 -K1 coefficients could be increased from a total of ten bits to a total of twelve bits.

Similarly, if an eight stage equivalent digital filter were desired, the number of time periods in a cycle would then be at least sixteen and by setting N equal to eight in Figure 3 it can be seen that the propagation time through multiplier 30 would then be six time periods. In that case, using the array multiplier, which is subsequently discussed in detail, would limit the number of bits in the coefficients from K-stack 31 to having no more than eight bits. However, as was previously mentioned with respect to Figure 4, even more time periods may be used to accomplish a multiply operation in certain embodiments. This may be desired here, as a design choice, if additional accuracy is desired in the Kn coefficients.The additional accuracy would require more bits in the Kn coefficients, which in turn, requires more delay through array multiplier 30. The basic design of equivalent filter of Figure 5 would be modified somewhat because then a multiply and an addition operation would not be initiated every time period. It should be evident to those skilled m the art, that in that case, some of the intermediate results obtained within the filter would have to be stored temporarily, thereby, requiring additional storage elements to be included in the filter of Figure 5. While such modifications are not spelled out here in detail, such modification to the digital implementation of lattice filter should be within the skill of knowledgeable digital circuit designers.

It has previously been mentioned that the Kic.Yic(i) and b11(i) intermediate results are generated by the digital filter of Figure 5, but these intermediate results are not utilized inasmuch as they are not required to implement lattice filter 10 of Figure la.

Now, recalling that the data (V) from the voicing or unvoicing source is multiplied by an amplification factor (A) by a multiplier 18 in the conventional speech synthesis circuit of Figure la, it has been found that this multiplication may be done by array multiplier 30 during the time that K10.Y10(i) would otherwise be generated by the array multiplier. An embodiment of the digital filter performing this multiPlication V(i). A is shown in Figure 1. In Figure 8, there is shown the various intermediate results generated in the circuit of Figure 7.

Referring now briefly to Figures 7 and 8, it can be seen that this circuit (including the intermediate results generated thereby) is similar to the circuit of Figure 5, with the following modifications. The identification numerals of Figure 7 are generally the same as used in Figure 5, but have a prime added thereto for ease of identification. The data (V) to be multiplied by multiplication factor A is applied to one input of array multiplier 30' via a switch 38d' at time period T3 in lieu of applying the output of the one period delay circuit 34 at that time.

At time period Tl l, when the multiplication has been completed to form U(i+l), i.e., A.V(i+l), logical zeroes are inputted to the other input of adder/subtractor circuit 33' in lieu of inputting the b10(i-1) in data from shift register 35. Also, of course, both Kn coefficient data and A amplification data must be inputted to K-stack 31'. As can be seen from Figures 7 and 8, this embodiment incorporates the function performed by multiplier 18 (Figure la into the digital implementation of lattice filter 10. The data storage in K-stack 31' is depicted in Table III. The amplification factor A is preferable updated at the same rate as the Kn coefficients are updated in K-stack 31'.

Referring now to Figure 9, there is shown, in block diagram form, array multiplier 30. Lines 32-1 through 32-9 receives the least significant through most significant, respectively, bits of coefficient data from K-stack 32. On lines 32-10 is received the sign data from K-stack 31.

Another input to array multiplier 30 is received via bus 40. Lines 40-1 through 40-12 of bus 40 carry the least significant through most significant bits, respectively, and line 4012 carries the sign of the data on bus 40.

In Figure 9, there is an array of elements having reference letters A, B, C, or D (the elements with no reference letter are also "A" type elements, e.g., also correspond to Figure 10a) These elements A-D, correspond to the circuits of Figures 10a--10d, respectively. Referring briefly to Figures 10a--10d, the circuits thereof are each enclosed via a dashed line with certain conductors extending across the dashed line. The relative position of the conductors extending across the dashed line of Figures 10a-1 correspond location-wise to the conductors contacting elements A-D in Figure 9. In Figure 9, the elements are arranged in eight rows and twelve columns.

The eight rows correspond to the eight previously mentioned eight stages of array multiplier 30. These stages are identified on the right-hand side of Figure 9 and include the eight shift register cells 51 coupled to lines 40-13. The twelve columns correspond to the twelve bits of numeric data (on lines 40-1 through 40-12) inputted to array multiplier 30. The data on lines 40I through 40-13 propagates through array multiplier 30 stage-by-stage in a shift register fashion as it is being multiplied in array multipiier 30. Thus, the propagation time through any given stage is on the order of the aforementioned five microseconds or so.

Lines 32-1 from K-stack 31 is coupled to one input of twelve AND gates 52-1 through 52-12, the other input of each one being connected to lines 40-1 through 4-12, respectively. The outputs of AND gates 52-12 through 52-1 are applied to the partial sum inputs of the type A and B elements of stage 1 (See Figures 10a and lOb).

Lines 32-2 through 32-8 are coupled to the K-stack inputs of the A type elements (Figure 10a) in stages 1--7, respectively, of array multiplier 30. Line 32-9 is coupled to the input therefrom in the C type elements of stage 8 (See Figure 10c). The data on lines 41 through 40-12 is coupled to the "data-in" inputs of the stage 1 elements and coupled therethrough to stage 2 through stage 8 elements by the "date-out,' terminals of those elements. The partial sum input in the stage 1 elements is derived from the outputs of AND gates 52-1 through 52-I 2 and in the following stages is derived from the partial sum output from the next most significant bit, with the exception of the partial sum input of element in the most significant bit position in which case the partial sum input is derived from the carry output from the most significant bit position in the prior stage. Otherwise, the carry-out connections from the elements are connected to the carry-in elements in each stage.

Referring now briefly to Figure 10a, the data from K-stack 31 determines whether the "partial sum" is to be directly connected to the "partial sum" via a transfer gate 60 or to the output from exclusive OR gate 62 via a transfer gate 61.

An AND gate 63 and an exclusive OR gate 64 are responsive to the data on "data-in" and "partial sum in". Exclusive OR gate 62 is responsive to the output from exclusive OR gate 64 and to "carry-in". An AND gate 65 is responsive to the output of exclusive OR gate 64 and to "carry-in" and the output thereof is provided along with the output from AND gate 63 to an OR gate 66, whose output is "carry-out." "Data-out" corresponds to "data-in" delayed by a shift register section 67 comprising two inverters, for instance. As can be seen from Figure 10c, a C type element is identical to an A type element with the exception that no "data-out" connection is provided nor is a shift register 67 provided.

In Figure 10b, a B type element is shown which merely provides a "data-out" connection coupled to a shift register 67' whose input is "data-in" and a "carry-out" connection provided by an AND gate 68 whose inputs are "data-in" and "partial sum in". In Figure lOd, the D type element provides merely a "carry-out" signal from an AND gate 68' whose inputs are "data-in,' and "partial sum in".

As can be seen, a new partial sum is calculated at each stage, including a necessary transfer of carry information between elements of a stage, but the "partial sum out" remains unchanged if the data on the K-stack line is a logical zero or is added to the data on "data-in" to provide the "partial sum out" if the data on the line from K-stack 31 is a logical 1. The partial sums are shifted to succeedingly less significant places as data is shifted through the array multiplier.Of course, a least significant digit position is lost in each stage of the array multiplier, but inasmuch as the Kn coefficient data from K-stack 31 corresponds to a number in the decimaal range of -1 to + I; Thus if logical zeroes appear on lines 32-1 through 32-9, the output from array multiplier 30 will be a logical zero and conversely, if the data on lines 32-1 through 32-9 are all logical ones, the data inputted on bus 40 will be outputted from array multiplier 30 unchanged.For the other possible data patterns on lines 32-1 throuh32-9, the data on bus 40 will be scaled between zero and the inputted value on bus 40 in 2' possible steps, according to the magnitude of the data on line 32-1 through 32-9.

Inasmuch as the data shifts through array multiplier 30 stage-by-stage in a shift register fashion, the data from K-stack 31 is skewed as shown in Table II and III, for instance, to assure that the appropriate bit of the appropriate coefficient arrives at the appropriate time in array multiplier 30. In Figures 10a--10e the timing pulses for operating those circuits in the aforementioned shift register fashion is not depicted here, for, as is well known to those skilled in the art such timing function may be provided by adding clocked gates to the circuits of Figures 10a--10e or by utilizing recharge and conditional discharge type logic, and therefore such timing considerations are not shown here in detail.

Referring again briefly to Figure 9, the sign data on lines 41 3 is merely delayed during the eight stage delay or array multiplier 30 via shift register elements 51 and then compared with the sign data from K-stack 31 on line 32-10 at exclusive OR gate 53, thereby providing a correct sign of the outputted data according to the normal rules of multiplication.

Referring again briefly to Figures 5 and7, the array multiplier 30 (or 30') thereof has been described in detail. The remaining elements, such as the adder/subtractor circuit 33 (or 33'), are period delay circuit 34 (or 34'), shift register 35 (or 35') and latch memory 36 (or 36') are not shown in such detail, since such conventional elements are well known. The adder/subtractor circuit 33 (or 33') receives signed data on its two inputs and should determine whether a subtraction or addition operation is called or bused on the particular sign inputted with the data.

Having described the invention with respect to several embodiments thereof, additional modification may now suggest itself to those skilled in the art.

TABLE I Equation Stage Y10(i)=Y11(i)-K10b10(i-1) 10 Y9(i)=Y10(i)-K9b9(i-1) 9 b10(i)=b9(i-1)+K9Y9(i) 9 Y8(i)=Y9(i)-K8b8(i-1) 8 b9(i)=b8(i-1)+K8Y8(i) 8 Y7(i)=Y8(i)-K7-b7(i-1) 7 b8(i)=b7(i-l)+K7Y7(i) 7 Y6(i)=Y7(i)-K6b6(i-1) 6 b7(i)=b6(i-1)+K6Y6(i) 6 Y5(i)=Y6(i)-K5b5(i-1) 5 b6(i)=b5(i-1)+K5Y5(i) 5 Y4(i)=Y5(i)-K4b4(i-1) 4 b5(i)=b4(i-1)+K4Y4(i) 4 Y3(i)=Y4(i)-K3b3(i-1) 3 b4(i)=b3(i-1)+K3Y3(i) 3 Y2(i)=Y3(i)-K2b2(i-1) 2 b3(i)=b2(i-1)+K2Y2(i) 2 Y1(i)=Y2(i)-K1b1(i-1) 1 b2(i)=b1(i-1)+K1Y1(i) 1 b1(i)=Y1(i) TABLE II Data Outputted from K-stack 31 by Time Periods K-STACK OUTPUT Time Period Bit Line T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 LSB 32-1 K2 K1 K10 K9 K8 K7 K6 K5 K4 K3 32-2 K2 K1 K10 K9 K8 K7 K6 K5 K4 K3 32-3 K3 K2 K1 K10 K9 K8 K7 K6 K5 K4 32-4 K4 K3 K2 K1 K10 K9 K8 K7 K6 K5 32-5 K5 K4 K3 K2 K1 K10 K9 K8 K7 K6 32-6 K6 K5 K4 K3 K2 K1 K10 K9 K8 K7 32-7 K7 K6 K5 K4 K3 K2 K1 K10 K9 K8 32-8 K8 K7 K6 K5 K4 K3 K2 K1 K10 K9 MSB 32-9 K9 K8 K7 K6 K5 K4 K3 K2 K1 K10 SIGN BIT 32-10 K9 K8 K7 K6 K5 K4 K3 K2 K1 K10 TABLE III Data Outputted From K-stack 31' by Time Periods K-STACK OUTPUT Time Periods Bit | Line T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 LSB 32-1 K2 K1 A K9 K8 K7 K6 K5 K4 K3 32-2 K2 K1 A K9 K8 K7 K6 K5 K4 K3 32-3 K3 K2 K1 A K9 K8 K7 K6 K5 K4 32-4 K4 K3 K2 K1 A K9 K8 K7 K6 K5 32-5 K5 K4 K3 K2 K1 A K9 K8 K7 K8 32-6 K6 K5 K4 K3 K2 K1 A K9 K8 K7 32-7 K7 K6 K5 K4 K3 K2 K1 A K9 K8 32-8 K8 K7 K6 K5 K4 K3 K2 K1 A K9 MSB 32-9 K9 K8 K7 K6 K5 K4 K3 K2 K1 A BIGN BIT 32-10 K9 K8 K7 K6 K5 K4 K3 K2 K1 A TABLE III (cont.) Data Outputted from K-stack 31' by Time Periods K-STACK OUTPUT Time Periods Bit Line T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 LSB 32-1 K2 K1 K10 K9 K8 K7 K6 K5 K4 K3 32-2 K2 K1 K10 K9 K8 K7 K6 K5 K4 K3 32-3 K3 K2 K1 K10 K9 K8 K7 K6 K5 K4 32-4 K4 K3 K2 K1 K10 K9 K8 K7 K6 K5 32-5 K5 K4 K3 K2 K1 K10 K9 K8 K7 K6 32-6 K6 K5 K4 K3 K2 K1 K10 K9 K8 K7 32-7 K7 K6 K5 K4 K3 K2 K1 K10 K9 K8 32-8 K8 K7 K6 K5 K4 K3 K2 K1 K10 K9 MSB 32-9 K9 K8 K7 K6 K5 K4 K3 K2 K1 K10 SIGN BIT 32-10 K9 K8 K7 K6 K5 K4 K3 K2 K1 K10 WHAT WE CLAIM IS: 1.Apparatus for generating data representing the instantaneous values of a signal representing speech from data representing the instantaneous values of an excitation signal the apparatus including (1) A first store for containing digital coefficients, (2) A digital feedback loop including a second store for data to enable data occurring at various different times to be available at other times, multiplier circuit means coupled to the store for multiplying by sequentially applied digital coefficients from the first store data occurring in the loop at respective selected times and producing an output, and an arithmetic unit coupled to the store for additively combining data occurring in the loop at various selected times and producing an output, (3) Means for applying to the loop data representing the instantaneous values of the excitation signal, (4) Means for extracting from the loop data representing the instantaneous values of the speech signal, the arrangement being such that in operation the apparatus simulates the efficient of a multistage digital filter, the coefficients of which corresponds to the stored digital coefficients.

2. Apparatus according to claim 1 wherein the multiplier circuit is such that in operation at any one time it has several successive multiplications at various stages of partial completion.

3. Apparatus according to claim 1 or claim 2 including switching means for directing the data from the second store to the multiplier circuit and to the arithmetic circuit at particular times and for applying said data representing the instantaneous values of the excitation signal to said loop at particular times, said times each occurring in a repetitive sequence.

4. Apparatus according to any preceding claim wherein the arrangement is such as to simulate a lattic filter.

5. Apparatus for synthesising speech including apparatus according to any preceding claim and further including a digital to analogue converter coupled to said extracting means for converting the data representing the instantaneous values

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (11)

1. **WARNING** start of CLMS field may overlap end of DESC **.

   TABLE III Data Outputted From K-stack 31' by Time Periods K-STACK OUTPUT Time Periods Bit | Line T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 LSB 32-1 K2 K1 A K9 K8 K7 K6 K5 K4 K3

   32-2 K2 K1 A K9 K8 K7 K6 K5 K4 K3

   32-3 K3 K2 K1 A K9 K8 K7 K6 K5 K4

   32-4 K4 K3 K2 K1 A K9 K8 K7 K6 K5

   32-5 K5 K4 K3 K2 K1 A K9 K8 K7 K8

   32-6 K6 K5 K4 K3 K2 K1 A K9 K8 K7

   32-7 K7 K6 K5 K4 K3 K2 K1 A K9 K8

   32-8 K8 K7 K6 K5 K4 K3 K2 K1 A K9 MSB 32-9 K9 K8 K7 K6 K5 K4 K3 K2 K1 A BIGN BIT 32-10 K9 K8 K7 K6 K5 K4 K3 K2 K1 A TABLE III (cont.) Data Outputted from K-stack 31' by Time Periods K-STACK OUTPUT Time Periods Bit Line T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 LSB 32-1 K2 K1 K10 K9 K8 K7 K6 K5 K4 K3

   32-2 K2 K1 K10 K9 K8 K7 K6 K5 K4 K3

   32-3 K3 K2 K1 K10 K9 K8 K7 K6 K5 K4

   32-4 K4 K3 K2 K1 K10 K9 K8 K7 K6 K5

   32-5 K5 K4 K3 K2 K1 K10 K9 K8 K7 K6

   32-6 K6 K5 K4 K3 K2 K1 K10 K9 K8 K7

   32-7 K7 K6 K5 K4 K3 K2 K1 K10 K9 K8

   32-8 K8 K7 K6 K5 K4 K3 K2 K1 K10 K9 MSB 32-9 K9 K8 K7 K6 K5 K4 K3 K2 K1 K10 SIGN BIT 32-10 K9 K8 K7 K6 K5 K4 K3 K2 K1 K10 WHAT WE CLAIM IS: 1. Apparatus for generating data representing the instantaneous values of a signal representing speech from data representing the instantaneous values of an excitation signal the apparatus including (1) A first store for containing digital coefficients, (2) A digital feedback loop including a second store for data to enable data occurring at various different times to be available at other times, multiplier circuit means coupled to the store for multiplying by sequentially applied digital coefficients from the first store data occurring in the loop at respective selected times and producing an output, and an arithmetic unit coupled to the store for additively combining data occurring in the loop at various selected times and producing an output, (3) Means for applying to the loop data representing the instantaneous values of the excitation signal, (4) Means for extracting from the loop data representing the instantaneous values of the speech signal, the arrangement being such that in operation the apparatus simulates the efficient of a multistage digital filter, the coefficients of which corresponds to the stored digital coefficients.
2. 2. Apparatus according to claim 1 wherein the multiplier circuit is such that in operation at any one time it has several successive multiplications at various stages of partial completion.
3. 3. Apparatus according to claim 1 or claim 2 including switching means for directing the data from the second store to the multiplier circuit and to the arithmetic circuit at particular times and for applying said data representing the instantaneous values of the excitation signal to said loop at particular times, said times each occurring in a repetitive sequence.
4. 4. Apparatus according to any preceding claim wherein the arrangement is such as to simulate a lattic filter.
5. 5. Apparatus for synthesising speech including apparatus according to any preceding claim and further including a digital to analogue converter coupled to said extracting means for converting the data representing the instantaneous values

   of a speech signal an electrical speech signal.
6. 6. Apparatus according to claim 5 and further including generator means coupled to the applying means for generating the data representing the instantaneous values of an excitation signal, wherein the generator means includes switch means for changing the excitation signal between a voiced and an unvoiced signal as jt appropriate to the speech being generated.
7. 7. Apparatus according to claim 5 or 6 further including a loud speaker coupled to the digital to analogue converter for producing audible speech.
8. 8. An integrated circuit including apparatus according to any one of claims 1 to 6.
9. 9. A method of generating data representing the instantaneous values of a signal representing speech from data representing the instantaneous values of an excitation signal and from a set of digital filter co-efficients the method including the steps of 1. taking a first set of data in sequence, 2. multiplying said data by sequentially supplied digital filter co-efficients, 3. additively combining said data with a second set of data, 4. storing said data to enable data occurring at one time to be available at another time, 5. selectively feeding back said data to provide said first and second sets of data, 6. selectively extracting said data to represent speech, 7. combining data representing the instantaneous values of an excitation signal, the arrangement being such that the method simulates the effect of passing the excitation signal through a multistage digital filter the co-efficients of which are the digital co-efficients.
10. 10. Apparatus according to claim 1 and substantially as herein described with reference to the accompanying drawings, employing the arrangement filter substantially as herein described with reference to Figure 5 or employing the arrangement substantially as herein described with reference to Figure 7, or employing the arrangement substantially as herein described with reference to Figure
11. 11.