GB1576457A

GB1576457A - Semiconductor devices

Info

Publication number: GB1576457A
Application number: GB17411/77A
Authority: GB
Original assignee: General Electric Co
Current assignee: General Electric Co
Priority date: 1976-04-26
Filing date: 1977-04-26
Publication date: 1980-10-08
Also published as: DE2718185A1; NL7704389A; JPS52139385A; NL185808C; NL185808B

Description

(54) IMPROVEMENTS IN SEMICONDUCTOR DEVICES (71) We, GENERAL ELECTRIC COM- PANY, a corporation organized and existing under the laws of the State of New York, United States of America, of 1 River Road, Schenectady 12305, State of New York, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: - This invention relates to semiconductor devices comprising a plurality of components in a single body of semiconductor material and, more particularly, to such structures specifically designed for relatively high voltage use.

Compound semiconductor devices, that is, devices with more than one semiconductor component therein, are becoming more common. There are several reasons -for this growth in usage of compound semiconductors: while semiconductor devices have become less costly, the cost of most other commodities has increased; integrated circuits make possible functions not previously performed electronically; semiconductor devices are inherently highly reliable; and semiconductor devices are light in weight and small in size. In addition, certain technological advances, such as advances in materials technology, have made evermore complex and intricate compound devices possible.

It is inevitable that with compound devices becoming more common, users desire to expand the uses of the devices beyond their traditional functions of signal sensing and processing to higher power control functions. However, there is a fundamental incompatibility between small size, closely packed semiconductor components in a compound device such as a -conventional integrated circuit, and the desire to operate such a device at a high voltage level.

The present invention provides a high voltage semiconductor device comprising a body of monocrystalline semiconductor material of one conductivity type having two substantially parallel major surfaces and having formed adjacent one major surface at least two laterally spaced apart regions of the opposite conductivity type, each of said regions having a sub-region formed therein for providing first and second active semiconductor components including at least first and second semiconductor junctions, each of said regions and the other major surface having electrical contact means thereon, there being a common border region between said laterally spaced apart regions and -the regions being surrounded on all sides except along said common border region by breakdown control means so that punch-through is achieved across said common border region before said device suffers voltage-induced breakdown.

This structure alleviates premature device breakdown inasmuch as each of the semiconductor regions functions as a field limiting ring for its neighbor, thus limiting the voltage stress appearing across the surface in the vicinity of the common border.

It will be appreciated that inasmuch as the present invention requires that the regions be closely spaced, a signifi-cant saving of semiconductor material is inherently provided.

It is preferable that the spacing between the adjacent regions be approximately equal to what would be the desired spacing for a conventional field limiting ring in a device operating at the desired voltage; Since field limiting rings operate above punch-through voltage, punch-through will occur prior to voltage-induced device breakdown. In certain compound devices where the two regions will be held at an- proximately the same voltage level, such as in a Darlington transistor, the spacing can safely be up to twice the calculated spacing for a field limiting ring. This is so because the depletion region in the Darlington configuration and punchthrough occurs in the middle of the common border region when the plasmas meet.

Another preferable feature is that the edges of the regions which are not adjacent à neighboring region be protected by some other breakdown control system. Such protection can typically take the form of conventional field limiting rings or grooves.

The present invention will be further described, by way of example only, with reference to the accompanying drawing in which: - Figure 1 is a sectional elevation view of a prior art NPN transistor; Figure 2 is a sectional elevation view of the transistor depicted in Figure 1 showing the depletion region formed therein during device operation; Figure 3 is a sectional elevation view of the transistor of Figures 1 and 2 with an added field limiting ring; Figure 4 is a schematic diagram of a Darlington configuration of two transistors; Figure 5 is a sectional elevation view of a compound semiconductor device of the present invention which embodies the Darlington configuration of Figure 4; Figure 6 is a sectional elevation view of a prior art Darlington transistor illustrating the effect of surface inversion therein; Figure 7 is a schematic diagram of another compound semiconductor device which can be made according to the present invention; Figure 8 is an isometric view of a semiconductor chip embodying the circuit illustrated in Figure 7; Figure 9 is a plan view ob the metallization employed with the chip of Figure 8: Figure 10 is a sectional elevation view of yet another compound semiconductor device embodying the subiect invention; and Figure 11 is a graph illustrating a typical relationship between the device voltage and the corresponding voltage between a device region and a surrounding field limiting ring.

Referring first to Figure 1, there is shown a sectional elevation view of a conventional transistor 10. Metallization, passivation, and mounting devices have been omitted from the drawing in order to preserve clarity.

Of primary interest is the PN blocking junction 11 between the transistor base 12 and the collector 13. During normal operation, the N-type collector 13 is connected to a source of positive potential so that the junction 11 is reverse biased.

When a PN junction is reverse biased. a depletion region forms around the junction as shown by the dotted line of Figure 2.

The depletion region in a back biased iunc- tion consist5 of positive charges on the N side of the junction and electrons on the P side of the junction. This is due to the positive potential on the collector drawing some electrons therefrom, leaving positive ions. Similarly, electrons are injected into the base region providing negative charges.

The size of the depletion region is influenced by several factors including the resistivity of the semiconductor material and the reverse bias voltage applied. Inasmuch as the collector is typically of much higher resistivity than the base, the depletion region extends quite far into the collector as indicated by the broken line in Figure 2, but only slightly into the base.

The reverse bias voltage appears on the surface of the transistor where the depletion region intersects the surface. Inasmuch as the depletion region extends only slightly into the base 12, a fair approximation is that the entire reverse bias appears on the surface across the region "A".

Thus, if surface breakdown is to occur, it will probably occur at the region "A".

Breakdown on the surface of a semiconductor device is a far more serious matter than breakdown in the interior of a device.

Referring now to Figure 3, there is shown the transistor 10 to Figures 1 and 2 with the addition of a floating annular field limiting ring 14 of P-type material, which is, generally, diffused simultaneously with the base 12. As the reverse bias voltage is increased, the depletion region exentually reaches the field limiting ring 14.

Thus, negative charges within the field limiting ring are drawn to its edge, as shown diagrammatically. Consequently, any further extension of the depletion region begins on the outside of the P-type field limiting ring. The net effect of this, as illustrated in Figure 3, is to lengthen the region "A" across which the reverse bias voltage is impressed on the surface of the device. Consequently, the likelihood of surface breakdown, as compared to bulk breakdown, is decreased.

As is well known in the art, a Darlington transistor consists of two or more transistors connected as shown in Figure 4, frequently on a single semiconductor chip. It is possible to put a single field limiting ring around each device in a Darlington, but that wastes silicon because it substantially increases the size of each transistor.

The solution of the present invention is illustrated in Figure 5 which is a Darlington shown with corresponding parts carrying the same reference numerals as in Figure 4. Still referring to Figures 4 and 5, the compound semiconductor device is formed in a body of monocrvstalline semiconductor material which defines first and second substantially parallel major sur faces. For example, the body can advantageously be a wafer of silicon. At least a major portion of the body which is adjacent the first surface is primarily of oneconductivity type, in this example, N-type, and, further, in this example, the major portion comprises essentially the entire wafer. The common collectors 13 are connected to a collector terminal 23 by collector metallization 25 on the second major surface. The base 12 of an input transistor 27 is connected to a base terminal 21. The emitter 15 of the input transistor is connected, by metallization 16, directly to the base 19 of an output transistor 28.

The emitter 18 of the output transistor is surmounted by metallization 17 and thence connected to the emitter terminal 22.

Areas of the first and second major surfaces not metallized are illustrated as being coated with a passivant, such as silicon oxide 26. The positioning and formation of such a passivant is well within the ability of those skilled in the art and need not be discussed here.

By the present invention, the two transistors 27 and 28 are positioned close enough together that the base regions act as field limiting rings for each other along their common border region on the first major surface (illustrated at the point "B" of Figure 5). It will be observed that a conventional field limiting ring 14 surrounds the periphery of the entire Darlington combination to provide protection where one region 12 or 19 has no adjacent neighbor.

As illustrated in Figure 5, after the reverse bias voltage is increased to a pride termined level, the plasmas of positive charges in the collector around the base collector junctions of the separate transistors meet and become a single plasma.

From that point on, little change in surface charge at point "B" will take place as the transistor voltage is further increased.

The plasma will extend primarily in a downward direction to accommodate increased voltage. Thus, each transistor serves as a field limiting ring for its adjacent neighbor.

The above descriptions of Figures 4 and 5 assume that the two bases 12 and 19 are at approximately equal potentials. Inasmuch as transistors are normally operated with the base emitter junction forward biased and the base collector junction reverse biased, it will be appreciated that the collector terminal 23 in Figure 4 will be the most positive of the external terminals, the base terminal 21 will be intermediate, and the emitter terminal 22 will be the most negative of the terminals. As is evident from Figure 4, the bases 12 and 19 are separated only by the base emitter junction of the transistor 27 and the metallization 16. Inasmuch as the junction is forward biased, the voltage drop there across is only a fraction of a volt and therefore it will be appreciated that the two bases 12 and 19 are, for a "high voltage" device, at approximately the same potential.

There is another benefit derived from the contemplated close spacing of components in a compound semiconductor device that should be pointed out. Referring to Figure 6, there is shown a conventional Darlington structure 30 with two transistor bases widely separated. Also shown is the collector metallization 13 and the metallization 16 running from the base of one transistor to the emitter of the second transistor. Assuming conventional bias conditions in the transistor 30, the metallization 13 is positive and the metallization 16 is negative. Only a small thin layer of oxide 31 exists under metallization 16.

Thus, a capacitor is formed between the metallization 16 and the upper surface of the silicon. Since the metallization 16 is negative, positive charges will be drawn to the region underlying that metallization as illustrated in Figure 6. The higher the bias voltage, the more positive charge is drawn to that area.

It will be recalled that the primary attribute of a P-type semiconductor is a majority of positive charges, and the primary attribute of an N-type semiconductor is a majority of negative charges. If the bias voltage of the device 30 is increased to a high enough level, the number of positive charges at the surface immediately underlying the metallization 16 will exceed the number of negative charges there and, thus, that portion of the silicon will begin to behave like P-type material. This condition effectively connects the two P-base regions with what appears to be P-type semiconductor material. This is an effect called surface inversion which is well known in the art.

The configuration of Figure 5 prevents surface inversion from taking place because once the plasmas meet (punchthrough), no further positive charge accumulates at the region "B". One skilled in the art can design the device so that punch through occurs at a lower voltage level than would be required to cause surface inversion. Thus, the device is protected from surface inversion.

A monolithic integrated circuit is shown in Figures 7-9. The circuit diagram is shown in Figure 7, and Figure 8, drawn in perspective, emphasizes the separate semiconductor regions and their doping. Figure 9, shown in plan view, illustrates the surface metallization.

The circuit is formed in a body of monocrystalline semiconductor material consisting of a substrate 50 of N+ type material upon- which an N- epitaxial layer 51 of 25-30 ohm centimeters is formed.

The layer 51 forms the collector region for all four transistors. The collector electroding is not shown, but is conventionally applied to the undersurface of the substrate 50. The substrate is square and divided into four equal areas to accommodate each of the four transistors 52, 53, 54 and 55. The areas are defined by the four base regions 56, 57, 58 and 59. The base regions are square P diffusions formed into a first major surface of the wafer. The emitters of each transistor are provided by N diffusions into the respective base diffusions. In particular, the emitter of transistor 52 is a circular dot 61 diffused into the centre of the base diffusion 56. The emitter of transistor 53 is a circular dot 62 diffused into the center of the base diffusion 57. The small angular diffusion 63 forms a feedback diode 64 shown in Figure 7. The emitter of transistor 54 is the circular dot 65 diffused into the center of the base diffusion 58. The emitter of the transistor 55 is the large L-shaped emitter diffusion 66 diffused into the base region 59. The emitter diffusion 66 is large so as to accommodate the larger current require- ments of the Darlington output transistor 55. The small rectangular diffusion 67 on the inner corner of the base diffusion 59 forms a feedback diode 68 shown in Figure 7. In practice, the first diffusions may be varied in size as desired and according to current carrying requirements.

Surrounding the base regions is a narrow field limiting ring 69 consisting of a P diffusion spaced from, but encircling, the four base regions. The spacing between the field limiting ring 69 and the base regions is calculated to assure that punchthrough occurs between them prior to device breakdown. The spacing between the several base regions along their common boundaries is preferably between one and two times the calculated spacing for the field limiting ring from the base regions.

The emitter-to-base connections of the circuit are provided by the metallization illustrated in Figure 9. The metallization is applied in a single layer and consists of four separated parts. The first part 71 interconnects the emitter of transistor 52 and the base of transistor 53. The second part 72 interconnects the emitter of transistor 53, the base of transistor 54, and the diffusion 67. The third metallization 73 intercdnnects the emitter of transistor 54 and the base of transistor 55. The fourth metallization 74 interconnects the emitter of transistor 55, the base of transistor 52, and the diffusion 63. The metallization 74 is connected to a bonded lead 77, and the metallization 72 is connected to a bonded lead 78. The metallization does not contact the field limiting ring, which floats at an intermediate potential, and permits the transistors to operate at relatively high voltages as previously indicated.

Referring now to Figure 10, there is shown another monolithic integrated circuit 80 including a transistor portion 81 and a power rectifier portion 82. A body 83 of monocrystalline silicon, having first and second major surfaces is, for example, N-type. Adjacent the first major surface, there is a P-base diffused region 84 for the transistor and the second P-diffused region 85 forming the resctifier. Diffused into the region 84 is the small N diffusion 86 forming the emitter of the transistor 81. Common collector contact metallization 87 serves both components 81 and 82. The rectifier also includes anode contact metallization 88 and the transistor includes emitter contact metallization 89 and base contact metallization 90. The nonmetallized portions of the major surfaces would generally be covered with a passivant such as silicon oxide, but such passivant has been eliminated from Figure 10 to preserve clarity. The peripheral portions of the first major surface define a conventional groove 91, commonly called a "moat groove", containing their glass passivation 92.

The compound semiconductor device 80 described above can be fabricated by conventional techniques. It will be appreciated that in the device 80 the two components 81 and 82 are closely spaced along their common border 93. The spacing along the common border 93 is calculated so that punch-through occurs between the regions 84, 85 prior to breakdown at the major surface. The portions of the regions 84 and 85 which do not share the common border 93 are protected from severe voltage stress by the groove 91 and the glass passivation 82. Thus, the device is effectively protected against surface breakdown.

Assuming that the base region 84 and the anode region 85 are at approximately equal potentials, punch-through will occur in the center of the common border region 93 as the two plasmas meet in the manner indicated above. However, it is not necessary that the regions 84 and 85 be at a common potential, although neither junction should be forward biased. If the potentials are substantially different, punch-through will still occur by a meeting of the plasmas, but the meeting may occur off centre on the common border region 93. If one of the regions 84 or 85 is clamped at essentially zero voltage, punch-through will occur when the plasma extending from the non-zero voltage region reaches the zero voltage region. However, it should be appreciated that in any of the aforementioned situations, the close spacing is effective to prevent surface breakdown.

Since the potentials of the regions 84 and 85 are not necessarily equal for the circuit illustrated in Figure 100, in order to assure that adequate protection will be provided, it is preferred to assume that the plasma may extend from only one region 84 or 85 to the other region. Thus, the common border region 93 should approximately equal the spacing which is calculated for a field limiting ring.

It has been found effective to design compound semiconductor devices such that the voltage across the common border region when the device is at its operating potential is approximately half of the voltage between the two major surfaces. Figure 11 is a graph illustrating a typical relationship between the voltage across the common border region, or between a device and a field limiting ring, versus the device voltage across the entire wafer. It will be appreciated that the common border region voltage remains approximately equal to the device voltage until punch-through is achieved. Following punch-through, the common border region voltage increasing only slightly as the device voltage is further increased. In the typical curve illustrated, when the device voltage reaches 200 volts, after a punch-through at 80 volts, the common border region voltage is at the desired 100 volts. Thus, it is desirable to design the device so that punch-through occurs at slightly less than half of the intended operating voltage, in the case of 200 volts operating voltage, punch-through beneficially occurs at approximately 80 volts.

Calculation of spacing for a given desired punch-through voltage is well within the ability of those skilled in the; art. For example, see Temple, et al, IEEE, "Proceeding on Electron Devices," ED. 22, Oct.

1975, pp. 910916; or, Leistiko, et al, Solid State Electronics, Sept. 1966, pp. 847-852.

As an example, punch-through will occur in 30 to 50 ohm centimeter N-type silicon at 80 volts across a space of approximately one half mil.

In view of the foregoing, many modifications and variations of the present invention will be apparent to those skilled in the art. It is to be understood, therefore, that the invention can be practiced otherwise than as specifically described.

WHAT WE CLAIM IS: - 1. A high voltage semiconductor device comprising a body of monocrystalline semiconductor material of one conductivity type having two substantially parallel major surfaces and having formed adjacent one major surface at least two laterally spaced apart regions of the opposite conductivity type, each of said regions having a sub-region formed therein for providing first and second active semiconductor components including at least first and second semiconductor junctions, each of said regions and the other major surface having electrical contact means thereon, there being a common border region between said laterally spaced apart regions and the regions being surrounded on all sides except along said common border region by breakdown control means so that punch-through is achieved across said common border region before said device suffers voltage-induced breakdown.

2. A high voltage semiconductor device according to claim 1, wherein said contact means are metal contacts.

3. A high voltage semiconductor device according to claim 1 or claim 2, wherein said breakdown control means comprises a groove.

4. A high voltage semiconductor device according to claim 1 or claim 2, wherein said breakdown control means comprises a field limiting ring.

5. A high voltage semiconductor device according to claim 4 which is designed to operate below a preselected voltage, wherein said field limiting ring is spaced from said regions such that punch-through occurs between said regions at less than about one half of said preselected voltage.

6. A high voltage semiconductor device according to claim 5, wherein the width of said common border region is less than about twice the spacing between said field limiting ring and said regions.

7. A high voltage semiconductor device according to claim 6, wherein the width of said common border region is about equal to the spacing between said field limiting ring and said regions.

8. A high voltage semiconductor device according to any one of the preceding claims, wherein said regions are transistor base regions.

9. A high voltage semiconductor device according to claim 8, wherein said device is a Darlington transistor circuit.

10. A high voltage semiconductor device according to any one of claims 1 to 7,

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. is clamped at essentially zero voltage, punch-through will occur when the plasma extending from the non-zero voltage region reaches the zero voltage region. However, it should be appreciated that in any of the aforementioned situations, the close spacing is effective to prevent surface breakdown. Since the potentials of the regions 84 and 85 are not necessarily equal for the circuit illustrated in Figure 100, in order to assure that adequate protection will be provided, it is preferred to assume that the plasma may extend from only one region 84 or 85 to the other region. Thus, the common border region 93 should approximately equal the spacing which is calculated for a field limiting ring. It has been found effective to design compound semiconductor devices such that the voltage across the common border region when the device is at its operating potential is approximately half of the voltage between the two major surfaces. Figure 11 is a graph illustrating a typical relationship between the voltage across the common border region, or between a device and a field limiting ring, versus the device voltage across the entire wafer. It will be appreciated that the common border region voltage remains approximately equal to the device voltage until punch-through is achieved. Following punch-through, the common border region voltage increasing only slightly as the device voltage is further increased. In the typical curve illustrated, when the device voltage reaches 200 volts, after a punch-through at 80 volts, the common border region voltage is at the desired 100 volts. Thus, it is desirable to design the device so that punch-through occurs at slightly less than half of the intended operating voltage, in the case of 200 volts operating voltage, punch-through beneficially occurs at approximately 80 volts. Calculation of spacing for a given desired punch-through voltage is well within the ability of those skilled in the; art. For example, see Temple, et al, IEEE, "Proceeding on Electron Devices," ED. 22, Oct. 1975, pp. 910916; or, Leistiko, et al, Solid State Electronics, Sept. 1966, pp. 847-852. As an example, punch-through will occur in 30 to 50 ohm centimeter N-type silicon at 80 volts across a space of approximately one half mil. In view of the foregoing, many modifications and variations of the present invention will be apparent to those skilled in the art. It is to be understood, therefore, that the invention can be practiced otherwise than as specifically described. WHAT WE CLAIM IS: -

1. A high voltage semiconductor device comprising a body of monocrystalline semiconductor material of one conductivity type having two substantially parallel major surfaces and having formed adjacent one major surface at least two laterally spaced apart regions of the opposite conductivity type, each of said regions having a sub-region formed therein for providing first and second active semiconductor components including at least first and second semiconductor junctions, each of said regions and the other major surface having electrical contact means thereon, there being a common border region between said laterally spaced apart regions and the regions being surrounded on all sides except along said common border region by breakdown control means so that punch-through is achieved across said common border region before said device suffers voltage-induced breakdown.

10. A high voltage semiconductor device according to any one of claims 1 to 7,

wherein said device is an integrated circuit and said regions - are portions of separate components.

11. A high voltage semiconductor device as claimed in claim 1 substantially as hereinbefore described with reference to and as illustrated in Figs. 5 and 7 to 11 of the accompanying drawings.