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GB1357859A - Manufacture of semiconductor devices - Google Patents

Manufacture of semiconductor devices

Info

Publication number
GB1357859A
GB1357859A GB4331172A GB4331172A GB1357859A GB 1357859 A GB1357859 A GB 1357859A GB 4331172 A GB4331172 A GB 4331172A GB 4331172 A GB4331172 A GB 4331172A GB 1357859 A GB1357859 A GB 1357859A
Authority
GB
United Kingdom
Prior art keywords
defect
defects
yield
devices
steps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4331172A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1357859A publication Critical patent/GB1357859A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

1357859 Improving a semi-conductor process INTERNATIONAL BUSINESS MACHINES CORP 19 Sept 1972 [22 Sept 1971 (2)] 43311/72 Heading H1K A process of manufacturing semi-conductor devices includes (for the several most significant defect types) the evaluation or calculation of the probability that a defect of a given type will result in a defective device; samples of the devices are inspected after each of a series of steps in the process to determine for each sampled device the actual number of defects of the given type; the probability and actual numbers of defects are used to identify the step which (in respect of that defect type) produces the lowest yield of good devices; and the operations of the critical step thus identified are changed to decrease the number of defects produced by the step. When the devices are fabricated in array on a wafer the array is divided into regions of approximately homogeneous yield and the critical step separately identifiedfor each of these regions. The regional yeilds may be normalized to provide for that step a yield value for the whole wafer. (The variations of yield between regions may arise from the presence of such factors as the commonly occurring prevalence of better yields near the centre of a wafer, or the different design density of devices in various parts of a particular wafer). In addition to their use in the monitoring of each step the individual yieldmodels (probabilities based on the several key defect types in a step) may be combined to give for the entire process an overall yield prediction which is compared with actual overall yields; if there is significant disparity the results of visual, physical, and electrical testing are used to update the yield models (probability values) used in each step. Yield prediction and assessment at both step and process level may be computer controlled. The computer may be so programmed that overall yield prediction may be based on defect data obtained after each step of a particular run as it passes through or, as a diagnostic measure of line performance at a particular time, may be based on defect data obtained for each step at the particular time. The initial probability data, for the first run of a process, in respect of the likely effect of a given defect type may be obtained from the earlier operation of related processes or may be estimated with sufficient accuracy by simulating the random presence of the defect type on a layout of the device and the counting the number of the defects which occur in critical areas of the device in the layout. The probability data is then updated during the results of the first run. The simulated random presence may be achieved by physically scattering representations of the defects on an enlarged representation of the layout. Alternatively the representations of the defects and layout and the random distribution, and the subsequent counting of devices in critical areas, may be carried out within a computer. The process steps may each comprise several sub-steps. The illustrations given are in respect of the sub-steps of a photomasking process and the main defect types involved; the same techniques are applied to the diffusion steps, &c. Typically the process is applied to integrated circuit manufacture (a circuit may take one or more months to pass through the process) but the end products could be individual transistors or diodes.
GB4331172A 1971-09-22 1972-09-19 Manufacture of semiconductor devices Expired GB1357859A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US18277971A 1971-09-22 1971-09-22
US18277871A 1971-09-22 1971-09-22

Publications (1)

Publication Number Publication Date
GB1357859A true GB1357859A (en) 1974-06-26

Family

ID=26878414

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4331172A Expired GB1357859A (en) 1971-09-22 1972-09-19 Manufacture of semiconductor devices

Country Status (2)

Country Link
FR (1) FR2154263A5 (en)
GB (1) GB1357859A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6928375B2 (en) * 2002-04-10 2005-08-09 Hitachi High-Technologies Corporation Inspection condition setting program, inspection device and inspection system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6928375B2 (en) * 2002-04-10 2005-08-09 Hitachi High-Technologies Corporation Inspection condition setting program, inspection device and inspection system

Also Published As

Publication number Publication date
FR2154263A5 (en) 1973-05-04

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee