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GB1186340A - Manufacture of Semiconductor Devices - Google Patents

Manufacture of Semiconductor Devices

Info

Publication number
GB1186340A
GB1186340A GB33042/68A GB3304268A GB1186340A GB 1186340 A GB1186340 A GB 1186340A GB 33042/68 A GB33042/68 A GB 33042/68A GB 3304268 A GB3304268 A GB 3304268A GB 1186340 A GB1186340 A GB 1186340A
Authority
GB
United Kingdom
Prior art keywords
plate
light
semi
faces
manufacture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB33042/68A
Inventor
Derek Hubert Mash
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STC PLC
Original Assignee
Standard Telephone and Cables PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Telephone and Cables PLC filed Critical Standard Telephone and Cables PLC
Priority to GB33042/68A priority Critical patent/GB1186340A/en
Priority to US832360A priority patent/US3647581A/en
Priority to DE19691931949 priority patent/DE1931949A1/en
Priority to FR696923503A priority patent/FR2016792B1/fr
Publication of GB1186340A publication Critical patent/GB1186340A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/035—Diffusion through a layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/049—Equivalence and options
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/135—Removal of substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/162—Testing steps
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Led Devices (AREA)
  • Photovoltaic Devices (AREA)

Abstract

1,186,340. Semi-conductor devices. STANDARD TELEPHONES & CABLES Ltd. 11 July, 1968, No. 33042/68. Heading H1K. At some stage during the manufacture of a semi-conductor device in a single crystal of semi-conductor material, the crystal comprises an unsupported plate thinned to less than 20 Á thickness. Such a plate is flexible, and as such is less easily broken than a thicker plate. The thin Si plate 2a illustrated originally formed part of an epitaxial layer on a thicker substrate, into which a B-doped region 3 was diffused to provide a PN junction. The substrate and, if necessary, part of the epitaxial layer were polished and etched away while the assembly was mounted on a temporary support, and the remaining plate 2a was then mounted on a support 4, e.g. of Au-coated Cu or of an insulating material. During thinning the thickness of the plate may be monitored by measuring the transmission of sodium light. The plate 2a may be thinner than the original depth of the region 3. In another embodiment the final plate constitutes part of an original wafer more than 50 Á thick in which a junction has been formed by diffusion, no epitaxy being used in this case. Junctions may be formed in plates which have already been thinned to less than 20 Á. The invention may be used in the manufacture of diodes, transistors, Si or GaAs field effect transistors or varactors, light emitting GaAs or GaAsP diodes which emit light from both faces or which have reflectors on one face to reinforce light emitted through the other face, or lightsensitive devices such as solar cells open to light on both faces. Thin plates carrying devices may be mounted on top of one another to give a high packing density. Conductors may be provided on both faces of a thin plate containing a device.
GB33042/68A 1968-07-11 1968-07-11 Manufacture of Semiconductor Devices Expired GB1186340A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB33042/68A GB1186340A (en) 1968-07-11 1968-07-11 Manufacture of Semiconductor Devices
US832360A US3647581A (en) 1968-07-11 1969-06-11 Manufacture of semiconductor devices
DE19691931949 DE1931949A1 (en) 1968-07-11 1969-06-24 Manufacture of semiconductor devices
FR696923503A FR2016792B1 (en) 1968-07-11 1969-07-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB33042/68A GB1186340A (en) 1968-07-11 1968-07-11 Manufacture of Semiconductor Devices

Publications (1)

Publication Number Publication Date
GB1186340A true GB1186340A (en) 1970-04-02

Family

ID=10347742

Family Applications (1)

Application Number Title Priority Date Filing Date
GB33042/68A Expired GB1186340A (en) 1968-07-11 1968-07-11 Manufacture of Semiconductor Devices

Country Status (4)

Country Link
US (1) US3647581A (en)
DE (1) DE1931949A1 (en)
FR (1) FR2016792B1 (en)
GB (1) GB1186340A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3713922A (en) * 1970-12-28 1973-01-30 Bell Telephone Labor Inc High resolution shadow masks and their preparation

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2217068B1 (en) * 1973-02-13 1978-10-20 Labo Electronique Physique
NL7605234A (en) * 1976-05-17 1977-11-21 Philips Nv PROCEDURE FOR MANUFACTURING A SEMI-CONDUCTOR DEVICE AND SEMI-CONDUCTOR DEVICE MANUFACTURED USING THE PROCESS.
DE2752107A1 (en) * 1976-11-22 1978-06-01 Mitsubishi Monsanto Chem ELECTROLUMINESC ELEMENT AND METHOD FOR MANUFACTURING IT
US4118857A (en) * 1977-01-12 1978-10-10 The United States Of America As Represented By The Secretary Of The Army Flipped method for characterization of epitaxial layers
NL7710164A (en) * 1977-09-16 1979-03-20 Philips Nv METHOD OF TREATING A SINGLE CRYSTAL LINE BODY.
US4649627A (en) * 1984-06-28 1987-03-17 International Business Machines Corporation Method of fabricating silicon-on-insulator transistors with a shared element
EP0213488A2 (en) * 1985-08-26 1987-03-11 Itt Industries, Inc. Process for manufacturing gallium arsenide monolithic microwave integrated circuits
US4946735A (en) * 1986-02-10 1990-08-07 Cornell Research Foundation, Inc. Ultra-thin semiconductor membranes
US4952446A (en) * 1986-02-10 1990-08-28 Cornell Research Foundation, Inc. Ultra-thin semiconductor membranes
US5234846A (en) * 1992-04-30 1993-08-10 International Business Machines Corporation Method of making bipolar transistor with reduced topography
US5334281A (en) * 1992-04-30 1994-08-02 International Business Machines Corporation Method of forming thin silicon mesas having uniform thickness
US5258318A (en) * 1992-05-15 1993-11-02 International Business Machines Corporation Method of forming a BiCMOS SOI wafer having thin and thick SOI regions of silicon
US5399231A (en) * 1993-10-18 1995-03-21 Regents Of The University Of California Method of forming crystalline silicon devices on glass
US5674758A (en) * 1995-06-06 1997-10-07 Regents Of The University Of California Silicon on insulator achieved using electrochemical etching
US6649977B1 (en) 1995-09-11 2003-11-18 The Regents Of The University Of California Silicon on insulator self-aligned transistors
US6391744B1 (en) * 1997-03-19 2002-05-21 The United States Of America As Represented By The National Security Agency Method of fabricating a non-SOI device on an SOI starting wafer and thinning the same
US6500694B1 (en) * 2000-03-22 2002-12-31 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6984571B1 (en) 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
US6563133B1 (en) * 2000-08-09 2003-05-13 Ziptronix, Inc. Method of epitaxial-like wafer bonding at low temperature and bonded structure
AUPR174800A0 (en) 2000-11-29 2000-12-21 Australian National University, The Semiconductor processing
JP4530662B2 (en) * 2001-11-29 2010-08-25 トランスフォーム ソーラー ピーティーワイ リミテッド Semiconductor texturing process
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
US20160109503A1 (en) * 2014-10-15 2016-04-21 Kabushiki Kaisha Toshiba Jig, manufacturing method thereof and test method
US12424584B2 (en) 2020-10-29 2025-09-23 Adeia Semiconductor Bonding Technologies Inc. Direct bonding methods and structures

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1380350A (en) * 1963-01-31 1964-11-27 Rca Corp Epitaxial semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3713922A (en) * 1970-12-28 1973-01-30 Bell Telephone Labor Inc High resolution shadow masks and their preparation

Also Published As

Publication number Publication date
DE1931949A1 (en) 1970-02-19
FR2016792A1 (en) 1970-05-15
FR2016792B1 (en) 1974-06-14
US3647581A (en) 1972-03-07

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
435 Patent endorsed 'licences of right' on the date specified (sect. 35/1949)
PCNP Patent ceased through non-payment of renewal fee