[go: up one dir, main page]

FR3122759B1 - Implementations et procedes de traitement de reseau neuronal dans un materiel semi-conducteur - Google Patents

Implementations et procedes de traitement de reseau neuronal dans un materiel semi-conducteur Download PDF

Info

Publication number
FR3122759B1
FR3122759B1 FR2204171A FR2204171A FR3122759B1 FR 3122759 B1 FR3122759 B1 FR 3122759B1 FR 2204171 A FR2204171 A FR 2204171A FR 2204171 A FR2204171 A FR 2204171A FR 3122759 B1 FR3122759 B1 FR 3122759B1
Authority
FR
France
Prior art keywords
neural network
methods
implementations
input
take
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR2204171A
Other languages
English (en)
Other versions
FR3122759A1 (fr
Inventor
Joshua Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Uniquify Inc
Original Assignee
Uniquify Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from PCT/US2022/027035 external-priority patent/WO2022235517A2/fr
Application filed by Uniquify Inc filed Critical Uniquify Inc
Publication of FR3122759A1 publication Critical patent/FR3122759A1/fr
Application granted granted Critical
Publication of FR3122759B1 publication Critical patent/FR3122759B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/044—Recurrent networks, e.g. Hopfield networks
    • G06N3/0442—Recurrent networks, e.g. Hopfield networks characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks
    • G06N3/0455—Auto-encoder networks; Encoder-decoder networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0464—Convolutional networks [CNN, ConvNet]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/048—Activation functions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0495—Quantised networks; Sparse networks; Compressed networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/28—Programmable structures, i.e. where the code converter contains apparatus which is operator-changeable to modify the conversion process
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/044—Recurrent networks, e.g. Hopfield networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • General Health & Medical Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Computational Linguistics (AREA)
  • Molecular Biology (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Data Mining & Analysis (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Artificial Intelligence (AREA)
  • Neurology (AREA)
  • Image Analysis (AREA)
  • Feedback Control In General (AREA)
  • Image Processing (AREA)

Abstract

Des aspects de la présente invention concernent des systèmes, des procédés, des instructions d’ordinateur et des éléments de traitement d'intelligence artificielle (AIPE) impliquant un circuit décaleur ou de la circuiterie/du matériel/des instructions d’ordinateur équivalents à celui-ci, configuré(s) pour admettre une entrée décalable dérivée de données d'entrée pour une opération de réseau neuronal ; admettre une instruction de décalage dérivée d'un paramètre quantifié logarithmiquement correspondant d'un réseau neuronal ou d'une valeur constante ;et décaler l'entrée décalable dans une direction vers la gauche ou une direction vers la droite conformément à l'instruction de décalage pour former une sortie décalée représentative d'une multiplication de la donnée d'entrée avec le paramètre quantifié logarithmiquement correspondant du réseau neuronal. Fig. 1
FR2204171A 2021-05-05 2022-05-03 Implementations et procedes de traitement de reseau neuronal dans un materiel semi-conducteur Active FR3122759B1 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US202163184630P 2021-05-05 2021-05-05
US202163184576P 2021-05-05 2021-05-05
US63/184,630 2021-05-05
US63/184,576 2021-05-05
WOPCT/US2022/27035 2022-04-29
PCT/US2022/027035 WO2022235517A2 (fr) 2021-05-05 2022-04-29 Mises en oeuvre et procédés de traitement de réseau neuronal dans un matériel semi-conducteur

Publications (2)

Publication Number Publication Date
FR3122759A1 FR3122759A1 (fr) 2022-11-11
FR3122759B1 true FR3122759B1 (fr) 2025-01-10

Family

ID=83902756

Family Applications (1)

Application Number Title Priority Date Filing Date
FR2204171A Active FR3122759B1 (fr) 2021-05-05 2022-05-03 Implementations et procedes de traitement de reseau neuronal dans un materiel semi-conducteur

Country Status (7)

Country Link
US (1) US20240202509A1 (fr)
JP (3) JP7506276B2 (fr)
DE (1) DE112022000031T5 (fr)
FR (1) FR3122759B1 (fr)
GB (1) GB2621043A (fr)
NL (3) NL2035521B1 (fr)
TW (1) TW202312038A (fr)

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5452242A (en) * 1991-11-19 1995-09-19 Advanced Micro Devices, Inc. Method and apparatus for multiplying a plurality of numbers
EP0602337A1 (fr) * 1992-12-14 1994-06-22 Motorola, Inc. Décaleur à tonneau à grande vitesse
US5777918A (en) * 1995-12-22 1998-07-07 International Business Machines Corporation Fast multiple operands adder/subtracter based on shifting
US8976893B2 (en) * 2012-06-25 2015-03-10 Telefonaktiebolaget L M Ericsson (Publ) Predistortion according to an artificial neural network (ANN)-based model
US9021000B2 (en) * 2012-06-29 2015-04-28 International Business Machines Corporation High speed and low power circuit structure for barrel shifter
US10373050B2 (en) * 2015-05-08 2019-08-06 Qualcomm Incorporated Fixed point neural network based on floating point neural network quantization
US10831444B2 (en) * 2016-04-04 2020-11-10 Technion Research & Development Foundation Limited Quantized neural network training and inference
US10410098B2 (en) * 2017-04-24 2019-09-10 Intel Corporation Compute optimizations for neural networks
US11475305B2 (en) * 2017-12-08 2022-10-18 Advanced Micro Devices, Inc. Activation function functional block for electronic devices
US10459876B2 (en) * 2018-01-31 2019-10-29 Amazon Technologies, Inc. Performing concurrent operations in a processing element
JP6977864B2 (ja) * 2018-03-02 2021-12-08 日本電気株式会社 推論装置、畳み込み演算実行方法及びプログラム
CN110390383B (zh) * 2019-06-25 2021-04-06 东南大学 一种基于幂指数量化的深度神经网络硬件加速器

Also Published As

Publication number Publication date
GB2621043A (en) 2024-01-31
DE112022000031T5 (de) 2023-01-19
GB202316558D0 (en) 2023-12-13
TW202312038A (zh) 2023-03-16
NL2038031A (en) 2024-10-21
NL2031771B1 (en) 2023-08-14
FR3122759A1 (fr) 2022-11-11
JP2024119963A (ja) 2024-09-03
US20240202509A1 (en) 2024-06-20
NL2031771A (en) 2022-11-09
JP2024119962A (ja) 2024-09-03
NL2035521B1 (en) 2024-06-27
JP2024517707A (ja) 2024-04-23
NL2038031B1 (en) 2025-04-28
JP7506276B2 (ja) 2024-06-25
NL2035521A (en) 2023-08-17

Similar Documents

Publication Publication Date Title
CN112204516A (zh) 增强的低精度二进制浮点格式化
TW202103154A (zh) 資料處理方法、裝置和電子設備
Van Dung et al. Remarks on partial b-metric spaces and fixed point theorems
CN114008658A (zh) K线形态的识别方法及电子设备
CN111936965A (zh) 随机舍入逻辑
CN117215646A (zh) 一种浮点运算方法、处理器、电子设备及存储介质
FR3122759B1 (fr) Implementations et procedes de traitement de reseau neuronal dans un materiel semi-conducteur
CN117349671A (zh) 一种模型训练的方法、装置、存储介质及电子设备
Chatzarakis et al. Oscillation of certain nonlinear impulsive neutral partial differential equations with continuous distributed deviating arguments and a damping term
CN115062299B (zh) 一种针对数据泄露的安全性检测方法、装置及电子设备
Khanh et al. On optimality conditions and duality for multiobjective optimization with equilibrium constraints
Petrova et al. Automated system for synthesis of sensors for smart cities
Riaz et al. Hyers-Ulam types stability of nonlinear summation equations with delay
Gupta et al. Some contraction With Q-function for coupled coincidence point theorem in partially ordered quasi metric spaces
Tunç et al. Integral Inequalities of Hermite-Hadamard Type Via Green Function and Applications
Pham On ε-quasi efficient solutions for fractional infinite multiobjective optimization problems with locally Lipschitz data
Andres The standard Sharkovsky cycle coexistence theorem applies to impulsive differential equations: some notes and beyond
Ginting et al. Locally conservative B-spline finite element methods for two-point boundary value problems
Healey Transcending Humean Supervenience
CN115390548B (zh) 控制回路的识别方法、装置、存储介质及电子设备
Leike et al. Indefinitely oscillating martingales
Yousaf et al. An effective approach to analyze algorithms with linear O (n) worst-case asymptotic complexity
Agwa et al. Oscillation criteria for first order forced delay dynamic equations with maxima on time scales
Long Improved bounds about on-line learning of smooth-functions of a single variable
MOHSENIALHOSSEINI SOME APPROXIMATION PROBLEMS IN G-METRIC SPACES

Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 2

PLSC Publication of the preliminary search report

Effective date: 20230505

PLFP Fee payment

Year of fee payment: 3