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FR3113327B1 - Procédé de calcul convolutif intra-mémoire et dispositif correspondant - Google Patents

Procédé de calcul convolutif intra-mémoire et dispositif correspondant Download PDF

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Publication number
FR3113327B1
FR3113327B1 FR2008286A FR2008286A FR3113327B1 FR 3113327 B1 FR3113327 B1 FR 3113327B1 FR 2008286 A FR2008286 A FR 2008286A FR 2008286 A FR2008286 A FR 2008286A FR 3113327 B1 FR3113327 B1 FR 3113327B1
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Prior art keywords
calculation method
values
memory cells
intra
convolutional calculation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR2008286A
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English (en)
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FR3113327A1 (fr
Inventor
Rosa Francesco La
Antonino Conte
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
STMicroelectronics SRL
Original Assignee
STMicroelectronics Rousset SAS
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by STMicroelectronics Rousset SAS, STMicroelectronics SRL filed Critical STMicroelectronics Rousset SAS
Priority to FR2008286A priority Critical patent/FR3113327B1/fr
Priority to US17/373,935 priority patent/US12174909B2/en
Priority to EP21186854.2A priority patent/EP3955169A1/fr
Priority to CN202110890550.5A priority patent/CN114065117A/zh
Publication of FR3113327A1 publication Critical patent/FR3113327A1/fr
Application granted granted Critical
Publication of FR3113327B1 publication Critical patent/FR3113327B1/fr
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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/15—Correlation function computation including computation of convolution operations
    • G06F17/153—Multidimensional correlation or convolution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/498—Computations with decimal numbers radix 12 or 20. using counter-type accumulators
    • G06F7/4983—Multiplying; Dividing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Biomedical Technology (AREA)
  • Databases & Information Systems (AREA)
  • Algebra (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • Neurology (AREA)
  • Biophysics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Artificial Intelligence (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Computational Linguistics (AREA)
  • Evolutionary Computation (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

Le procédé de calcul convolutif (CNVL) comprend le fait de programmer des transistors à grille flottante (FGT) appartenant à des cellules mémoire non volatile (NVM) pour les mettre à des tensions de seuil multiniveaux (MLTLVL) selon des facteurs de pondération (W11-Wnm) d’un opérateur matriciel convolutif (MTXOP). Le calcul comprend le fait d’exécuter une séquence de multiplication et accumulation (MACi) pendant une opération de lecture (SNS) de cellules mémoire (NVMij), le temps (T) écoulé pour que chaque cellule mémoire devienne conductrice en réponse à un signal de commande en rampe de tension (VRMP) fournissant la valeur de chaque produit de valeurs d’entrée (A1…An) par un facteur de pondération respectif (Wi1…Win), les valeurs des produits étant accumulées avec des valeurs de sortie correspondantes (Bi). Figure pour l’abrégé : Fig 3
FR2008286A 2020-08-05 2020-08-05 Procédé de calcul convolutif intra-mémoire et dispositif correspondant Active FR3113327B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR2008286A FR3113327B1 (fr) 2020-08-05 2020-08-05 Procédé de calcul convolutif intra-mémoire et dispositif correspondant
US17/373,935 US12174909B2 (en) 2020-08-05 2021-07-13 Method and apparatus for convolutional computation based on floating gate NVM array
EP21186854.2A EP3955169A1 (fr) 2020-08-05 2021-07-21 Procédé de calcul convolutif intra-mémoire et dispositif correspondant
CN202110890550.5A CN114065117A (zh) 2020-08-05 2021-08-04 基于浮栅nvm阵列的卷积计算方法和装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2008286 2020-08-05
FR2008286A FR3113327B1 (fr) 2020-08-05 2020-08-05 Procédé de calcul convolutif intra-mémoire et dispositif correspondant

Publications (2)

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FR3113327A1 FR3113327A1 (fr) 2022-02-11
FR3113327B1 true FR3113327B1 (fr) 2023-05-12

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FR2008286A Active FR3113327B1 (fr) 2020-08-05 2020-08-05 Procédé de calcul convolutif intra-mémoire et dispositif correspondant

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US (1) US12174909B2 (fr)
EP (1) EP3955169A1 (fr)
CN (1) CN114065117A (fr)
FR (1) FR3113327B1 (fr)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT202300011370A1 (it) * 2023-06-05 2024-12-05 St Microelectronics Int Nv Dispositivo di computazione in memoria per l'esecuzione di una operazione mac con segno
EP4474977B1 (fr) * 2023-06-05 2025-10-01 STMicroelectronics International N.V. Dispositif de calcul en mémoire pour réaliser une opération multiply-and-accumulate (mac), à bas temps d'élaboration
CN119028404B (zh) * 2024-07-16 2025-10-24 南京大学 一种针对存算一体芯片的编程方法及其装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353382A (en) * 1990-10-15 1994-10-04 California Institute Of Technology Programmable synapse for neural network applications
US9864950B2 (en) * 2014-01-29 2018-01-09 Purdue Research Foundation Compact implementation of neuron and synapse with spin switches
US9760533B2 (en) * 2014-08-14 2017-09-12 The Regents On The University Of Michigan Floating-gate transistor array for performing weighted sum computation
US10180820B2 (en) 2016-09-30 2019-01-15 HEWLETT PACKARD ENTERPRlSE DEVELOPMENT LP Multiply-accumulate circuits
US10860923B2 (en) * 2016-12-20 2020-12-08 Samsung Electronics Co., Ltd. High-density neuromorphic computing element
US10957392B2 (en) * 2018-01-17 2021-03-23 Macronix International Co., Ltd. 2D and 3D sum-of-products array for neuromorphic computing system
US10719296B2 (en) * 2018-01-17 2020-07-21 Macronix International Co., Ltd. Sum-of-products accelerator array
US10692570B2 (en) 2018-07-11 2020-06-23 Sandisk Technologies Llc Neural network matrix multiplication in memory cells
US10741568B2 (en) 2018-10-16 2020-08-11 Silicon Storage Technology, Inc. Precision tuning for the programming of analog neural memory in a deep learning artificial neural network
US10991430B2 (en) * 2018-12-19 2021-04-27 Ememory Technology Inc. Non-volatile memory cell compliant to a near memory computation system

Also Published As

Publication number Publication date
CN114065117A (zh) 2022-02-18
US20220043885A1 (en) 2022-02-10
US12174909B2 (en) 2024-12-24
EP3955169A1 (fr) 2022-02-16
FR3113327A1 (fr) 2022-02-11

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