FR3156971A1 - Membrane matrix display device and methods of implementing the device - Google Patents

Abstract

The invention relates to a matrix display device with memristors and methods for implementing the device. The device comprises a plurality of pixels (P), each comprising a memory (MEM) for storing a binary word, the memory (MEM) comprising a plurality of memristors (RMx), each intended to store a bit of the binary word. Figure for abstract: Fig. 1

Description

Membrane matrix display device and methods of implementing the device

The invention relates to a matrix display device on an active matrix screen and methods for implementing the device. This type of screen has been widely developed in recent years, particularly for liquid crystal type screens known by their English abbreviation: LCD. More recently, other types of screens using light-emitting diodes have been developed, particularly using organic diodes or micro-diodes, known by their English abbreviation: OLED, respectively µLED.

In the case of a light-emitting diode screen, each pixel in the matrix contains a storage component and a transistor which controls the power supply of the light-emitting diode according to the useful signal stored in the storage component.

It is known to drive the display analogically. More precisely, once per frame, each pixel receives a voltage representative of the brightness that the pixel must display. This voltage is stored in the storage component, for example a capacitor. For a light-emitting diode pixel, the voltage is applied to the transistor configured as a follower to power the light-emitting diode proportionally to the stored voltage.

To store the information in the storage components, the display device includes a vertical register that selects, one line after the other, the different lines of the matrix and a horizontal register where digital/analog converters are located, one per column, which generate the analog values to be stored in each storage component.

This storage operation is performed sequentially, where each row is addressed and the corresponding pixels are refreshed once per frame.

The main advantage is the low number of components per pixel, which allows for a smaller pixel size. Power consumption is also reduced. Power consumption is essentially the current drawn by the LED of the pixel in question.

This architecture has some drawbacks, such as capacitor leaks that cause image attenuation and flickering. Other drawbacks include capacitive coupling in the pixel, as well as nonlinearities and the need to compensate for nonuniformities due to the shift in the transistor threshold voltage.

To overcome certain defects, it is possible to control light-emitting diodes using pulse width modulation, known by its English abbreviation: PWM for "Pulse Width Modulation". The light-emitting diode is switched on or off for a predetermined duration. The inertia of the eye allows the user to see an average brightness equal to the ratio between the duration of the lighting of the light-emitting diode and the duration of a frame. This control mode makes it possible to overcome the offset of the threshold voltage of the transistor and the non-linearity of the response of the light-emitting diode.

Driving light-emitting diodes using pulse width modulation also makes it possible to do without a storage component in each pixel, but this requires very high frequency switching, resulting in an increase in power consumption. Patent EP3079142 B1 filed in the name of the applicant makes it possible to reduce the frequency by proposing a pulse width proportional to the weight of the bit addressed to each pixel. This technique is known as "Binary Coded Modulation" or BCM in the English literature for "Binary Coded Modulation". In the cited patent, the addressing is unconventional. However, the refresh rate still remains very high.

Another solution to keep addressing the different pixels slower is to implement pixels each having a digital storage component and a pulse width modulation controller. The storage component can include flip-flops connected in series or a static random access memory known by its English abbreviation: SRAM for: "Static Random Access Memory". The main disadvantage of this type of solution is the complexity of each pixel in which the storage component must have a capacity of the order of 10 bits, to which are added the complexity of the gates of the pulse width modulation controller.

The invention aims to overcome all or part of the problems mentioned above by proposing a display device controlled by pulse width modulation and each pixel of which includes a memory making it possible to store a binary word representative of the brightness to be displayed, the memory being produced from simple components such as memristors.

To this end, the invention relates to a matrix display device comprising a matrix of pixels organized in rows and columns, each pixel comprising:
- an elementary display component,
a first electronic switch allowing the elementary display component to be controlled between two states called: on and off,
- a memory for storing a binary word for controlling the elementary display component to display a brightness corresponding to the binary word, the memory comprising several memristors each intended to store a bit of the binary word and connected to a node of the pixel common to all memristors, the node of the pixel forming a control of the first electronic switch,
- a resistor connected between the pixel node and a reference voltage,
- a second electronic switch connected in parallel with the resistor and allowing, in an on state, to modify the resistance values of the memristors while keeping the elementary display component off and in a blocked state to turn on the elementary component according to the binary word.

Advantageously, the resistor is a second memristor.

Advantageously, the device further comprises means for applying to the node of the pixel a voltage configured to initialize the first memristors.

In a variant of the invention, the memristors are each connected between a column conductor and the node of the pixel common to all memristors.

In another variant of the invention, the device further comprises a third electronic switch connected in series with each of the memristors, for each row of pixels the third electronic switches are each controlled by a column conductor.

In another variant compatible with the first two variants, each pixel comprises a memory element arranged at the node, the memristors being connected to the node via a latch making it possible to load the memory element with the value of the bit to be displayed and to maintain this value for a duration depending on the weight of the bit.

The device may further include:
- a circuit for reading the bits of a current binary word stored in each memory,
- a circuit for comparing the bits of the current binary word with the bits of a new binary word to replace the current binary word,
- a circuit for writing the new binary word configured to be deactivated if for a given bit its value in the new binary word is equal to its value in the current binary word and to be activated if for a given bit its value in the new binary word is different from its value in the current binary word.

The invention also relates to a method for implementing a matrix display device as summarized above, in which, during an operation of storing a binary word in the memory, a voltage is applied to the elementary display component keeping it in its off state for the two states of the first electronic switch.

The invention also relates to another method for implementing a matrix display device as summarized above in which, from an operation of storing a binary word in the memory to the following storage operation, only the memristors whose associated bits have changed value receive a voltage making it possible to modify their resistance value, the memristors whose associated bits have not changed value receive a voltage not making it possible to modify their resistance value.

The invention also relates to a method for implementing a matrix display device according to the invention and in which the memristors are each connected between a column conductor and the node of the pixel common to all memristors, in this method, to store a binary word in the memory, the following steps are successively carried out for each of the lines of pixels:
- closing of the second electronic switches,
- application to each column conductor of a voltage corresponding to the value of the bit to be stored in the memristor connected to the corresponding column conductor,
- opening of the second electronic switches,
These steps are repeated for each line.

The invention also relates to a method for implementing a matrix display device according to the invention and further comprising a third electronic switch connected in series with each of the memristors, in this method, to store a binary word in the memory, the following steps are successively carried out for each of the lines of pixels:
- closing of the second electronic switches,
- selective closing of the third electronic switches and application of the value of the bit to be stored to the different memristors,
- opening of the second electronic switches,
These steps are repeated for each line.

Advantageously, for the last method mentioned, all the third electronic switches associated with memristors which must store the same bit value are simultaneously closed.

The invention also relates to a method for implementing a matrix display device according to the invention, in this method, to display on the elementary display component a brightness corresponding to the binary word stored in the memory, the following steps are successively carried out simultaneously for all the lines of pixels:
- opening of electronic switches,
- application of voltage pulses successively to each memristor,
- closing of electronic switches.

In this latter method applied to a matrix display device according to the invention and comprising the memory element, the slots are pulses whose duration is independent of the weight of the bit concerned and the pulses are separated by a duration which is a function of the weight of the bit stored in the corresponding memristor.

Advantageously, in this latter method, the storage of a binary word in the memory occurs between the pulses.

Advantageously, in this latter method applied to the display device not comprising a memory element, the voltage pulses have a duration which is a function of the weight of the bit stored in the corresponding memristor.

The invention will be better understood and other advantages will appear on reading the detailed description of an embodiment given as an example, a description illustrated by the attached drawing in which:

there FIG. 1 represents an example of a matrix display device according to the invention whose pixels comprise a memristor-based memory;

there FIG. 2 represents a variant of the display device incorporating means enabling a memory initialization cycle;

Figures 3 and 4 illustrate respectively for the display device, writing in the memory and displaying from a binary word stored in the memory;

there FIG. 5 represents a variant of the display device making it possible to reduce the electrical consumption of the memristors by placing an electronic switch in series with each of them;

there FIG. 6 represents a variant of the display device which further reduces the power consumption of the memristors by reducing the reading time of the state of each memristor;

there FIG. 7 represents a variant of the display device of the FIG. 6 enabling the voltage levels applied to an electronic switch to be stabilized, enabling the elementary display component of each pixel of the device to be switched on and off;

there FIG. 8 represents a variant of the device allowing to limit the number of writings in the memory of each pixel.

For the sake of clarity, the same elements will have the same references in the different figures.

The invention uses memristors, which are worth introducing. A memristor is a passive component whose electrical resistance value changes permanently when an adequate electrical current passes through it. The memristor allows a resistance value to be permanently stored. Among the memristors, we can cite resistive random access memories known by their acronym RRAM for “Resistive Random Access Memory”. An article by Zahoor et al. published in 2020 in the journal Nanoscale Research Letters allows you to familiarize yourself with this type of component. The title of the article is: “Resistive Random Access Memory (RRAM): an Overview of Materials, Switching Mechanism, Performance, Multilevel Cell (mlc) Storage, Modeling, and Applications”.

Other types of memristors have also been developed, such as magnetoresistive or phase-change memories. These different types of memristors have very promising characteristics, particularly in terms of speed and energy consumption. All of these memristor technologies can be implemented within the framework of the invention.

The applicant has developed an oxide-based memristor technology whose resistance can be switched between two values with a difference of more than two decades. This technology is also known by the English acronym: OxRAM for “Oxide-based Resistive Random Access Memory”. In practice, an OxRAM type memristor is a two-terminal component. After applying a positive voltage between its terminals of the order of +1.5V, the memristor has a resistance of the order of 3kΩ considered as a low impedance and subsequently called LORES and after applying a negative voltage of the order of -2.5V, the memristor has a resistance of the order of 600kΩ considered as a high impedance and subsequently called HIRES.

There FIG. 1 represents an example of a matrix display device 10 according to the invention. The device 10 comprises several pixels P organized in rows and columns. On the FIG. 1 , only one pixel P is represented. It is understood that conventional devices generally have a large number of pixels. The number of rows and the number of columns can exceed a thousand. Furthermore, the designations row and column are purely conventional and can be reversed.

Each of the pixels P comprises an elementary LED display component and a first electronic switch N1 arranged in series with the elementary LED display component. For convenience, a single elementary display component is shown here. It is also possible for each pixel to comprise several elementary display components connected in parallel in order to achieve the maximum brightness desired for the display device 10. The electronic switch N1 makes it possible to turn the elementary LED display component on and off. Any type of elementary display component making it possible to emit or reflect light radiation can be implemented, in particular a conventional light-emitting diode, an organic light-emitting diode, a micro light-emitting diode, a micro-mirror implemented in a projector forming the device 10, etc. The electronic switch N1 can be a transistor or any other type of controlled switch. The electronic switch N1 makes it possible to control the elementary LED component between two states. For an elementary LED component of the light-emitting diode type, the component emits light in a first state and does not emit light in a second state. For an elementary LED component of the micro-mirror type, the component reflects light emitted by a permanent light source of the device 10 in a first state and does not reflect light emitted by the source in a second state. For convenience, the two states will be respectively called: on and off. In practice, these are two binary states of the elementary LED display component.

Each of the pixels P comprises a memory MEM for storing a binary word for controlling the elementary LED display component between its two states. The binary word is representative of the average brightness that the pixel must display. According to the invention, the memory MEM comprises several memristors RMx for each storing a bit of the binary word. For each memristor, a first state of the corresponding bit is formed by the high impedance state HIRES of the memristor and a second state of the corresponding bit is formed by the low impedance state LORES of the memristor. The memristors have a first terminal RMxa common to all the memristors RMx and connected to a control terminal of the electronic switch N1 for modifying its state: the gate G in the case of a transistor. The common terminals RMxa connected to the gate G form a node ng1 of the pixel P. The channel of the electronic switch N1, between its drain D and its source S, still in the case of the transistor, is connected in series with the elementary LED display component. The second terminal of each of the memristors RMx, respectively RMxb, is connected to a column conductor Bx.

On the FIG. 1 , the RMx memristors and the Bx conductors are referenced with an index x varying from 0 to N-1. The memristors allow N bits of a binary word to be stored representing the average light intensity displayed by the elementary LED display component.

Each of the pixels P further comprises a resistor RB and a second electronic switch N0. The resistor RB is connected at a first of its terminals to the node ng1 and at a second of its terminals to a reference voltage, for example an electrical ground of the device 10. The electronic switch N0 is connected between the terminals RMxa common to all the memristors RMx and a reference voltage which can also be the electrical ground of the device 10. The electronic switch N0 is controlled by means of a row conductor L1i. The index i represents the rank of the row in the pixel matrix.

The electronic switch N0 allows switching from a write mode in the MEM memory by keeping the elementary LED display component off to a read mode of the MEM memory by authorizing the lit state for the elementary LED display component. Specifically to keep the elementary LED display component off, the electronic switch N0 is in the on state to keep the electronic switch N1 blocked by lowering the source gate voltage difference. To allow the LED display component to be lit, the electronic switch N0 is in a blocked state. The source gate voltage difference is then given by the voltage across the resistor RB. In addition, in its on state, the electronic switch N0 allows the passage of sufficient current in the different memristors to make them change state and therefore memorize the different bits of the binary word according to information passing on the column bus formed by the column conductors Bx. On the contrary, when the electronic switch N0 is in its blocked state, the memristors RMx and the resistor RB form a voltage divider bridge allowing the elementary LED display component to be switched on. In other words, in the blocked state, the electronic switch N0 allows the memory MEM to be read for display by the elementary LED display component via the electronic switch N1.

The resistor RB can be a conventional resistor. However, to ensure better stability of the divider bridge and to harmonize the manufacturing of the device 10, it is advantageous for the resistor RB to also be a memristor. As mentioned above, the writing of the binary word representing the brightness to be displayed is done by choosing the resistance value of each of the memristors RMx: HIRES or LORES. On the other hand, the resistance value of the memristor RB remains fixed during the writing and reading operations of the memory MEM. In practice, it is possible to retain for the memristor RB, a resistance value equal to HIRES.

Such a pixel is suitable for a monochrome display. It is possible to implement the invention for a color display device having pixels of different colors, for example red, green and blue. Each type of pixel comprises one or more elementary display components suitable for emitting the desired color.

Certain types of memristors may require an initialization cycle performed only once in the lifetime of the memristor. More specifically for OxRAM type memristors, an initialization cycle allows the creation of filaments in the memristor. This cycle can be performed outside the device 10 during the manufacture of each of the memristors. But advantageously, it is possible to provide, in the device 10, means adapted to this cycle. FIG. 2 represents an example of integration in the device 10 of means allowing the initialization cycle.

On the FIG. 2 , we find the pixel P, the column conductors Bx and the row conductor L1i. For the switch N0, the reference voltage to which it is connected can take two values, one for writing in the memory MEM and the other for initializing the memristances RMx. To do this, the device comprises for each row i of pixels, a second row conductor L2i and a switch SWPRi. The switches N0 of the row i of pixels are connected between the node ng1 of their respective pixel and the row conductor L2i. The switch SWPRi makes it possible to apply to the different row conductors L2i either the voltage of the electrical ground of the device 10 to allow writing in the memory MEM of the binary word representing the brightness to be displayed or a specific voltage Vprog-init making it possible to carry out an initialization cycle which can be carried out simultaneously for all the memristances RMx of all the pixels P of the device 10.

Alternatively, it is possible to provide means separate from the switch N0 to apply the specific voltage directly to the node of each pixel, for example by means of another switch separate from N0. However, the use of the switch N0 makes it possible to simplify the pixel P.

On the FIG. 2 , appears in the form of a timing diagram the voltage applied to the line conductor L2i when the switch SWPRi applies the specific voltage Vprog-init to it. In the first part of the timing diagram, the voltage Vprog-init takes a value –Vform allowing the creation of filaments for the different RMx memristors and then possibly a value Vreset allowing the HIRES value to be established on all the RMx memristors. It is possible to do without the application of the Vreset and define the HIRES and LORES values of the different RMx memristors during a subsequent write operation in the MEM memory.

When the resistor RB is a memristor, applying the voltage –Vform to the node ng1 of the pixel P also allows it to be initialized. In this case, applying a programming voltage to the memristor RB is mandatory to freeze its value; in the example illustrated, the voltage Vrst is applied to give the memristor RB the value HIRES.

There FIG. 3 illustrates the writing of the binary word in the MEM memory. The FIG. 3 takes up the structure of device 10 illustrated on the FIG. 2 , that is, integrating the line conductor L2i and the switch SWPRi applying the voltage of the electrical ground to the line conductor L2i. It is quite possible to implement the writing of the MEM memory in the simplified structure shown in the FIG. 1 , that is to say without means of choice of different voltages applied to the node ng1 through the electronic switch N0 when it is passing.

Each column bus is associated with two series of switches: SWDIS and SWPRO. Each series includes as many switches as Bx column conductors. Each Bx column conductor of one of the column buses is connected to a switch of the SWDIS series which allows to apply to the column in question either a reference voltage VREF or an output of one of the SWPRO switches which allows to apply to the column in question either a voltage allowing to modify the resistance value of the RMx memristor connected to the column in question or the voltage of the electrical ground allowing not to modify the resistance value of the RMx memristor. Two voltage levels denoted Vset and Vrst allow to modify the resistance value of the RMx memristor in question, respectively towards the LORES and HIRES values. It is possible to do without the third voltage level corresponding to the electrical ground. However, this voltage level allows, between two displays, to modify only the bits of the binary word having changed state. The different voltage levels can be generated by a column control module located in the device 10 at the foot of the column.

During the MEM memory programming operation, the electronic switch N0, controlled by the line conductor L1i in the high state, is on, marked ON on the FIG. 3 and the switch SWPRi applies the voltage of the electrical ground to the row conductor L2i. Thus, the voltage of the node ng1 is sufficiently low both for the elementary LED display component to remain off and to allow the programming of the MEM memory. The programming operation of the MEM memory is carried out row by row by sequentially applying to each row conductor L1i, a signal making it possible to make the switches N0 of the same row of pixels conductive. More precisely, in the embodiment shown in the FIG. 3 , the PROGi signal in a high state (HIGH on the FIG. 4 ) is sent sequentially to each row conductor L1i. When the different switches N0 of the same row i are on, the voltages corresponding to the values of the corresponding bits are applied to the different column conductors Bx.

In the example shown in the FIG. 3 , the memristor RM0 takes the value HIRES, RM1 the value LORES and RMN-1 remains unchanged. On the FIG. 3 , appear in the form of a timeline:
- the PROGi voltage applied to the line conductor L2i,
- the PROG-BN control of the SWPRO switch series,
- the voltage applied to column B1,
- the voltage applied to column B0.
To ensure that the voltages corresponding to the bit values are applied when the elementary display component is switched off, it is advantageous to successively carry out the following steps for each of the pixel lines:
- closing of electronic switches N0,
- application to each column conductor Bx of a voltage corresponding to the value of the bit to be stored in the RMx memristor connected to the corresponding column conductor Bx,
- opening of electronic switches N0,
These three steps are repeated for each row of the matrix.

We have seen previously that the programming operation is done one line after the other. The selection of a line to be programmed is carried out by closing the electronic switches N0 of the line in question, the electronic switches N0 of the other non-selected lines remaining open. For the non-selected lines, the voltage divider bridge formed by the memristors RMx and the resistor RB is then active and each memristor RMx of a column receives the programming voltage even if this voltage is not intended for it. These programming voltages could make the electronic switch N1 conductive, in particular in an unfavorable case where all the memristors RMx receive a positive voltage Vset. It is possible to provide a positive voltage value Vset compatible with maintaining the electronic switch N1 in its closed state. Alternatively, it is possible to temporarily modify the voltage Va applied to the elementary LED display component, for example by setting the voltage Va to the voltage present at the other end of the conduction channel of the electronic switch N1, in this case: VDD/2. This modification of the voltage Va during the programming operation can be carried out line by line or globally for all the lines of the matrix, including for the lines selected for programming. The voltage VDD/2 is already available in the device and therefore easily accessible. More generally, other voltage values are possible if this voltage applied to the elementary LED display component allows it to be kept in its off state for the two states of the electronic switch N1.

The duration of the MEM memory programming operation is of the order of 100ns for a line of pixels. For a high-definition 10 device comprising 1080 lines of 1920 pixels P, the total duration for the entire device is of the order of 100μs. This duration corresponds to a monochrome screen. For a color screen, each line of pixels can comprise elementary pixels of different colors. In this case, the total duration of the programming operation remains unchanged. It is also possible to produce a color display device in which each line can display only a single color. For example, for a device where three elementary colors are implemented, the duration of the programming operation is then of the order of 300μs.

After the programming operation of all the lines of the matrix, a display operation can begin. Each pixel P having received the binary word representing the brightness that the elementary display component considered must display, the display operation can be global, that is to say that all the pixels P of the device 10 display simultaneously according to the stored binary word. For a global command, all the pixels P of the device 10 receive the same signals simultaneously.

There FIG. 4 illustrates the display operation. As with the programming operation, it is possible to implement the display operation with a simplified device as shown in the FIG. 1 .

During the programming operation the switch N0 of each pixel P is on and during the display operation the switch N0 is off. This is illustrated in the FIG. 4 for the display operation where the PROGi signal, in a low state noted LOW on the FIG. 4 , is sent simultaneously to all the L1i line conductors of the device 10. The series of switches SWPRO is controlled to apply a VDD voltage to the different Bx conductors of all the column buses of the device 10.

During the display operation, a voltage pulse VDD is successively applied to each RMx memristor. The duration of the pulse depends on the weight of the bit it stores. The pulse is applied to each RMx memristor through the associated Bx column conductor. In the example shown in the FIG. 4 , the voltage pulses are controlled by the series of SWDIS switches, each switch of which allows either the VDD voltage or the VREF voltage to be applied to the column conductor Bx with which it is associated. A VDD voltage pulse is applied successively to each column conductor Bx of the same column bus. As mentioned previously, the different column buses of the matrix can be controlled simultaneously to apply the voltage pulses to them.

More precisely, the slot with the shortest duration t0 is applied to the memristor RM0 storing the least significant bit of the binary word. Then, to the memristor RM1 is applied a slot of duration t1 double that applied to memristor RM0 and so on by doubling the duration of the slots until the memristor RMN-1 storing the most significant bit of the binary word. The slot applied to the memristor RMN-1 has a duration 2 ^{N -1} .t0.

On the FIG. 4 appears, in the form of a timing diagram, the voltage applied to the line conductor L1i allowing transistor N0 to be blocked, the different pulses noted DISP BX applied successively to the different memristors RMx and the lit state noted ON and off state noted OFF of the elementary LED display component. The timing diagram also shows the programming operation where the voltage applied to the line conductor L1i allows transistor N0 to be turned on. The timing diagram also shows the application of the voltage pulses in the order of the bits of the binary word. It is possible not to respect this order. Indeed, the apparent brightness for a user is an average of the durations during which the elementary LED display component is lit on a display frame. The order in which the bits are displayed does not modify this average.

The refresh rate of the device, i.e. the inverse of the duration of a sequence comprising a programming operation and a display operation, has no influence on the average brightness displayed by the elementary LED display components. On the other hand, the power consumption of the device increases with this frequency due to the number of switching operations. It is therefore advantageous to choose the lowest possible refresh rate based on physiological parameters usually retained for a user of the device.

The values of the voltages VDD and VREF are chosen according to the ratio of the resistance values HIRES and LORES of the RMx memristors, the value of the resistance RB which, as seen previously, can be equal to HIRES and the number of RMx memristors so that, during the display operation, the elementary LED display component can be in its on state when only one of the RMx memristors has a LORES resistance value and the other RMx memristors have a HIRES resistance value and can be in its off state when the voltage VDD is applied to an RMx memristor having a HIRES resistance value while the other memristors have a LORES resistance value.

In practice, if the resistor RB is a memristor whose resistance value is HIRES, the voltage VDD can be approximately double that present at the source S of the switch N1. If a VDD voltage pulse is applied to a memristor RMx, whose resistance value is HIRES, the voltage present at node ng1 of pixel P is approximately VDD/2 and the transistor N1 is blocked because the gate-source potential difference is zero. On the other hand, with a resistance value ratio between HIRES and LORES of the order of two decades, if a VDD voltage pulse is applied to a memristor RMx, whose resistance value is LORES, the voltage present at node ng1 of pixel P is approximately VDD, the gate-source potential difference increases and the transistor N1 is conducting.

More precisely, when an RMx memristor has a high resistance value (HIRES), the bit it stores is 0 and during the display operation when it receives a VDD voltage pulse, the voltage value of node ng1 is:

V(ng1_low) = VDD RB/(RB+RMx) = VDD (HIRES/(HIRES+HIRES)) = VDD/2

By choosing VREF=VDD/2, the influence on the Vng1_low voltage of the pixel node P of the other RMx memristors is not significant. Since the source of switch N1 is at voltage VDD/2, transistor N1 is blocked (VGS=0) and the elementary LED display component is in its off state.

On the other hand, if one RMx memristor has a low resistance value (LORES, bit = 0) and the other RMx memristors have high resistance values (HIRES, bit = 1), the voltage on node ng1 is higher:

V_(ng1_high) ≈ VDD * (RB/(RB+RMx)) = VDD * (HIRES/(LORES+HIRES)).

For example, with a ratio of LORES to HIRES of 0.5%, the voltage value Vng1_high is almost equal to VDD. This causes transistor N1 to turn on, and the LED display component is in its on state.

The elementary LED display component is therefore lit only during periods when an RMx memristor having a LORES resistance value (bit=1) is addressed by its VDD voltage slot.

Given the proportionality of the different slot durations to the bit weight, the average light intensity will correspond to the digital value stored in pixel P.

The duration of the programming operation during which the elementary LED display component is in its off state must be taken into account in the average light intensity perceived by a user. Since the duration of the programming operation is very short (of the order of 100µs for a high definition device (1080 lines), it is possible to choose a much longer duration of the display operation while maintaining a high display rate. The duration of the programming operation has very little influence on the average light intensity.

In the extreme case where we want to display maximum light intensity, in other words when all the RMx memristors have a resistance value equal to LORES, when applying the different voltage slots, the voltage of node ng1 may not be sufficient to turn on transistor N1 due to the presence of N-1 memristors to which the VREF voltage is applied, tending to lower the voltage of node ng1. The voltage level of node ng1 depends on the number of bits N and the LORES resistance value. It is possible to overcome this drawback by increasing the VDD voltage, but this has two drawbacks:
- Risk of increasing the voltage of the ng1 node when the display element component must remain in the off state,
- Increased power consumption in the RMx memristors and in the RB resistor.

Regarding power consumption, even if the current flowing in the RMx memristors is low during the display operation compared to that required for the programming operation, for large device formats, the power consumption of the RMx memristors is not negligible.

It is possible to completely overcome the first drawback and significantly reduce power consumption by interrupting the flow of current through the memristors that do not receive a voltage pulse for displaying the corresponding bit.

There FIG. 5 illustrates a variant of a device providing an electronic switch NBx connected in series with each memristor RMx and controlled by the column conductor Bx associated with the memristor RMx considered. During the display operation, the voltage pulse is applied sequentially to control each electronic switch NBx and turn it on. Among the different memristors RMx, at a given instant of the display operation, only one is subjected to the voltage pulse. The memristors RMx whose corresponding electronic switch NBx is blocked therefore do not consume any current. The timing diagram of the display operation is similar to that of the FIG. 4 .

To carry out the programming and display operations, an additional column conductor NCOM is required to apply the voltage level to the RMx memristors either for their programming or for the display. More precisely, unlike in Figures 1 to 4, where the RMxb terminals are connected respectively to the different column conductors Bx, in the variant of the FIG. 5 , the RMxb terminals are all connected to the NCOM column conductor.

During the programming operation, the programming voltage is selectively applied to each RMx memristor by the additional column conductor NCOM. The RMx memristor to be programmed is selected by closing one of the NBx switches selected by the voltage of one of the SWDIS series switches.

During the display operation, a voltage equal to that of the slot is applied to the additional column conductor NCOM. The selection of the memristor RMx to apply the information it stores to be displayed is carried out by closing one of the switches NBx as during the programming operation.

A SWMOD switch allows either VDD voltage during display operation, Vset, Vrst programming voltage, or zero voltage to be applied to the NCOM column driver. The SWPRO series of switches is no longer needed.

This variant, however, has a disadvantage because it does not allow all RMx memristors to be programmed simultaneously. During the programming operation, the elementary LED display components must be switched off, which increases the risk of the device blinking phenomena (known in English literature as "blinking").

The variant illustrated on the FIG. 5 allows better control of the voltage of the ng1 node based on the value of the stored bits.

For each of the pixels, without counting the power consumption of the elementary LED display component, the power consumption of the memristors is much reduced compared to that of the pixels illustrated in FIG. 1 . In fact, only one RMx memristor is selected at a time by turning the corresponding NBx switch on. No current flows in the other RMx memristors whose corresponding NBx switches are blocked. However, the power consumption can still be significant, especially when the stored brightness is maximum or close to maximum brightness. For example, in the extreme case where for a high-definition display device, all the binary words only include bits in the high state, the power consumption excluding the elementary LED display component is of the order of 4A for OxRAM type memristors.

The programming operation can be done sequentially for each of the RMx memristors by closing the corresponding electronic switch NBx and applying to the column conductor NCOM the programming voltage Vset, Vrst or a zero voltage if the previously stored resistance value does not change. Alternatively, it is also possible to simultaneously program all the RMx memristors to receive the same voltage Vset or Vrst and then simultaneously program all the RMx memristors to receive the other of the voltages Vset or Vrst. This alternative appears on the timing diagram appearing on the FIG. 5 . The NBx electronic switches are controlled by the SWDIS switch series. For RMX memristors that do not need to change their resistance value, their NB1 switch will not switch to the on state when the two voltages Vset and Vrst are successively applied. This timing diagram also shows the application of the VDD/2 voltage to the elementary LED display component to prevent it from lighting up during the programming operation, even if the electronic switch N1 were to close due to the voltages applied to the RMx memristors.

The display operation for the variant illustrated on the FIG. 5 is done in a similar way to the variant illustrated on the FIG. 4 by applying during this operation a voltage VDD to the column conductor NCOM. The reading of each memristor RMx is done by successively applying to each electronic switch NBx a voltage pulse allowing it to close, the duration of the pulse being proportional to the weight of the bit represented by the associated memristor RMx. The application of the voltage pulse is done by means of the corresponding column conductor Bx.

There FIG. 6 illustrates another device variant that allows the power consumption of the memristors to be further reduced. In the previous variants, a current flows through the series memristors, RMx and RB, which operate as a voltage divider bridge. For a given memristor, this current flows for the duration of the pulse applied to it. This duration is all the greater as the weight of the corresponding bit is high. The variant of the FIG. 6 allows to limit the duration of the electrical consumption of each memristor to the duration of a pulse independently of the weight of the corresponding bit. For this purpose, each pixel P comprises a memory element C0 arranged at node ng1 and a latch P0 allowing to load the memory element with the value of the bit to be displayed and to maintain this value for a duration depending on the weight of the bit. The latch P0 is arranged between node ng1 and the common point of the memristors RMx.

In the example shown where the electronic switch N1 is a transistor, the memory element is for example a capacitor C0 making it possible to store a voltage making it possible either to open or to close the channel of the transistor N1 depending on the resistance value ratio between the memristor RMx and the resistor Rb. The latch is for example a transistor P0 whose channel connects the node ng1 and the common point nrb of the memristors RMx, a common point also connected to the resistor RB. The latch P0 is controlled by a line conductor L3i.

On the FIG. 6 A timing diagram appears describing the application of a pulse to each of the different Bx columns and as many simultaneous pulses (LATCH signal) on the column conductor L3i to make the transistor P0 conductive. The pulses are separated by a duration that depends on the weight of the bit stored in the corresponding RMx memristor. The duration separating the pulses is equal to the duration of the slots described using the FIG. 4 .

Between two pulses, the RMx memristors and the RB resistor do not consume any current and it is quite possible to insert the programming operation between two pulses, that is to say during the display operation. On the FIG. 6 , the programming operation occurs while the most significant bit is being displayed. It is possible to have the programming operation occur while another bit is being displayed. It is even possible to split the programming operation while several bits are being displayed.

The variant of the FIG. 6 allows both to reduce the power consumption of the RMx memristors and the RB resistor, and also to reduce the inactive time of the display for the programming operation. This second advantage takes on particular interest in the variant of the FIG. 5 where the programming of the different memristors cannot be done simultaneously. It is of course possible to implement the memory element C0 and the lock P0 in the variant shown in the FIG. 1 .

The presence of a P0 lock and a C0 memory element can also be implemented in the variant of the FIG. 1 .

There FIG. 7 illustrates different structures for producing the latch and the memory element, in particular to stabilize the high and low voltage levels present on the node ng1 in order to limit the effects of possible leakage currents on the capacitor C0. More precisely, it is possible to place between the latch P0 and the memory element an inverter produced for example by means of three transistors N2, N3 and P2. The memory element can be produced by means of a double inverter produced for example by means of four transistors P4, N4, P5 and N5.

We mentioned above the fact of not modifying the resistance value of an RMx memristor when the corresponding bit has not been modified, from one programming operation to the next, by applying to a given RMx memristor the voltage level of the electrical ground of the device, see in particular the voltage applied to the RMN-1 memristor on the FIG. 3 during the programming operation. This reduces the stress on the RMx memristors to change state and therefore increases their lifespan.

The choice of applying a zero voltage to a given memristor or applying a voltage to it allowing it to change its resistance value can be made by means of a computer comparing bit by bit the successive binary words to be stored in the MEM memories in different pixels. The comparison is made in the computer by memorizing the current binary word previously stored in each of the MEM memories in order to compare it with a new binary word to replace it. If one or more bits of the current binary word have a level identical to that of the new binary word, then the computer applies a zero voltage to the memristor(s) corresponding to the bits considered through the column conductor Bx. On the contrary, if one or more bits of the current binary word have a level different from that of the new binary word, then the computer applies the voltage either Vset or Vrst to the memristor(s) corresponding to the bits considered through the column conductor Bx. The computer can then address only the pixels whose binary word has been modified in order to reprogram them.

In such an operating mode, the rewriting of the MEM memories, and therefore the refreshing of the video image, is only done in the case of changes only on the pixels concerned. The concept of fixed video rate is therefore not applicable and the image becomes free of any flickering phenomenon or other artifacts linked to the continuous updating traditionally implemented in existing systems.

Alternatively, before a programming operation, instead of storing the current binary word in the calculator for each of the pixels P, it is possible to read the current binary word stored in the MEM memory and compare this reading with the new binary word to be stored. As before, a voltage is applied to the different memristors depending on the result of the comparison. The comparison can be made in the calculator or by means of a dedicated circuit, for example, located at the bottom of each column.

There FIG. 8 illustrates an example of a reading circuit R, a comparison circuit C, and a writing circuit W arranged at the bottom of each column and allowing respectively, the reading of the memory MEM of each pixel P, the comparison of the current and new binary words as well as the writing in the memories MEM. In order not to overload the FIG. 8 , for two pixels of two distinct lines: i and i+1, only one of the memristors is represented, in this case the one that must store the bit of rank k of the binary word, the transistor NBk and the transistor N0. Also appear on the FIG. 8 , the column conductors NCOM and Bk as well as the row conductors L2i and L2i+1.

The row i whose MEM memory is to be read is selected by means of the row conductor L2i. The SWMOD switch is in position to apply the programming voltage to the column conductor NCOM. Note that this position of the SWMOD switch here allows either reading the MEM memory or writing the bits of the new binary word to it. The choice between the reading circuit R and the writing circuit W is made by means of a switch SWRW. The reading circuit R is connected to the column conductor NCOM through the switches SWMOD, SWPRO and SWRW. The comparison is made for example by means of an operational amplifier OP connected on its inverting input to the column NCOM on which the resistor RMk of row i is connected to ground through the switch NO in the on state. The operational amplifier OP has a resistor RS in its feedback to the inverting input. The resistance value ratio of the memristor RMk and the resistor RS makes it possible to deliver at the output of the operational amplifier OP a binary information relating to the HIRES or LORES resistance value of the memristor RMk. This binary information is delivered to the comparison circuit C, for example formed by a logic cell, to be compared with the new value, called "new Bk", of the bit concerned. Then after reading and comparing a bit, the switch SWRW changes position to connect the write circuit W to the column conductor NCOM. The result of the comparison makes it possible to apply by means of the write circuit W either a zero voltage if the value of the current bit is equal to that of the new bit, the write circuit W is then considered deactivated, or the value of the new bit, Vset or Vrst if the value of the current bit is different from that of the new bit, the write circuit W is then considered activated. In other words, the write circuit W is configured to be deactivated if for a given bit its value in the new binary word is equal to its value in the current binary word. Conversely, the write circuit W is configured to be activated if for a given bit its value in the new binary word is different from its value in the current binary word.

On the FIG. 8 a truth table appears indicating the operation of the comparison and writing circuits C and W. It is understood that the circuits R, C and W represented on the FIG. 8 are only examples and can be adapted according to specific needs.

Claims (16)

Matrix display device comprising a matrix of pixels (P) organized in rows and columns, each pixel (P) comprising:
- an elementary display component (LED),
- a first electronic switch (N1) allowing the elementary display component (LED) to be controlled between two states called: on and off,
- a memory (MEM) for storing a binary word for controlling the elementary display component (LED) to display a brightness corresponding to the binary word, the memory (MEM) comprising several memristors (RMx) each intended to store a bit of the binary word and connected to a node (ng1) of the pixel (P) common to all memristors (RMx), the node (ng1) of the pixel (P) forming a control (G) of the first electronic switch (N1),
- a resistor (RB) connected between the node (ng1) of the pixel (P) and a reference voltage (GND),
- a second electronic switch (N0) connected in parallel with the resistor (RB) and allowing, in an on state, to modify the resistance values of the memristors (RMx) while keeping the elementary display component (LED) off and in a blocked state to turn on the elementary component (LED) according to the binary word. A matrix display device according to claim 1, wherein the resistor (RB) is a second memristor. Device according to one of the preceding claims, further comprising means for applying to the node (ng1) of the pixel (P) a voltage configured to initialize the first memristors (RMx). Device according to one of the preceding claims, in which the memristors (RMx) are each connected between a column conductor (Bx) and the node (ng1) of the pixel (P) common to all memristors (RMx). Device according to one of claims 1 to 3, further comprising a third electronic switch (NBx) connected in series with each of the memristors (RMx), for each row of pixels (P), the third electronic switches each being controlled by a column conductor (Bx). Device according to one of the preceding claims, in which each pixel (P) comprises a memory element (C0) arranged at the node (ng1), the memristors (RMx) being connected to the node (ng1) via a latch (P0) making it possible to load the memory element (C0) with the value of the bit to be displayed and to maintain this value for a duration depending on the weight of the bit. Device according to one of the preceding claims, further comprising:
- a reading circuit (R) of the bits of a current binary word stored in each memory (MEM),
- a comparison circuit (C) of the bits of the current binary word with the bits of a new binary word to replace the current binary word,
- a write circuit (W) of the new binary word configured to be deactivated if for a given bit its value in the new binary word is equal to its value in the current binary word and to be activated if for a given bit its value in the new binary word is different from its value in the current binary word. Method for implementing a matrix display device according to one of claims 1 to 7 in which, during an operation of storing a binary word in the memory (MEM), a voltage (va) is applied to the elementary display component (LED) keeping it in its off state for the two states of the first electronic switch (N1). Method for implementing a matrix display device according to one of claims 1 to 7 in which, from an operation of storing a binary word in the memory (MEM) to the following storage operation, only the memristors (RMx) whose associated bits have changed value receive a voltage allowing their resistance value to be modified, the memristors (RMx) whose associated bits have not changed value receive a voltage not allowing their resistance value to be modified. Method for implementing a matrix display device according to claim 4, in which, to store a binary word in the memory (MEM), the following steps are successively carried out for each of the lines (i) of pixels (P):
- closing of the second electronic switches (N0),
- application to each column conductor (Bx) of a voltage corresponding to the value of the bit to be stored in the memristor (RMx) connected to the corresponding column conductor (Bx),
- opening of the second electronic switches (N0),
These steps are repeated for each line (i). Method for implementing a matrix display device according to claim 5, in which, to store a binary word in the memory (MEM), the following steps are successively carried out for each of the lines (i) of pixels (P):
- closing of the second electronic switches (N0),
- selective closing of the third electronic switches (NBx) and application of the value of the bit to be stored to the different memristors,
- opening of the second electronic switches (N0),
These steps are repeated for each line (i). Method according to claim 11, in which all the third electronic switches (NBx) associated with memristors (RMx) which are to store the same bit value are simultaneously closed. Method for implementing a matrix display device according to one of claims 1 to 7, in which, to display on the elementary display component (LED) a brightness corresponding to the binary word stored in the memory (MEM), the following steps are successively carried out simultaneously for all the lines (i) of pixels (P):
- opening of electronic switches (N0),
- application of voltage pulses successively to each memristor (RMx),
- closing of electronic switches (N0). Method according to the preceding claim for implementing a matrix display device according to claim 6, in which the slots are pulses whose duration is independent of the weight of the bit concerned and in which the pulses are separated by a duration which is a function of the weight of the bit stored in the corresponding memristor (RMx). Method according to the preceding claim for implementing a matrix display device according to claim 6, in which the storage of a binary word in the memory (MEM) occurs between the pulses. Method according to claim 13 for implementing a matrix display device according to one of claims 1 to 5, in which the voltage slots have a duration which is a function of the weight of the bit stored in the corresponding memristor (RMx).