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FR3038774B1 - Procede de realisation d'un transistor haute tension a encombrement reduit, et circuit integre correspondant - Google Patents

Procede de realisation d'un transistor haute tension a encombrement reduit, et circuit integre correspondant Download PDF

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Publication number
FR3038774B1
FR3038774B1 FR1556470A FR1556470A FR3038774B1 FR 3038774 B1 FR3038774 B1 FR 3038774B1 FR 1556470 A FR1556470 A FR 1556470A FR 1556470 A FR1556470 A FR 1556470A FR 3038774 B1 FR3038774 B1 FR 3038774B1
Authority
FR
France
Prior art keywords
producing
integrated circuit
reduced size
voltage transistor
corresponding integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1556470A
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English (en)
Other versions
FR3038774A1 (fr
Inventor
Julien Delalleau
Christian Rivero
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
Original Assignee
STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR1556470A priority Critical patent/FR3038774B1/fr
Priority to CN201620136399.0U priority patent/CN205406528U/zh
Priority to CN201610099471.1A priority patent/CN106409905A/zh
Priority to US15/068,732 priority patent/US20170012104A1/en
Publication of FR3038774A1 publication Critical patent/FR3038774A1/fr
Priority to US15/454,184 priority patent/US9978847B2/en
Application granted granted Critical
Publication of FR3038774B1 publication Critical patent/FR3038774B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/025—Manufacture or treatment forming recessed gates, e.g. by using local oxidation
    • H10D64/027—Manufacture or treatment forming recessed gates, e.g. by using local oxidation by etching at gate locations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
FR1556470A 2015-07-08 2015-07-08 Procede de realisation d'un transistor haute tension a encombrement reduit, et circuit integre correspondant Expired - Fee Related FR3038774B1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FR1556470A FR3038774B1 (fr) 2015-07-08 2015-07-08 Procede de realisation d'un transistor haute tension a encombrement reduit, et circuit integre correspondant
CN201620136399.0U CN205406528U (zh) 2015-07-08 2016-02-23 集成电路
CN201610099471.1A CN106409905A (zh) 2015-07-08 2016-02-23 制造占地面积减少的高压晶体管的方法和对应集成电路
US15/068,732 US20170012104A1 (en) 2015-07-08 2016-03-14 Method for producing a high-voltage transistor with reduced footprint, and corresponding integrated circuit
US15/454,184 US9978847B2 (en) 2015-07-08 2017-03-09 Method for producing a high-voltage transistor with reduced footprint, and corresponding integrated circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1556470 2015-07-08
FR1556470A FR3038774B1 (fr) 2015-07-08 2015-07-08 Procede de realisation d'un transistor haute tension a encombrement reduit, et circuit integre correspondant

Publications (2)

Publication Number Publication Date
FR3038774A1 FR3038774A1 (fr) 2017-01-13
FR3038774B1 true FR3038774B1 (fr) 2018-03-02

Family

ID=54145884

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1556470A Expired - Fee Related FR3038774B1 (fr) 2015-07-08 2015-07-08 Procede de realisation d'un transistor haute tension a encombrement reduit, et circuit integre correspondant

Country Status (3)

Country Link
US (2) US20170012104A1 (fr)
CN (2) CN106409905A (fr)
FR (1) FR3038774B1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3038774B1 (fr) * 2015-07-08 2018-03-02 Stmicroelectronics (Rousset) Sas Procede de realisation d'un transistor haute tension a encombrement reduit, et circuit integre correspondant
CN109216359B (zh) * 2017-07-04 2022-06-03 华邦电子股份有限公司 存储器装置及其制造方法
CN109326595B (zh) * 2017-07-31 2021-03-09 联华电子股份有限公司 半导体元件及其制作方法
DE112017008328T5 (de) * 2017-12-27 2020-10-08 Intel Corporation Reduziertes elektrisches Feld durch Verdickung des Dielektrikums auf der Drain-Seite
CN108511518B (zh) * 2018-03-09 2024-02-06 长鑫存储技术有限公司 晶体管及其形成方法、半导体器件
KR102471277B1 (ko) 2018-09-19 2022-11-28 삼성전자주식회사 게이트 절연층을 갖는 반도체 소자
KR102671273B1 (ko) 2019-06-17 2024-06-04 에스케이하이닉스 주식회사 매립 게이트 구조를 구비한 반도체 장치 및 그 제조 방법
CN111640745A (zh) * 2019-09-04 2020-09-08 福建省晋华集成电路有限公司 存储器及其形成方法

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JPH02206175A (ja) * 1989-02-06 1990-08-15 Fuji Electric Co Ltd Ｍｏｓ型半導体装置
KR940002400B1 (ko) * 1991-05-15 1994-03-24 금성일렉트론 주식회사 리세스 게이트를 갖는 반도체장치의 제조방법
WO1999043029A1 (fr) * 1998-02-20 1999-08-26 Infineon Technologies Ag Transistor mos a grille et tranchee, son utilisation dans des systemes de memoires mortes programmables effaçables electriquement, et son procede de production
US6391720B1 (en) * 2000-09-27 2002-05-21 Chartered Semiconductor Manufacturing Ltd. Process flow for a performance enhanced MOSFET with self-aligned, recessed channel
TWI235411B (en) 2003-07-23 2005-07-01 Samsung Electronics Co Ltd Self-aligned inner gate recess channel transistor and method of forming the same
US6963108B1 (en) * 2003-10-10 2005-11-08 Advanced Micro Devices, Inc. Recessed channel
KR100663359B1 (ko) * 2005-03-31 2007-01-02 삼성전자주식회사 리세스 채널 트랜지스터 구조를 갖는 단일 트랜지스터플로팅 바디 디램 셀 및 그 제조방법
DE102005047058B4 (de) * 2005-09-30 2009-09-24 Qimonda Ag Herstellungsverfahren für einen Graben-Transistor und entsprechender Graben-Transistor
KR100668862B1 (ko) * 2005-10-25 2007-01-16 주식회사 하이닉스반도체 리세스 채널 트랜지스터 및 그 형성방법
US7655973B2 (en) * 2005-10-31 2010-02-02 Micron Technology, Inc. Recessed channel negative differential resistance-based memory cell
ITMI20052140A1 (it) * 2005-11-10 2007-05-11 St Microelectronics Srl Metodo di realizzazione di un trasnsitor mos a gate verticale con incavo con incavo di gate svasato
US7371645B2 (en) * 2005-12-30 2008-05-13 Infineon Technologies Ag Method of manufacturing a field effect transistor device with recessed channel and corner gate device
TWI302355B (en) * 2006-04-20 2008-10-21 Promos Technologies Inc Method of fabricating a recess channel array transistor
KR101061296B1 (ko) * 2010-07-01 2011-08-31 주식회사 하이닉스반도체 반도체 소자 및 그 형성 방법
US8476136B2 (en) * 2010-12-14 2013-07-02 Stmicroelectronics S.R.L. Method and a structure for enhancing electrical insulation and dynamic performance of MIS structures comprising vertical field plates
FR3038774B1 (fr) * 2015-07-08 2018-03-02 Stmicroelectronics (Rousset) Sas Procede de realisation d'un transistor haute tension a encombrement reduit, et circuit integre correspondant

Also Published As

Publication number Publication date
FR3038774A1 (fr) 2017-01-13
CN205406528U (zh) 2016-07-27
US20170179247A1 (en) 2017-06-22
US20170012104A1 (en) 2017-01-12
US9978847B2 (en) 2018-05-22
CN106409905A (zh) 2017-02-15

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