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FR3021455B1 - Procede d'aplanissement d'evidements remplis de cuivre - Google Patents

Procede d'aplanissement d'evidements remplis de cuivre

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Publication number
FR3021455B1
FR3021455B1 FR1454578A FR1454578A FR3021455B1 FR 3021455 B1 FR3021455 B1 FR 3021455B1 FR 1454578 A FR1454578 A FR 1454578A FR 1454578 A FR1454578 A FR 1454578A FR 3021455 B1 FR3021455 B1 FR 3021455B1
Authority
FR
France
Prior art keywords
evidents
filled
flowing copper
copper
flowing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1454578A
Other languages
English (en)
Other versions
FR3021455A1 (fr
Inventor
Maurice Rivoire
Viorel Balan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Crolles 2 SAS
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
STMicroelectronics Crolles 2 SAS
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, STMicroelectronics Crolles 2 SAS, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR1454578A priority Critical patent/FR3021455B1/fr
Priority to US14/706,579 priority patent/US9620385B2/en
Publication of FR3021455A1 publication Critical patent/FR3021455A1/fr
Priority to US15/447,410 priority patent/US9865545B2/en
Application granted granted Critical
Publication of FR3021455B1 publication Critical patent/FR3021455B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

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    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08121—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the connected bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/08146—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a via connection in the body
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
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    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
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    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
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    • H01L24/03—Manufacturing methods

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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US14/706,579 US9620385B2 (en) 2014-05-21 2015-05-07 Method of planarizing recesses filled with copper
US15/447,410 US9865545B2 (en) 2014-05-21 2017-03-02 Plurality of substrates bonded by direct bonding of copper recesses

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FR3021455B1 (fr) * 2014-05-21 2017-10-13 St Microelectronics Crolles 2 Sas Procede d'aplanissement d'evidements remplis de cuivre
CN115547924A (zh) * 2014-12-23 2022-12-30 太浩研究有限公司 解耦过孔填充
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
TWI892323B (zh) 2016-10-27 2025-08-01 美商艾德亞半導體科技有限責任公司 用於低溫接合的結構和方法
US10515913B2 (en) 2017-03-17 2019-12-24 Invensas Bonding Technologies, Inc. Multi-metal contact structure
US10446441B2 (en) 2017-06-05 2019-10-15 Invensas Corporation Flat metal features for microelectronics applications
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
JP2019140178A (ja) * 2018-02-07 2019-08-22 東芝メモリ株式会社 半導体装置
GB2584372B (en) * 2018-02-22 2022-04-13 Massachusetts Inst Technology Method of reducing semiconductor substrate surface unevenness
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US11244916B2 (en) 2018-04-11 2022-02-08 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10790262B2 (en) 2018-04-11 2020-09-29 Invensas Bonding Technologies, Inc. Low temperature bonded structures
WO2020034063A1 (fr) * 2018-08-13 2020-02-20 Yangtze Memory Technologies Co., Ltd. Contacts de soudage ayant une couche de capsulage et procédé destiné à les former
US11011494B2 (en) * 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11244920B2 (en) 2018-12-18 2022-02-08 Invensas Bonding Technologies, Inc. Method and structures for low temperature device bonding
EP3734652A1 (fr) 2019-05-02 2020-11-04 ams AG Dispositif à semi-conducteurs et procédé de fabrication de dispositif à semi-conducteurs
KR102898430B1 (ko) 2019-08-26 2025-12-09 삼성전자 주식회사 반도체 소자 제조 방법
US11735523B2 (en) 2020-05-19 2023-08-22 Adeia Semiconductor Bonding Technologies Inc. Laterally unconfined structure
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die
JP7783896B2 (ja) 2020-12-30 2025-12-10 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド 導電特徴部を備えた構造体及びその形成方法

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US6927113B1 (en) * 2003-05-23 2005-08-09 Advanced Micro Devices Semiconductor component and method of manufacture
US6812141B1 (en) * 2003-07-01 2004-11-02 Infineon Technologies Ag Recessed metal lines for protective enclosure in integrated circuits
US6979625B1 (en) * 2003-11-12 2005-12-27 Advanced Micro Devices, Inc. Copper interconnects with metal capping layer and selective copper alloys
JP2007035734A (ja) * 2005-07-25 2007-02-08 Nec Electronics Corp 半導体装置およびその製造方法
US8119500B2 (en) * 2007-04-25 2012-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer bonding
FR2963158B1 (fr) * 2010-07-21 2013-05-17 Commissariat Energie Atomique Procede d'assemblage par collage direct entre deux elements comprenant des portions de cuivre et de materiaux dielectriques
CN102915962B (zh) * 2012-11-12 2016-04-20 上海华力微电子有限公司 铜金属覆盖层的制备方法
US9425155B2 (en) * 2014-02-25 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer bonding process and structure
FR3021455B1 (fr) * 2014-05-21 2017-10-13 St Microelectronics Crolles 2 Sas Procede d'aplanissement d'evidements remplis de cuivre

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US9620385B2 (en) 2017-04-11
US20170179035A1 (en) 2017-06-22

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