FR2911430B1 - "procede de fabrication d'un substrat hybride" - Google Patents
"procede de fabrication d'un substrat hybride"Info
- Publication number
- FR2911430B1 FR2911430B1 FR0700265A FR0700265A FR2911430B1 FR 2911430 B1 FR2911430 B1 FR 2911430B1 FR 0700265 A FR0700265 A FR 0700265A FR 0700265 A FR0700265 A FR 0700265A FR 2911430 B1 FR2911430 B1 FR 2911430B1
- Authority
- FR
- France
- Prior art keywords
- manufacturing
- hybrid substrate
- hybrid
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0700265A FR2911430B1 (fr) | 2007-01-15 | 2007-01-15 | "procede de fabrication d'un substrat hybride" |
| US11/836,527 US7632739B2 (en) | 2007-01-15 | 2007-08-09 | Fabrication of hybrid substrate with defect trapping zone |
| PCT/IB2008/000050 WO2008087516A1 (fr) | 2007-01-15 | 2008-01-07 | Procédé de fabrication d'un substrat hybride |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0700265A FR2911430B1 (fr) | 2007-01-15 | 2007-01-15 | "procede de fabrication d'un substrat hybride" |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2911430A1 FR2911430A1 (fr) | 2008-07-18 |
| FR2911430B1 true FR2911430B1 (fr) | 2009-04-17 |
Family
ID=38512570
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR0700265A Expired - Fee Related FR2911430B1 (fr) | 2007-01-15 | 2007-01-15 | "procede de fabrication d'un substrat hybride" |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7632739B2 (fr) |
| FR (1) | FR2911430B1 (fr) |
| WO (1) | WO2008087516A1 (fr) |
Families Citing this family (38)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008123116A1 (fr) * | 2007-03-26 | 2008-10-16 | Semiconductor Energy Laboratory Co., Ltd. | Substrat soi et procédé de réalisation d'un substrat soi |
| WO2008123117A1 (fr) * | 2007-03-26 | 2008-10-16 | Semiconductor Energy Laboratory Co., Ltd. | Substrat soi et procédé de réalisation d'un substrat soi |
| CN101281912B (zh) * | 2007-04-03 | 2013-01-23 | 株式会社半导体能源研究所 | Soi衬底及其制造方法以及半导体装置 |
| CN101657882B (zh) | 2007-04-13 | 2012-05-30 | 株式会社半导体能源研究所 | 显示器件、用于制造显示器件的方法、以及soi衬底 |
| US8513678B2 (en) | 2007-05-18 | 2013-08-20 | Semiconductor Energy Laboratory Co., Ltd. | Light-emitting device |
| FR2919427B1 (fr) * | 2007-07-26 | 2010-12-03 | Soitec Silicon On Insulator | Structure a reservoir de charges. |
| US8101501B2 (en) * | 2007-10-10 | 2012-01-24 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing semiconductor device |
| CN101842910B (zh) * | 2007-11-01 | 2013-03-27 | 株式会社半导体能源研究所 | 用于制造光电转换器件的方法 |
| JP5503876B2 (ja) * | 2008-01-24 | 2014-05-28 | 株式会社半導体エネルギー研究所 | 半導体基板の製造方法 |
| FR2926925B1 (fr) * | 2008-01-29 | 2010-06-25 | Soitec Silicon On Insulator | Procede de fabrication d'heterostructures |
| FR2933534B1 (fr) * | 2008-07-03 | 2011-04-01 | Soitec Silicon On Insulator | Procede de fabrication d'une structure comprenant une couche de germanium sur un substrat |
| US8741740B2 (en) * | 2008-10-02 | 2014-06-03 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
| US8377798B2 (en) * | 2010-11-10 | 2013-02-19 | Taiwan Semiconductor Manufacturing Co., Ltd | Method and structure for wafer to wafer bonding in semiconductor packaging |
| JP2012156495A (ja) | 2011-01-07 | 2012-08-16 | Semiconductor Energy Lab Co Ltd | Ｓｏｉ基板の作製方法 |
| JP2014516470A (ja) | 2011-04-08 | 2014-07-10 | エーファウ・グループ・エー・タルナー・ゲーエムベーハー | ウェハを恒久的にボンディングするための方法 |
| CN102810464B (zh) * | 2011-06-02 | 2015-07-01 | 无锡华润上华半导体有限公司 | 一种光刻方法 |
| US8802534B2 (en) | 2011-06-14 | 2014-08-12 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming SOI substrate and apparatus for forming the same |
| FR2980636B1 (fr) | 2011-09-22 | 2016-01-08 | St Microelectronics Rousset | Protection d'un dispositif electronique contre une attaque laser en face arriere, et support semiconducteur correspondant |
| KR101357795B1 (ko) | 2011-10-10 | 2014-02-11 | 삼성코닝정밀소재 주식회사 | 수직형 반도체 소자용 기판 및 이의 제조방법 |
| FR3007891B1 (fr) * | 2013-06-28 | 2016-11-25 | Soitec Silicon On Insulator | Procede de fabrication d'une structure composite |
| KR102148336B1 (ko) | 2013-11-26 | 2020-08-27 | 삼성전자주식회사 | 표면 처리 방법, 반도체 제조 방법 및 이에 의해 제조된 반도체 장치 |
| KR102212296B1 (ko) | 2014-01-23 | 2021-02-04 | 글로벌웨이퍼스 씨오., 엘티디. | 고 비저항 soi 웨이퍼 및 그 제조 방법 |
| US10224233B2 (en) | 2014-11-18 | 2019-03-05 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed by He-N2 co-implantation |
| EP3573094B1 (fr) | 2014-11-18 | 2023-01-04 | GlobalWafers Co., Ltd. | Tranche de semiconducteur sur isolant à résistivité élevée et son procédé de fabrication |
| WO2016140850A1 (fr) | 2015-03-03 | 2016-09-09 | Sunedison Semiconductor Limited | Procédé pour déposer des films de silicium polycristallin de piégeage de charge sur des substrats de silicium avec une contrainte de film pouvant être maîtrisée |
| CN104900615A (zh) * | 2015-05-08 | 2015-09-09 | 武汉新芯集成电路制造有限公司 | 一种提高键合力的方法及一种半导体键合结构 |
| EP3304586B1 (fr) | 2015-06-01 | 2020-10-07 | GlobalWafers Co., Ltd. | Procédé de fabrication de silicium-germanium sur isolant |
| US10529616B2 (en) | 2015-11-20 | 2020-01-07 | Globalwafers Co., Ltd. | Manufacturing method of smoothing a semiconductor surface |
| US10468294B2 (en) | 2016-02-19 | 2019-11-05 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface |
| WO2017142849A1 (fr) * | 2016-02-19 | 2017-08-24 | Sunedison Semiconductor Limited | Structure de semi-conducteur sur isolant comprenant une couche enfouie à haute résistivité |
| US10573550B2 (en) | 2016-03-07 | 2020-02-25 | Globalwafers Co., Ltd. | Semiconductor on insulator structure comprising a plasma oxide layer and method of manufacture thereof |
| WO2017155808A1 (fr) | 2016-03-07 | 2017-09-14 | Sunedison Semiconductor Limited | Structure de semi-conducteur sur isolant contenant une couche de nitrure de plasma et son procédé de fabrication |
| WO2017155804A1 (fr) | 2016-03-07 | 2017-09-14 | Sunedison Semiconductor Limited | Procédé de fabrication d'une structure de semi-conducteur sur isolant au moyen d'un traitement de liaison sous pression |
| EP3469120B1 (fr) | 2016-06-08 | 2022-02-02 | GlobalWafers Co., Ltd. | Lingot et plaquette de silicium monocristallin à résistivité élevée présentant une résistance mécanique améliorée |
| US10269617B2 (en) | 2016-06-22 | 2019-04-23 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising an isolation region |
| JP7123182B2 (ja) | 2018-06-08 | 2022-08-22 | グローバルウェーハズ カンパニー リミテッド | シリコン箔層の移転方法 |
| JP6679666B2 (ja) * | 2018-07-05 | 2020-04-15 | エーファウ・グループ・エー・タルナー・ゲーエムベーハー | ウエハの永久接合方法 |
| FR3134650B1 (fr) * | 2022-04-19 | 2024-03-01 | Soitec Silicon On Insulator | Procede d’assemblage de deux substrats par adhesion moleculaire, et structure obtenue par un tel procede |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2823599B1 (fr) * | 2001-04-13 | 2004-12-17 | Commissariat Energie Atomique | Substrat demomtable a tenue mecanique controlee et procede de realisation |
| CA2482258A1 (fr) * | 2001-04-17 | 2002-10-24 | California Institute Of Technology | Procede utilisant un transfert de la couche au germanium au si pour applications photovoltaiques, et heterostructures realisees par ce procede |
| US20030124265A1 (en) * | 2001-12-04 | 2003-07-03 | 3M Innovative Properties Company | Method and materials for transferring a material onto a plasma treated surface according to a pattern |
| FR2866983B1 (fr) * | 2004-03-01 | 2006-05-26 | Soitec Silicon On Insulator | Realisation d'une entite en materiau semiconducteur sur substrat |
| EP1571705A3 (fr) * | 2004-03-01 | 2006-01-04 | S.O.I.Tec Silicon on Insulator Technologies | Réalisation d'une entité en matériau semiconducteur sur substrat |
| US8138061B2 (en) * | 2005-01-07 | 2012-03-20 | International Business Machines Corporation | Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide |
| FR2881573B1 (fr) * | 2005-01-31 | 2008-07-11 | Soitec Silicon On Insulator | Procede de transfert d'une couche mince formee dans un substrat presentant des amas de lacunes |
| US7166520B1 (en) * | 2005-08-08 | 2007-01-23 | Silicon Genesis Corporation | Thin handle substrate method and structure for fabricating devices using one or more films provided by a layer transfer process |
| FR2896619B1 (fr) * | 2006-01-23 | 2008-05-23 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat composite a proprietes electriques ameliorees |
-
2007
- 2007-01-15 FR FR0700265A patent/FR2911430B1/fr not_active Expired - Fee Related
- 2007-08-09 US US11/836,527 patent/US7632739B2/en active Active
-
2008
- 2008-01-07 WO PCT/IB2008/000050 patent/WO2008087516A1/fr not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| US20080171443A1 (en) | 2008-07-17 |
| US7632739B2 (en) | 2009-12-15 |
| WO2008087516A1 (fr) | 2008-07-24 |
| FR2911430A1 (fr) | 2008-07-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| CD | Change of name or company name |
Owner name: SOITEC, FR Effective date: 20120423 |
|
| PLFP | Fee payment |
Year of fee payment: 10 |
|
| PLFP | Fee payment |
Year of fee payment: 11 |
|
| PLFP | Fee payment |
Year of fee payment: 12 |
|
| ST | Notification of lapse |
Effective date: 20190906 |