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FR2830972B1 - Architecture de circuits protegee contre des perturbations - Google Patents

Architecture de circuits protegee contre des perturbations

Info

Publication number
FR2830972B1
FR2830972B1 FR0113241A FR0113241A FR2830972B1 FR 2830972 B1 FR2830972 B1 FR 2830972B1 FR 0113241 A FR0113241 A FR 0113241A FR 0113241 A FR0113241 A FR 0113241A FR 2830972 B1 FR2830972 B1 FR 2830972B1
Authority
FR
France
Prior art keywords
protected against
circuit architecture
against disturbances
architecture protected
disturbances
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0113241A
Other languages
English (en)
Other versions
FR2830972A1 (fr
Inventor
Michael Nicolaidis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Iroc Technologies SA
Original Assignee
Iroc Technologies SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Iroc Technologies SA filed Critical Iroc Technologies SA
Priority to FR0113241A priority Critical patent/FR2830972B1/fr
Priority to US10/492,294 priority patent/US20040255204A1/en
Priority to EP02785543A priority patent/EP1451688A2/fr
Priority to PCT/FR2002/003484 priority patent/WO2003032160A2/fr
Publication of FR2830972A1 publication Critical patent/FR2830972A1/fr
Application granted granted Critical
Publication of FR2830972B1 publication Critical patent/FR2830972B1/fr
Priority to US11/904,762 priority patent/US20080028278A1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
    • G06F11/141—Saving, restoring, recovering or retrying at machine instruction level for bus or memory accesses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1016—Error in accessing a memory location, i.e. addressing error

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)
  • Logic Circuits (AREA)
FR0113241A 2001-10-12 2001-10-12 Architecture de circuits protegee contre des perturbations Expired - Fee Related FR2830972B1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FR0113241A FR2830972B1 (fr) 2001-10-12 2001-10-12 Architecture de circuits protegee contre des perturbations
US10/492,294 US20040255204A1 (en) 2001-10-12 2002-10-11 Circuit architecture protected against perturbations
EP02785543A EP1451688A2 (fr) 2001-10-12 2002-10-11 Architecture de circuits protegee contre des perturbations
PCT/FR2002/003484 WO2003032160A2 (fr) 2001-10-12 2002-10-11 Architecture de circuits protegee contre des perturbations
US11/904,762 US20080028278A1 (en) 2001-10-12 2007-09-27 Circuit architecture protected against perturbations

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0113241A FR2830972B1 (fr) 2001-10-12 2001-10-12 Architecture de circuits protegee contre des perturbations

Publications (2)

Publication Number Publication Date
FR2830972A1 FR2830972A1 (fr) 2003-04-18
FR2830972B1 true FR2830972B1 (fr) 2004-09-10

Family

ID=8868280

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0113241A Expired - Fee Related FR2830972B1 (fr) 2001-10-12 2001-10-12 Architecture de circuits protegee contre des perturbations

Country Status (4)

Country Link
US (2) US20040255204A1 (fr)
EP (1) EP1451688A2 (fr)
FR (1) FR2830972B1 (fr)
WO (1) WO2003032160A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2790887B1 (fr) * 1999-03-09 2003-01-03 Univ Joseph Fourier Circuit logique protege contre des perturbations transitoires
DE102006027448B4 (de) * 2006-06-12 2008-05-15 Universität Potsdam Schaltungsanordnung

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4942516A (en) * 1970-12-28 1990-07-17 Hyatt Gilbert P Single chip integrated circuit computer architecture
US4199810A (en) * 1977-01-07 1980-04-22 Rockwell International Corporation Radiation hardened register file
US4612632A (en) * 1984-12-10 1986-09-16 Zenith Electronics Corporation Power transition write protection for PROM
US5173905A (en) * 1990-03-29 1992-12-22 Micron Technology, Inc. Parity and error correction coding on integrated circuit addresses
US5233617A (en) * 1990-04-13 1993-08-03 Vlsi Technology, Inc. Asynchronous latch circuit and register
JPH05298134A (ja) * 1991-12-16 1993-11-12 Internatl Business Mach Corp <Ibm> コンピュータシステムにおける処理誤りの処理機構及び方法
US5336939A (en) * 1992-05-08 1994-08-09 Cyrix Corporation Stable internal clock generation for an integrated circuit
JPH06237151A (ja) * 1993-02-10 1994-08-23 Fujitsu Ltd 半導体集積回路装置
US5699365A (en) * 1996-03-27 1997-12-16 Motorola, Inc. Apparatus and method for adaptive forward error correction in data communications
US5931959A (en) * 1997-05-21 1999-08-03 The United States Of America As Represented By The Secretary Of The Air Force Dynamically reconfigurable FPGA apparatus and method for multiprocessing and fault tolerance
US6519715B1 (en) * 1998-05-22 2003-02-11 Hitachi, Ltd. Signal processing apparatus and a data recording and reproducing apparatus including local memory processor
FR2790887B1 (fr) * 1999-03-09 2003-01-03 Univ Joseph Fourier Circuit logique protege contre des perturbations transitoires
US6636991B1 (en) * 1999-12-23 2003-10-21 Intel Corporation Flexible method for satisfying complex system error handling requirements via error promotion/demotion

Also Published As

Publication number Publication date
WO2003032160A2 (fr) 2003-04-17
FR2830972A1 (fr) 2003-04-18
EP1451688A2 (fr) 2004-09-01
US20040255204A1 (en) 2004-12-16
WO2003032160A3 (fr) 2004-06-17
US20080028278A1 (en) 2008-01-31

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20100630