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FR2819143B1 - Procede de realisation de plots de connexion sur un circuit imprime - Google Patents

Procede de realisation de plots de connexion sur un circuit imprime

Info

Publication number
FR2819143B1
FR2819143B1 FR0017230A FR0017230A FR2819143B1 FR 2819143 B1 FR2819143 B1 FR 2819143B1 FR 0017230 A FR0017230 A FR 0017230A FR 0017230 A FR0017230 A FR 0017230A FR 2819143 B1 FR2819143 B1 FR 2819143B1
Authority
FR
France
Prior art keywords
printed circuit
making connection
plots
connection plots
making
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0017230A
Other languages
English (en)
Other versions
FR2819143A1 (fr
Inventor
Myriam Oudart
Francois Bernard
Marie Jose Molino
Bruno Reig
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Priority to FR0017230A priority Critical patent/FR2819143B1/fr
Priority to KR1020027011250A priority patent/KR20020089367A/ko
Priority to EP01989644A priority patent/EP1262094A1/fr
Priority to JP2002555597A priority patent/JP2004517500A/ja
Priority to PCT/FR2001/004117 priority patent/WO2002054842A1/fr
Priority to US10/204,561 priority patent/US20030013045A1/en
Publication of FR2819143A1 publication Critical patent/FR2819143A1/fr
Application granted granted Critical
Publication of FR2819143B1 publication Critical patent/FR2819143B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3473—Plating of solder
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H05K2203/0542—Continuous temporary metal layer over metal pattern

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Manufacturing Of Printed Wiring (AREA)
FR0017230A 2000-12-28 2000-12-28 Procede de realisation de plots de connexion sur un circuit imprime Expired - Fee Related FR2819143B1 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
FR0017230A FR2819143B1 (fr) 2000-12-28 2000-12-28 Procede de realisation de plots de connexion sur un circuit imprime
KR1020027011250A KR20020089367A (ko) 2000-12-28 2001-12-20 인쇄회로상에 본드 패드를 형성하는 방법
EP01989644A EP1262094A1 (fr) 2000-12-28 2001-12-20 Procede de realisation de plots de connexion sur un circuit imprime
JP2002555597A JP2004517500A (ja) 2000-12-28 2001-12-20 印刷回路の上に接続バンプを生成する方法
PCT/FR2001/004117 WO2002054842A1 (fr) 2000-12-28 2001-12-20 Procede de realisation de plots de connexion sur un circuit imprime
US10/204,561 US20030013045A1 (en) 2000-12-28 2001-12-20 Method for producing bond pads on a printed circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0017230A FR2819143B1 (fr) 2000-12-28 2000-12-28 Procede de realisation de plots de connexion sur un circuit imprime

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FR2819143A1 FR2819143A1 (fr) 2002-07-05
FR2819143B1 true FR2819143B1 (fr) 2003-03-07

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US (1) US20030013045A1 (fr)
EP (1) EP1262094A1 (fr)
JP (1) JP2004517500A (fr)
KR (1) KR20020089367A (fr)
FR (1) FR2819143B1 (fr)
WO (1) WO2002054842A1 (fr)

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Publication number Priority date Publication date Assignee Title
US8901736B2 (en) * 2010-05-28 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Strength of micro-bump joints
CN107709505B (zh) * 2015-05-27 2020-04-28 Ａｇｃ株式会社 拒水拒油剂组合物、其制造方法及物品

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Publication number Priority date Publication date Assignee Title
US5024734A (en) * 1989-12-27 1991-06-18 Westinghouse Electric Corp. Solder pad/circuit trace interface and a method for generating the same
FR2666173A1 (fr) * 1990-08-21 1992-02-28 Thomson Csf Structure hybride d'interconnexion de circuits integres et procede de fabrication.
US5376584A (en) * 1992-12-31 1994-12-27 International Business Machines Corporation Process of making pad structure for solder ball limiting metallurgy having reduced edge stress
FR2701602B1 (fr) * 1993-02-12 1995-03-31 Thomson Csf Détecteur thermique comprenant un isolant thermique en polymère expansé.
US5480835A (en) * 1993-05-06 1996-01-02 Motorola, Inc. Electrical interconnect and method for forming the same
JPH0845941A (ja) * 1994-08-03 1996-02-16 Oki Electric Ind Co Ltd 半導体装置バンプの形成方法
US5800726A (en) * 1995-07-26 1998-09-01 International Business Machines Corporation Selective chemical etching in microelectronics fabrication
FR2740933B1 (fr) * 1995-11-03 1997-11-28 Thomson Csf Sonde acoustique et procede de realisation
FR2745973B1 (fr) * 1996-03-08 1998-04-03 Thomson Csf Memoire de masse et procede de fabrication de memoire de masse
JP3352352B2 (ja) * 1997-03-31 2002-12-03 新光電気工業株式会社 めっき装置、めっき方法およびバンプの形成方法
US6293457B1 (en) * 2000-06-08 2001-09-25 International Business Machines Corporation Integrated method for etching of BLM titanium-tungsten alloys for CMOS devices with copper metallization
US6586322B1 (en) * 2001-12-21 2003-07-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a bump on a substrate using multiple photoresist layers
US6696356B2 (en) * 2001-12-31 2004-02-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a bump on a substrate without ribbon residue

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Publication number Publication date
EP1262094A1 (fr) 2002-12-04
FR2819143A1 (fr) 2002-07-05
US20030013045A1 (en) 2003-01-16
JP2004517500A (ja) 2004-06-10
WO2002054842A1 (fr) 2002-07-11
KR20020089367A (ko) 2002-11-29

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