FR2881575B1 - MOS TRANSISTOR WITH TOTALLY SILICATED GRID - Google Patents
MOS TRANSISTOR WITH TOTALLY SILICATED GRIDInfo
- Publication number
- FR2881575B1 FR2881575B1 FR0500896A FR0500896A FR2881575B1 FR 2881575 B1 FR2881575 B1 FR 2881575B1 FR 0500896 A FR0500896 A FR 0500896A FR 0500896 A FR0500896 A FR 0500896A FR 2881575 B1 FR2881575 B1 FR 2881575B1
- Authority
- FR
- France
- Prior art keywords
- silicated
- totally
- grid
- mos transistor
- mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
- H10D30/0213—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation providing different silicide thicknesses on gate electrodes and on source regions or drain regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32105—Oxidation of silicon-containing layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
- H10D64/668—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the layer being a silicide, e.g. TiSi2
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0500896A FR2881575B1 (en) | 2005-01-28 | 2005-01-28 | MOS TRANSISTOR WITH TOTALLY SILICATED GRID |
| US11/329,358 US7638427B2 (en) | 2005-01-28 | 2006-01-10 | MOS transistor with fully silicided gate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0500896A FR2881575B1 (en) | 2005-01-28 | 2005-01-28 | MOS TRANSISTOR WITH TOTALLY SILICATED GRID |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2881575A1 FR2881575A1 (en) | 2006-08-04 |
| FR2881575B1 true FR2881575B1 (en) | 2007-06-01 |
Family
ID=35219448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR0500896A Expired - Fee Related FR2881575B1 (en) | 2005-01-28 | 2005-01-28 | MOS TRANSISTOR WITH TOTALLY SILICATED GRID |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7638427B2 (en) |
| FR (1) | FR2881575B1 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7268065B2 (en) * | 2004-06-18 | 2007-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of manufacturing metal-silicide features |
| US7544553B2 (en) * | 2005-03-30 | 2009-06-09 | Infineon Technologies Ag | Integration scheme for fully silicided gate |
| US7220643B1 (en) * | 2005-06-08 | 2007-05-22 | Spansion Llc | System and method for gate formation in a semiconductor device |
| KR100729366B1 (en) * | 2006-05-19 | 2007-06-15 | 삼성전자주식회사 | Semiconductor Device and Forming Method |
| US20070296052A1 (en) * | 2006-06-26 | 2007-12-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming silicide regions and resulting MOS devices |
| JP4822982B2 (en) * | 2006-08-21 | 2011-11-24 | 株式会社東芝 | Manufacturing method of semiconductor device |
| US7741171B2 (en) * | 2007-05-15 | 2010-06-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Oxygen-rich layers underlying BPSG |
| US8273645B2 (en) * | 2008-08-07 | 2012-09-25 | Texas Instruments Incorporated | Method to attain low defectivity fully silicided gates |
| US8404589B2 (en) * | 2010-04-06 | 2013-03-26 | International Business Machines Corporation | Silicide contact formation |
| US9218976B2 (en) * | 2013-08-13 | 2015-12-22 | Globalfoundries Inc. | Fully silicided gate formed according to the gate-first HKMG approach |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5352631A (en) * | 1992-12-16 | 1994-10-04 | Motorola, Inc. | Method for forming a transistor having silicided regions |
| US6187675B1 (en) * | 1999-06-03 | 2001-02-13 | Advanced Micro Devices, Inc. | Method for fabrication of a low resistivity MOSFET gate with thick metal silicide on polysilicon |
| US6268255B1 (en) * | 2000-01-06 | 2001-07-31 | Advanced Micro Devices, Inc. | Method of forming a semiconductor device with metal silicide regions |
| US6620718B1 (en) * | 2000-04-25 | 2003-09-16 | Advanced Micro Devices, Inc. | Method of forming metal silicide regions on a gate electrode and on the source/drain regions of a semiconductor device |
| US6306698B1 (en) * | 2000-04-25 | 2001-10-23 | Advanced Micro Devices, Inc. | Semiconductor device having metal silicide regions of differing thicknesses above the gate electrode and the source/drain regions, and method of making same |
| US6458678B1 (en) * | 2000-07-25 | 2002-10-01 | Advanced Micro Devices, Inc. | Transistor formed using a dual metal process for gate and source/drain region |
| US6562717B1 (en) * | 2000-10-05 | 2003-05-13 | Advanced Micro Devices, Inc. | Semiconductor device having multiple thickness nickel silicide layers |
| DE10056866C2 (en) * | 2000-11-16 | 2002-10-24 | Advanced Micro Devices Inc | Process for forming an etch stop layer during the manufacture of a semiconductor device |
| US6562718B1 (en) * | 2000-12-06 | 2003-05-13 | Advanced Micro Devices, Inc. | Process for forming fully silicided gates |
| US6657244B1 (en) * | 2002-06-28 | 2003-12-02 | International Business Machines Corporation | Structure and method to reduce silicon substrate consumption and improve gate sheet resistance during silicide formation |
| FR2853134B1 (en) | 2003-03-25 | 2005-07-01 | St Microelectronics Sa | PROCESS FOR MANUFACTURING A METALLIC GRID TRANSISTOR, AND CORRESPONDING TRANSISTOR |
| US7122472B2 (en) * | 2004-12-02 | 2006-10-17 | International Business Machines Corporation | Method for forming self-aligned dual fully silicided gates in CMOS devices |
-
2005
- 2005-01-28 FR FR0500896A patent/FR2881575B1/en not_active Expired - Fee Related
-
2006
- 2006-01-10 US US11/329,358 patent/US7638427B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| FR2881575A1 (en) | 2006-08-04 |
| US7638427B2 (en) | 2009-12-29 |
| US20060172492A1 (en) | 2006-08-03 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| ST | Notification of lapse |
Effective date: 20140930 |