FR2876472A1 - Protocol method for patented hardware used on chip, involves requesting software function corresponding to entry of request signal in hardware, waiting for return value coinciding with transmission of results and resetting hardware - Google Patents

Abstract

Method involves determining whether IP hardware, or patented circuit block, requires parameters, and, if needed, entering parameters; requesting software function corresponding to entry of request signal in IP hardware; waiting for return value of software function corresponding to entry of acknowledgement signal in IP hardware. Return value is sent back to coincide with transmission of results from IP hardware, and IP hardware is reset.

Description

The invention relates to a protocol method for a system device

  on chip, and more particularly a protocol method for reusable IP hardware component for a system-on-a-chip device.

  s Systems-on-a-chip implementations in which a plurality of functionally related circuit blocks are integrated into a single chip have become an important trend in current circuit implementations. As an example of a system-on-a-chip microprocessor in the field of computing, the internal circuits of the on-chip system integrate the circuit blocks of a central unit, a chipset and a chip. graphics chip, so that the system-on-chip microprocessor contains the functionality of the three circuit blocks. The realization of systems-on-a-chip not only reduces the cost of manufacturing, but also the total area of the circuits to reduce the size of all circuits. Each circuit block is composed of several different modules that may include counters, adders, encoders, decoders, etc., which are referred to as IP devices. Those skilled in the art are more familiar with the English terminology "IP hardware"; IP means Intellectual Property, that is, Industrial Property in French. IP devices are pre-built components or blocks that perform a function. They are often protected by patents, hence the terminology used. The realization of systems-on-a-chip uses IP hardware to build the required circuit blocks and then integrates these together into a single chip.

  However, the realization of systems on chip poses some problems. The most important is the control of the clock frequency between the different IP hardware components. A clock frequency signal is used to control the operating frequency, or operation, of each IP hardware component in the system-on-a-chip. When the clock rate signal is sent to each system-on-a-chip circuit block, all the IP hardware components of the circuit block operate at the same frequency. Since each IP hardware component has its own operating frequency, to allow multiple IP hardware components to operate with a single clock rate, the clock rate signal must satisfy the lowest clock rate to avoid a clock frequency. incorrect timing. This reduces the overall efficiency of the system.

  It is therefore desirable to have a protocol method for reusable IP hardware components for a system-on-a-chip to mitigate and / or avoid the aforementioned problems.

  The main object of the present invention is to provide a protocol method for reusable IP hardware component for an on-chip system, which can describe hardware behavior by software functions.

  Another object of the present invention is to provide a protocol method for reusable IP hardware component for a system-on-a-chip, which can be reused many times.

  Still another object of the present invention is to provide a protocol method for a reusable IP hardware component for a system-on-a-chip that can be used in asynchronous-type circuits.

  To achieve the objectives mentioned above, the present invention relates to a protocol method for reusable IP hardware component for a system-on-a-chip device, arranged to describe the behavior of a hardware through a software function, which method comprising: (A) a step of determining whether parameters are needed, corresponding to a step of determining whether the IP hardware requests parameters, and if parameters are required, moving to step (B), otherwise, switching to step (C), 30 (B) the input of at least one function parameter, corresponding to the input of at least one function parameter in the IP hardware, (C) call of the software function corresponding to the input of a request signal in the IP hardware, (D) waiting for a return value of the software function corresponding to the input of an acknowledgment signal reception in the material IP, (E) returning the return value of the software function corresponding to the sending of the result data of the IP hardware, and (F) terminating the software function corresponding to the resetting or booting of the hardware. IP.

  Finally, the software function is used to create a hardware description language, and this language is used to create IP hardware components. The system-on-a-chip is designed for at least one hardware module, and this module operates asynchronously. The software function of the present invention can be used to describe hardware behavior and for both synchronous and asynchronous circuit designs to achieve the objects of the present invention.

  Advantageously, the method further comprises, prior to step (A), a hardware initialization step for initializing the IP hardware.

  Advantageously, step (B) further comprises an input of at least one detection data which corresponds to the parameter or function parameters.

  Preferably in this case, the one or more detection data is a complement number of the parameter or function parameters.

  More preferably, the data or detection data is used to detect whether the parameter or function parameters are incorrect or to detect whether the parameter or the function parameters are completely entered.

  Advantageously, the step (E) further comprises an output of the IP hardware of at least one resultant detection datum, the resulting datum or the resulting detection data corresponding to the resulting data.

  Preferably in this case, the resultant data or the resultant detection data is a complement number of the resulting data or resultant data.

  More preferably, the resultant data or detection data is used to detect whether the resulting data or resultant data is incorrect or to detect whether the resulting data or resultant data is completely entered.

  Advantageously, the software function can be transformed into a hardware description language.

  Advantageously, the system-on-a-chip device comprises at least one IP hardware and the interaction of the IP hardware or each IP hardware is asynchronous.

  Fig. 1 shows a software flowchart of a protocol method for reusable IP hardware component for a system-on-chip according to the present invention; FIG. 2 represents a behavior chart for IP hardware component corresponding to FIG. 1 and FIG. 3 represents a schematic sketch, in the form of a timing diagram, of the behavior of the IP hardware component.

  The method of the present invention uses a software function to describe the behavior of the IP hardware component and calls the software module to match the execution of the hardware IP component. With reference to FIG. 1, a procedure of the method of the present invention comprises: a step of determining whether the software function needs parameters; if it needs it, step 12 is executed; otherwise, step 14 is executed. The software function can be the following accumulation function (1), but is not limited to this function: public static int sumTo (int CNT) int SUM O; for (int i = 1; i ≤ CNT; i ++) <SUM + = i; return SUM; Before calling the function (1), a function parameter must be set and entered, for example by setting the CNT function parameter to 5. 1n

  As is known, when an IP hardware component resets or boots, step 30 is always executed to initialize the hardware for eventual subsequent execution. Further, the hardware operation of step 30 is shown in FIG. 3 as the rising edge 50 of a CLR (clear) signal, which means that the CLR signal is set high to eliminate the data. if any temporarily stored in the hardware components W. Step 10 for the software function corresponds to step 32 for the IP hardware component, step 32 being executed to determine whether the IP hardware component needs parameters, and it needs it, step 34 is executed to enter parameter data, to correspond to step 12. If step 32 determines that no hardware component IP is required, step 36 is performed to validate a request signal, to correspond to step 14. The hardware operation of step 34 is shown in FIG. 3 as rising edge 52 of the parameter data, which means that a circuit outside (the circuit connected to the com posing IP hardware) between parameter data (such as CNT = 5 mentioned above) in the IP hardware component. The external circuit 3o can also receive the acknowledgment signal of the input data of the IP hardware component.

  Step 14 is executed to call the software function. For function (1), after step 12, the software must be executed. Step 14 executes the following code: intSUM = O; for (int i = 1; i ≤ CNT; i ++) SUM + = i; In addition, step 14 corresponds to step 36 of FIG. 2, which is executed to validate a request signal (REQ). The high REQ signal is inputted from the external circuit into the IP hardware component, and the IP hardware component executes an internal circuit operation (corresponding to step 14) according to functional settings and the input and output parameter. an appropriate response (the output result of step 14). Step 36 is shown in Figure 3 as a rising edge 54, which means that the external circuit puts the REQ signal high, and then the internal circuit of the IP hardware component begins to operate.

  Step 16 is executed to wait for a return value of the software function. For function (1), when the parameter is supplied (in step 12) and executed (in step 16), function (1) will return a result value (or a return value).

  In addition, step 16 corresponds to step 38 of FIG. 2, which is executed to wait for an acknowledgment signal (ACK). After the z hardware component 1P has performed its operation, or operation, appropriately, it produces the resultant value and sends it to the external circuit. The signal ACK is sent from the hardware component 1P to the external circuit indicating that the resulting value is being produced. The IP hardware component is then ready to send the resultant value to the third external circuit. Step 38 is shown in FIG. 3 in the form of the rising edge 56 of the ACK signal; when the IP equipment passes the ACK signal from a low level to a high level, the hardware component 1P performs the requested operation and sends the result value to the external circuit.

  Step 18 is executed to return the return value of the software function. After function (1) has completed its operation, the return value is returned. Since the CNT (count) parameter is 5, the function (1) takes place and the result is a SUM parameter of 15, and the function returns the SUM parameter. Step 18 corresponds to step 40 of Figure 2, which is executed to output the resulting data. When both the REQ signal and the ACK signal are set high, the IP hardware component sends the resultant value of the operation to the external circuit, i.e., transmits the resultant data 15. Step 40 is shown in Fig. 3 as the rising edge 58 of the result data, which indicates the output of the result data 15.]. o

  Step 20 is executed to terminate the software function. After returning the return value, function (1) has completed its task and can be called again. Step 20 corresponds to step 42 shown in Figure 2, which is executed to reset the hardware. After receiving the resulting data, the external circuit puts the REQ signal low, so that the IP component can erase the stored temporary data and is ready for the next call. Step 42 is shown in FIG. 3 as the falling edge 60 of the REQ signal. When the REQ signal is low, the IP hardware component stops transmitting the resulting data and eliminates all the resulting data it contains, as indicated by a falling edge 62 of a data signal shown in FIG. When the ACK signal is low, which indicates that the resulting data has been completely eliminated, as indicated by the falling edge 64 of the ACK signal shown in Fig. 3, the hardware component 1P is ready for subsequent operation.

  In addition, upon parameter input and output of the resulting data, a dual control data representation is used to ensure that the I / O procedures have been completed, as well as the execution of the data. error detection means. As in step 34, during the input of the parameter data, completion detection or error detection parameter data (CDED) are also introduced at the same time for example by a complement technique (also used in step 40) which determines whether the sum of the parameter data and the CDED parameter data is equal to 1. However, many other error detection methods can also be used. When the parameter data is entered as CNT = 5, the CDED parameter is entered as CNT '= -6, and its hardware execution is shown in FIG. 3 as the rising edge 53 of the CDED parameter data. ; when the result data is output as SUM = 15, the data of the detection / detection parameter is output as SUM '= -16, and their hardware execution is shown in FIG. rising edge 59 of the CDED parameter data. Therefore, the correct realization of the data transmission is assured.

  The software function of the present embodiment may be used to indicate the performance or operation of the IP hardware component; and the software function can be called repeatedly, which means that the IP hardware component can repeat the operation. Thus, the software function can be transformed into a practical hardware structure. For example, the software function can be transformed into a well-known hardware language for high-speed integrated circuits (VHDL), and the VHDL is then transformed into a practical hardware structure. In other words, the software function can describe the hardware's performance. In addition, when the system-on-a-chip is designed to have several software functions, as the IP hardware component corresponding to the software function is realized according to the steps mentioned above and unrelated to the clock frequency, the various components IP devices can have different clock rates. Therefore, the IP hardware component can work well in both synchronous and asynchronous system-on-chip implementations. 3o

Claims (1)

2876472 Claims   A protocol method for a reusable IP hardware component for a system-on-a-chip device, arranged to describe the behavior of a hardware through a software function, which method comprises: (A) a step of determining whether parameters are required, corresponding to a step of determining whether the IP hardware requests parameters, and if parameters are needed, moving to step (B), otherwise, proceeding to step (C), ( B) the input of at least one function parameter, corresponding to the input of at least one function parameter in the IP hardware, (C) the call of the software function corresponding to the input of a request signal in the IP hardware, (D) waiting for a return value of the software function corresponding to the input of an acknowledgment signal in the IP hardware, (E) the return of the return value of the software function corresponding to the emiss ion of the IP hardware result data; and (F) terminating the software function corresponding to resetting or booting the IP hardware.   The method of claim 1, further comprising, prior to step (A), a hardware initialization step for initializing the IP hardware.   The method of claim 1, wherein step (B) further comprises an input of at least one detection data that corresponds to the parameter or function parameters.   The method of claim 3, wherein the at least one detection data is a complement number of the parameter or function parameters.   The method of claim 4, wherein the data or the detection data is used to detect whether the parameter or function parameters are incorrect or to detect whether the parameter or the function parameters are completely entered.   The method of claim 1, wherein the step (E) further comprises an output of the IP hardware of at least one resultant detection data, the resultant data or the resultant detection data corresponding to the resultant data.   The method of claim 6, wherein the resultant data or the resultant detection data is a complement number of the resulting data or resultant data.   The method of claim 7, wherein the resultant data or the resultant detection data is used to detect whether the resulting data or resulting data is incorrect or to detect whether the resulting data or resulting data is completely entered.   The method of claim 1, wherein the software function can be transformed into a hardware description language.   The method of claim 1, wherein the on-chip system device comprises at least one IP hardware, and the interaction of the IP hardware or each IP hardware is asynchronous.