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FR2704690B1 - Procédé d'encapsulation de pastilles semi-conductrices, dispositif obtenu par ce procédé et application à l'interconnexion de pastilles en trois dimensions. - Google Patents

Procédé d'encapsulation de pastilles semi-conductrices, dispositif obtenu par ce procédé et application à l'interconnexion de pastilles en trois dimensions.

Info

Publication number
FR2704690B1
FR2704690B1 FR9304962A FR9304962A FR2704690B1 FR 2704690 B1 FR2704690 B1 FR 2704690B1 FR 9304962 A FR9304962 A FR 9304962A FR 9304962 A FR9304962 A FR 9304962A FR 2704690 B1 FR2704690 B1 FR 2704690B1
Authority
FR
France
Prior art keywords
chips
wafers
interconnection
dimensions
application
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9304962A
Other languages
English (en)
Other versions
FR2704690A1 (fr
Inventor
Val Christian
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Priority to FR9304962A priority Critical patent/FR2704690B1/fr
Priority to PCT/FR1994/000427 priority patent/WO1994025987A1/fr
Priority to EP94913654A priority patent/EP0647357A1/fr
Priority to JP6523941A priority patent/JPH07509104A/ja
Publication of FR2704690A1 publication Critical patent/FR2704690A1/fr
Application granted granted Critical
Publication of FR2704690B1 publication Critical patent/FR2704690B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
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    • H01L2224/0237—Disposition of the redistribution layers
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    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Dicing (AREA)
FR9304962A 1993-04-27 1993-04-27 Procédé d'encapsulation de pastilles semi-conductrices, dispositif obtenu par ce procédé et application à l'interconnexion de pastilles en trois dimensions. Expired - Fee Related FR2704690B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR9304962A FR2704690B1 (fr) 1993-04-27 1993-04-27 Procédé d'encapsulation de pastilles semi-conductrices, dispositif obtenu par ce procédé et application à l'interconnexion de pastilles en trois dimensions.
PCT/FR1994/000427 WO1994025987A1 (fr) 1993-04-27 1994-04-15 Procede d'encapsulation de pastilles semi-conductrices, dispositif obtenu par ce procede et application a l'interconnexion de pastilles en trois dimensions
EP94913654A EP0647357A1 (fr) 1993-04-27 1994-04-15 Procede d'encapsulation de pastilles semi-conductrices, dispositif obtenu par ce procede et application a l'interconnexion de pastilles en trois dimensions
JP6523941A JPH07509104A (ja) 1993-04-27 1994-04-15 半導体チップを封止する方法，この方法によって得られる装置，及び３次元のチップの相互接続への適用

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9304962A FR2704690B1 (fr) 1993-04-27 1993-04-27 Procédé d'encapsulation de pastilles semi-conductrices, dispositif obtenu par ce procédé et application à l'interconnexion de pastilles en trois dimensions.

Publications (2)

Publication Number Publication Date
FR2704690A1 FR2704690A1 (fr) 1994-11-04
FR2704690B1 true FR2704690B1 (fr) 1995-06-23

Family

ID=9446488

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9304962A Expired - Fee Related FR2704690B1 (fr) 1993-04-27 1993-04-27 Procédé d'encapsulation de pastilles semi-conductrices, dispositif obtenu par ce procédé et application à l'interconnexion de pastilles en trois dimensions.

Country Status (4)

Country Link
EP (1) EP0647357A1 (fr)
JP (1) JPH07509104A (fr)
FR (1) FR2704690B1 (fr)
WO (1) WO1994025987A1 (fr)

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US7829438B2 (en) 2006-10-10 2010-11-09 Tessera, Inc. Edge connect wafer level stacking
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US7943952B2 (en) 2006-07-31 2011-05-17 Cree, Inc. Method of uniform phosphor chip coating and LED package fabricated using method
US8043895B2 (en) 2007-08-09 2011-10-25 Tessera, Inc. Method of fabricating stacked assembly including plurality of stacked microelectronic elements
US8167674B2 (en) 2007-12-14 2012-05-01 Cree, Inc. Phosphor distribution in LED lamps using centrifugal force
US8232564B2 (en) 2007-01-22 2012-07-31 Cree, Inc. Wafer level phosphor coating technique for warm light emitting diodes
US8337071B2 (en) 2005-12-21 2012-12-25 Cree, Inc. Lighting device
US8513789B2 (en) 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
US8637883B2 (en) 2008-03-19 2014-01-28 Cree, Inc. Low index spacer layer in LED devices
US8680662B2 (en) 2008-06-16 2014-03-25 Tessera, Inc. Wafer level edge stacking
US8878219B2 (en) 2008-01-11 2014-11-04 Cree, Inc. Flip-chip phosphor coating method and devices fabricated utilizing method
US8969908B2 (en) 2006-04-04 2015-03-03 Cree, Inc. Uniform emission LED package
US9024349B2 (en) 2007-01-22 2015-05-05 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
US9041285B2 (en) 2007-12-14 2015-05-26 Cree, Inc. Phosphor distribution in LED lamps using centrifugal force
US9093616B2 (en) 2003-09-18 2015-07-28 Cree, Inc. Molded chip fabrication method and apparatus
US9159888B2 (en) 2007-01-22 2015-10-13 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
US9166126B2 (en) 2011-01-31 2015-10-20 Cree, Inc. Conformally coated light emitting devices and methods for providing the same

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JP2000124354A (ja) * 1998-10-21 2000-04-28 Matsushita Electric Ind Co Ltd チップサイズパッケージ及びその製造方法
JP3235586B2 (ja) * 1999-02-25 2001-12-04 日本電気株式会社 半導体装置及び半導体装置の製造方法
JP3065309B1 (ja) 1999-03-11 2000-07-17 沖電気工業株式会社 半導体装置の製造方法
US6812718B1 (en) 1999-05-27 2004-11-02 Nanonexus, Inc. Massively parallel interface for electronic circuits
US7247035B2 (en) 2000-06-20 2007-07-24 Nanonexus, Inc. Enhanced stress metal spring contactor
WO2001098793A2 (fr) * 2000-06-20 2001-12-27 Nanonexus, Inc. Systemes pour tester et mettre sous boitier des circuits integres
US7382142B2 (en) 2000-05-23 2008-06-03 Nanonexus, Inc. High density interconnect system having rapid fabrication cycle
AU6001599A (en) * 1999-10-01 2001-05-10 Hitachi Limited Semiconductor device and method of manufacture thereof
DE10023539B4 (de) * 2000-05-13 2009-04-09 Micronas Gmbh Verfahren zum Herstellen eines Bauteils
US7579848B2 (en) 2000-05-23 2009-08-25 Nanonexus, Inc. High density interconnect system for IC packages and interconnect assemblies
US20020100600A1 (en) * 2001-01-26 2002-08-01 Albert Douglas M. Stackable microcircuit layer formed from a plastic encapsulated microcircuit and method of making the same
DE10137184B4 (de) * 2001-07-31 2007-09-06 Infineon Technologies Ag Verfahren zur Herstellung eines elektronischen Bauteils mit einem Kuststoffgehäuse und elektronisches Bauteil
DE10149689A1 (de) 2001-10-09 2003-04-10 Philips Corp Intellectual Pty Elektrisches oder elektronische Bauteil und Verfahren zum Herstellen desselben
KR100886292B1 (ko) * 2003-09-09 2009-03-04 산요덴키가부시키가이샤 회로 소자를 포함하는 반도체 모듈과 반도체 장치, 그들의 제조 방법 및 표시 장치
EP1668745B1 (fr) * 2003-09-30 2011-08-31 International Business Machines Corporation Ensemble souple de puces empilees
US20050104027A1 (en) * 2003-10-17 2005-05-19 Lazarev Pavel I. Three-dimensional integrated circuit with integrated heat sinks
US7215018B2 (en) 2004-04-13 2007-05-08 Vertical Circuits, Inc. Stacked die BGA or LGA component assembly
US7217583B2 (en) 2004-09-21 2007-05-15 Cree, Inc. Methods of coating semiconductor light emitting elements by evaporating solvent from a suspension
US7759166B2 (en) 2006-10-17 2010-07-20 Tessera, Inc. Microelectronic packages fabricated at the wafer level and methods therefor
US10295147B2 (en) 2006-11-09 2019-05-21 Cree, Inc. LED array and method for fabricating same
US7952195B2 (en) 2006-12-28 2011-05-31 Tessera, Inc. Stacked packages with bridging traces
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JPH07509104A (ja) 1995-10-05
WO1994025987A1 (fr) 1994-11-10
FR2704690A1 (fr) 1994-11-04
EP0647357A1 (fr) 1995-04-12

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