FR2539978A1 - Apparatus for monitoring cardiac activity - Google Patents

Abstract

The invention relates to apparatuses used in cardiology. The monitoring apparatus which is the subject of the invention is characterised in particular in that the display unit 12 displays the various forms of perturbation of the cardiac rhythm: the extrasystoles in the case of grouped extrasystoles, the single extrasystoles, the ordinary blocks, the dangerous blocks, the extrasystoles in the case of bigeminy, and the normal rhythm, as a function of the various signal combinations appearing at the outputs of the logic circuit 6. The invention may be used in medical practice in particular for intense monitoring of the state of the cardiovascular system in particular during recovery, first aid, in ambulatory practice.

Description

 The present invention relates to cardiological diagnostic devices and in particular relates to a device intended for controlling cardiac activity, capable of measuring the time intervals between the R waves corresponding to the contractions of the heart, of analyzing the information thus obtained. , display the appearance of contractions and finally count the disturbances in their rhythm.

 The invention can be used in medical practice in particular for the intense control of the state of the cardiovascular system, in particular in resuscitation conditions, emergency rescue, in ambulatory practice, during physical effort tests or rehabilitation, as well as in case of monitoring of human behavior in extreme conditions (aviation, space and sports medicine).

 Annually, more than 250,000 people die from heart attacks without having the time to receive the necessary medical care. Obviously, if they could reach a hospital for adequate treatment, most of these people would still be alive today. The main reason for the fact that they could not be treated in time is the obvious inability of man to judge quickly enough whether or not to seek medical attention. The delay in making a decision is explained by the fact that the patient cannot properly control the frequency and rhythm of the contractions of his heart due to the absence of ad-hoc devices.

 It has been found that before the onset of a heart attack, there is generally a disturbance in the rhythm and frequency of the heartbeat, the latter being characterized by a significant number of dangerous arrhythmias or by an irregular gait.

If these arrhythmias could be detected in time, it would be possible to have a clear indication of the heart attack to come or which occurred shortly before. As a rule, these arrhythmias consist of premature ventricular contractions, such as: extrasystoles, blockages, bradycardias and tachycardias.

 Such arrhythmias can herald terminal states, namely ventricular fibrillation and asystole.

 It should be noted that the arrhythmias mentioned are directly related to the time intervals between the heartbeats. As for these, they can be easily determined by measuring the time between the successive R waves of the cardiosignal, after which the information obtained will be processed in order to have the data representative of one or more of the aforementioned symptoms.

 The application of a cardiac activity monitoring device would make it possible to intervene in time to help the patient, thereby reducing the number of possible threatening situations.

 For example, there is a device for controlling cardiac activity, described in US Patent No. 4,006,737, this device comprising com parers circuits whose inputs are supplied with electro-cardio signal. (ECS), and others, in constant reference signals, in particular temporal and amplitude. The outputs of these comparator circuits are connected, via AND circuits, to storage devices having their own outputs connected to display units.

 This device only detects and accumulates disturbances of the heart rate of two types, namely premature ventricular contractions and supraventricular tachycardia. It also makes it possible to record the exceeding of the predetermined upper and lower limits of the frequency of the heartbeat.

 Unfortunately, the apparatus described has only poor diagnostic possibilities since the comparison of the time and amplitude parameters of the ECS with fixed references implies the impossibility of taking into account the dynamics of the normal variations in the frequency of the heartbeat due to physical and emotional burdens, which results in the possibility of erroneous conclusions about disturbances of the heart rhythm.

 We also know a cardiac arrhythmia detector (see US Patent No. 3,861,387) comprising a set for obtaining the first derivative of GRECS with respect to time, a set for measuring the amplitude of the peaks of the derivative. , a set of averaging the amplitudes of the ECS derivative over a period of time, a set of measuring the time intervals between the droppings of the derivative signal, a set of averaging the time intervals between the peaks of the derivative of The DHW for a certain period of time, a comparator circuit which is triggered at the moment when the peak amplitude of the derivative deviates from the mean value of the amplitudes of +25 96, a comparator circuit operating when the tinter validates of time between the peaks of the derivative signal deviates from the average value of the intervals of + 25 '/ o, and a set of intermittent detection of cardiac contractions, consisting of a block for measuring the temporal intervals in be the R waves of the ECG and of a block which records an intermittence of contractions when the current interval is 1.5 times longer than the previous interval.

 This arrhythmia detector provides more secure detection of disturbances of the heart rhythm, such as abnormal ventricular contractions, disturbances of the rhythm accompanied by an increase in RR intervals, disturbances in the frequency of heartbeats.

 However, this device does not allow the disturbances detected to be stored separately, nor to classify them into groups, and only indicate the very fact of the presence of such disturbances.

 There is also a device for monitoring cardiac activity, the subject of US Patent No. 3,633,569, which includes an 11ECS amplification set, an arrhythmia detector, a bradycardia detector, a tachycardia detector, a counter. totalizer for counting detected disturbances and a binary display unit with sixteen positions.

This device detects arrhythmias in case the difference between the durations of the two intervals
Successive RRs exceed a constant reference value of 120 ms. In addition, it is capable of detecting any phenomenon of bradycardia or tachycardia if the frequency of the heart beats exceeds the prescribed upper and lower references.

 Here again, the simple comparison of the difference in the durations of two successive intervals of the ECS with the constant reference time value (120 ms #) does not reflect the dynamics of the normal variations in the frequency of the heartbeat under different conditions. As a result, bradycardia would result in a significantly increased number of erroneous positive conclusions, and tachycardia, an excessive number of false negative conclusions on the existence of an arrhythmia.

 The device also does not subdivide disturbances of the rhythm and frequency of heart contractions into various types, but only counts the total number of disturbances and displays this number in binary code which is very difficult to read.

 There is also a device for monitoring the cardiac action of the heart (see US Pat. No. 3,881,467) comprising a set for separating the R waves of the ECS, a set for determining the parameters of the ECS, the input of which is connected to the output of said wave separation assembly. From the DHW, a display unit whose inputs are associated with the outputs of the mentioned assembly for determining the parameters of the DHW, and a synchronizing circuit of which 11 input is connected to the output of the R wave separation assembly of ETCS and whose output is connected to the control input of the DHW parameter determination assembly.

 This last set is called to conform signals according to the results of the comparison of the interval times between the R waves of the DHW.

During this operation, a comparison takes place of the duration of the last interval RRi appeared between the waves R with that of the preceding normal interval h
Note that the interval that appeared last will only become '~' previous normal interval "for subsequent comparisons if it is at least equal to a determined percentage of the normal interval which preceded it.

In case inequality is realized
RRi at 0.8% (1) there is an extrasystole, whereas if
RRi 1,2 RRN (2) intermittence of contractions is recorded.

 If a disturbance of the rhythm is detected (the inequalities (1) and (2) being achieved, the interval between the second and third cardiac contractions following the disturbed contraction is taken as the normal interval for subsequent comparisons. one considers as normal interval that which follows the four successive intervals RR of greater width.

 This cardiac activity monitoring device also makes it possible to detect and count extrasystoles.

However, comparing the duration of the interval
RR appeared last with that of the RR interval "normal" quite often leads to erroneous conclusions on the number of extrasystoles.

 In addition, when making a judgment on the disturbances of the rhythm, one does not take into account the information concerning the ratio of the durations of intervals which preceded the analyzed intervals.

 Consequently, in the event of an increase in the frequency of appearance of extrasystoles, the number of extrasystoliúess- contractions of the heart will be determined incorrectly.

 In addition, certain combinations of the intervals with the interruptions in the contractions can give rise to the recording of extrasystoles which, in reality, did not occur.

 Finally, the device only detects and counts simple cases of single extrasystoles, while it is insensitive to possible dangerous phenomena such as bigemines, grouped extrasystoles or blockages.

 There is also known an apparatus for monitoring cardiac activity> which is the subject of US Pat. No. 3,658,055, which includes a set for separating R waves from the ECS and a set for determining the parameters of the ECS which reacts to the signal from the output of said R wave separation set from the DHW and provides at its first output a first signal when the absolute value of the difference between the duration of the interval last appeared between the R waves of 1 'ECS and that of the preceding interval between the R waves of the ECS is less than a determined percentage of the duration of the interval which appeared last between the R waves of the ECS, and a second signal when the absolute value of the difference between the duration of the interval which appeared last between the R waves of the DHW and that of the preceding interval between the R waves of the DHW is equal to said determined percentage of the duration of the interval appeared in last between R waves of the ECS or higher to said determined percentage of the duration of the interval last appeared between the R waves of the DHW, this same assembly providing at its second output a first signal when the duration of the interval which appeared last between the R waves of the ECs is less than the duration of the preceding interval between the R waves of the ECS, and a second signal, when the duration of the interval which appeared last between the R waves of the ECS is equal to that of the previous interval between R waves of the DHW or greater than the duration of said previous interval between the R waves of the DHW. Logic circuits are connected to the outputs of the mentioned set for determining the DHW parameters, the outputs of which are connected to the inputs of a memory and to the inputs of a display unit which counts and displays the detected results of the control of heart activity.

 The output of said R wave separation assembly of the DHW is connected to the input of a # synchronizing circuit, the respective outputs of which are connected to the control inputs of the assembly for determining the parameters of 1iECS, of the memory and of the display unit.

 If R @@ / RRn-1> 1,2 (where n and n-l are the numbers of the cardiac cycle which appeared last and that which preceded it), an RRf code is formed. On the other hand, if 0.85, c1 is the RRS code which is formed The set of these codes is memorized for several (four, for example) successions of cardiac cycles, the number of which is determined by the detected disturbance of the rhythm. In order to diagnose disturbances of the heart rhythm, the stored information is analyzed by means of logic circuits according to criteria which stem from experience acquired in clinical diagnosis. If all the symptoms corresponding to a specific arrhythmia are present at the same time, an appropriate logic circuit comes into operation and forms a signal characteristic of this type of arrhythmia.

In this way, ensuring the coding of the intervals
RR, storing codes during several successive cardiac cycles and 11 logical analysis of the data obtained, the device allows the control (diagnosis) of cardiac activity.

 However, such a diagnosis of heart rhythm disturbances requires that the number of RR intervals to be analyzed is at least three.

 In the case of diagnosis of complex types of arrhythmia, such as: bigemia, grouped extrasystoles, etc., the number of RR intervals to be analyzed increases considerably. is necessary to treat one. large volume of information, since the number of different combinations of the codes formed, which correspond to the various heart diseases, then becomes very large. However, since each of these combinations is analyzed by a corresponding logic circuit, the mounting of such a cardiac activity control device becomes extremely bulky, which makes it difficult to produce and use.

 The present invention therefore aims to create an apparatus for monitoring cardiac activity, which would simplify such monitoring by reducing the volume of information to be processed.

The objective thus posed is achieved thanks to the fact that the apparatus for controlling the cardiac activity, comprising a set of separation of the R waves from the electrocardio-signal, a set of determination of the parameters of the electrocardio-signal which reacts to the signal from of the output of said R wave separation assembly from the DHW and provides at its first output a first signal when the absolute value of the difference between the duration of the last interval appeared between the R waves of 11 DHW and that of the interval between the ETCS R waves which immediately precede it is less than a determined percentage of the duration of the last interval appeared between the ECS R waves, and a second signal when the absolute value of the difference between the duration of the last interval appeared between the R waves of SPECX and that of the interval between the R waves of the ETCS which immediately precedes it is equal to said determined percentage of the duration of the last interval appeared in be the ETCS R waves or higher than this determined percentage of the duration of the last interval appeared between the R waves of the ECS, and at its second output, a first signal when the duration of the last interval appeared between the R waves of ETCS is less than that of the interval between waves
R of the ECS which immediately precedes it, and a second signal when the duration of the last interval appeared between the R waves of the EC8 is equal to that of the interval between the R waves of the ECSgAi immediately preceding or greater at this duration of the immediately preceding interval between the R waves of the ECS, a logic circuit the first input of which is connected to the first output of said set of determination of the parameters of the ETCS and the second input of which is connected to the second output of this set of parameters for the ECS, a memory whose inputs are connected to the outputs of said logic circuit, a display unit which counts and displays the results of the cardiac activity control, the input of this unit being connected to the output of the logic circuit, and a synchronizing circuit whose input is connected to the output of said R wave separation assembly of the DHW, a first output, to the memory control input, a second outing , at the control input of the display unit, and a plurality of outputs, at the control inputs of the set for determining the parameters of the DHW, said apparatus being characterized, according to the invention, in that that said set for determining the parameters of the DHW is provided with a third output at which a first signal is formed when the difference between the duration of the last interval appeared between the waves
R of :: the DHW and that of the interval between the R waves of the DHW which immediately precedes the interval immediately preceding said last appeared interval is less than a preset value, and a second signal when said difference between the duration of the last interval between the R waves of the DHW and that of the interval between the R waves of the DHW which immediately precedes the interval immediately preceding the last appeared interval is equal to or greater than said preset value, said logic circuit being further provided with a third input connected to the third output of the set for determining the parameters of the DHW and of a plurality of inputs connected to the outputs of the memory, the reset inputs of the assembly for determining the parameters of 1ECS, of the memory and of the display unit being connected to a reset unit, the logic circuit being constructed so that it provides its outputs with a first comb inaison of signals when its first input is supplied with a second signal from the first output of the DHW parameter determination set, while its second input is supplied with a first signal from the second output of said DHW parameter determination set the ECS, and the memory contains the recorded code corresponding to the first, the third or the eighth combination of signals at the outputs of this logic circuit, that it provides at its outputs the same first combination of signals when its first input is supplied as the first signal from the first output of the DHW parameter determination set, and the memory contains the code corresponding to the first, third or eighth combination of signals of this logic circuit, that it provides its outputs with a second combination of signals when its first input is supplied with a second signal from the first output of the sensing assembly control of the DHW parameters, its second input is supplied with a second signal from the second output of the DHW parameter determination assembly, and the memory contains a code corresponding to the first, third or the eighth combination of signals at the outputs of this logic circuit, that it provides at its outputs a third combination of signals when its first input is supplied with a second signal from the first output of the set for determining the parameters of 1 ' DHW, its second input is supplied with the first signal from the second output of the DHW parameter determination unit, and the memory contains a code corresponding to the seventh combination of signals at the outputs of this logic circuit, that it provides its outputs with a fourth combination of signals when its first input is supplied with a second signal from the first output of the set for determining the parameters d in DHW, its second input is supplied with a second signal from the second output of the DHW parameter determination set, and the memory contains a code corresponding to the sixth combination of signals at the outputs of this logic circuit , that it supplies its outputs with the same fourth combination of signals when its first input is supplied with a second signal from the first output of the set for determining the parameters of the DHW, its second input is supplied with a second signal from of the second output - of the DHW parameter determination set, and the memory contains a code corresponding to the seventh combination of signals at the outputs of this logic circuit, that it supplies its outputs with a fifth combination of signals when its first input is supplied with a second signal from the first output of the DHW parameter determination unit, its second input is supplied with a second signal from the second output of the DHW parameter determination set, and the memory contains a code corresponding to the fourth or fifth combination of signals at the outputs of this logic circuit, that it provides at its outputs the fifth combination of signals when its first input is supplied as the first signal from the first output of the ECS parameter determination set, and the memory contains a code corresponding to the fourth or fifth combination of signals at the outputs of this logic circuit , that it provides its outputs with a sixth combination of signals when its first input is supplied with a second signal from the first output of the DHW parameter determination unit, its second input is supplied with the first signal from the second output of the DHW parameter determination set, and the memory contains a code corresponding to the fourth or fifth combination there are signals at the outputs of this logic circuit, that it provides at its outputs a seventh combination of signals when its first input is supplied with a second signal from the first output of the set for determining the parameters of the EC8, its second input is supplied with a second signal from the second output of the DHW parameter determination unit, and the memory contains a code corresponding to the second combination of signals at the outputs of this logic circuit, which it supplies to its outputs the seventh combination of signals when its first input is supplied with the first signal from the first output of the DHW parameter determination set, and the memory contains a code corresponding to the second combination of signals at the outputs of this logic circuit, that it provides its outputs with the same seventh combination of signals when its first input is supplied with a second signal from the first output of the set of parameters for 1'eus, its second input is supplied with the first signal from the second output of the set for determining the parameters of the DHW, its third input is supplied with the second signal from the third output of the set for determining the parameters of LBECS, and the memory contains a code corresponding to the second combination of signals at the outputs of this logic circuit, that it supplies at its outputs the seventh combination of signals when its first input is supplied with the first signal from the first output of the 1çECS parameter determination assembly, and the memory contains a code corresponding to the seventh combination of signals at the outputs of this logic circuit, which it supplies to its outputs the seventh signal combination when its first input is supplied with a second signal from the first output of the parameter determination set The DHW, its second input is supplied with the first signal from the second output of the DHW parameter determination set, and the memory contains a code corresponding to the sixth combination of signals at the outputs of this logic circuit, it supplies its outputs with the same seventh combination of signals when its first input is supplied with the first signal from the first output of the DHW parameter determination set, and the memory contains a code corresponding to the sixth combination of signals at the outputs of this logic circuit, and that it provides at its outputs an eighth combination of signals when its first input is supplied as a second signal from the first output of the DHW parameter determination set, its second input is supplied with the first signal from the second output of the DHW parameter determination unit, its third input is supplied with the first signal from l at the third output of the DHW parameter determination set, and the memory contains a code corresponding to the second combination of signals at the outputs of this logical circuit, while the display unit is designed in such a way that it can display the extrasystoles in the event of grouped extrasystole, the single extrasystoles, the ordinary blockages, dangerous blockages, the extrasystoles in the event of bigemina, and the normal rhythm, the extrasystole in the event of grouped extrasystole being displayed when outputs of said logic circuit is formed the first combination of signals, the unique extrasystole, when at other outputs of the logic circuit is formed the third combination of signals, ordinary blocking when at the outputs of the logic circuit is formed the fourth combination of signals, the dangerous blocking when at the outputs of the logic circuit is formed the fifth combination of signals, the extrasystole in case of bigemina when at the outputs of the log circuit ique is formed the eighth combination of signals, and the normal rhythm, when at the outputs of the logic circuit is formed the seventh combination of signals.

 In the proposed apparatus, at the third output of the set for determining the DHW parameters, during each cycle of analysis of the DHW, signals obtained as a result of the comparison of the difference between the duration of the last appeared interval (RRi) between the R waves of ETCS and that of the interval RRi 2 which precedes that taking place before said last appeared interval, with a fixed preset value, which makes it possible to distinguish between bigeminaemia, in which the interval following the extrasystole hardly differs from that preceding the extrasystolic interval, and the return to norm after a single or grouped extrasystole, when the interval following the last extrasystole (pause compensator) is significantly longer than the one preceding the interval before this last extrasystole.

 During each DHW analysis cycle, the logic circuit supplies its outputs with combinations of signals starting from the analysis of the signals coming from the outputs of the DHW parameter determination set, as well as those arriving from memory outputs.

This makes it possible to classify various disturbances of the heart rhythm into groups or to make a preliminary judgment on this rhythm, which judgment, although not displayed, makes it possible then to formulate, at: a later stage of the analysis, a definitive conclusion. In doing so, the rhythm is characterized on the basis of the results of the comparison of the last interval appeared between the R waves of the ECS with one or two previous intervals, taking into account the conclusion on the heart rate made during the previous stage of analysis. of the ECS and containing the information on the rhythm which took place before the analysis.

 Consequently, we analyze only three informational parameters, namely the ratio between the duration of the last interval appeared between the R waves of the ECS and that of the interval which precedes it, the ratio between the duration of the last appeared interval and that of the interval preceding that which takes place before said last interval appeared, and the conclusion on the heart rate obtained during the preceding stage of analysis of the ECS. As the latter includes, in a brief form, the information on the heart rate before the analysis, the following conclusion will obviously be formed on the basis of sufficiently complete data concerning the heart rate, and this, with a relatively small volume of the information to be processed.

The introduction of a reset assembly into the assembly of the proposed cardiac activity control device makes it possible to deliver, at the instant of triggering of the device, a reset signal. initial state, which will be applied to the reset inputs of the DHW parameter determination unit, the memory and the display unit. On receipt of said reset signal, the set for determining the parameters of the ETCS and the memory are put into a state corresponding to the rhythm as normal disc, while the display unit is preparing to analyze the information arriving there. The reset signal remains applied to the reset inputs of the DHW parameter determination unit, the memory and the display unit for the time necessary for the formation of '' at least three RR intervals, so that the ETCS parameter determination set can accumulate the information that will be used for the analysis
I1 is atile that apparatus for controlling 1 cardiac activity further comprises a set of preselection of initial conditions, capable of being placed in any one of three positions and having its first input connected to the -first output of the set of determination of DHW parameters, its second input linked to the second output of the DHW parameter determination set, its reset input linked to the output of the reset set , its first output connected to the first input of the logic circuit and its second output connected to the second input of the logic circuit, so that, when this set of preselection of the initial conditions is put in the first of said three positions, it provides its first output a signal identical to the first signal present at the first output of the DHW parameter determination set, and at its second output, a signal identical to the first signal at the second output ie the set for determining the parameters of the ECS, if the first input is attacked by the first signal from the first output of the set for determining the parameters of the ECS and the second entry is attacked by the first signal from the second output of the EC8 parameter determination set, or if the first input is attacked by the first signal from the first output of the ETCS parameter determination set and its second input is attacked by the second signal from the second output of the DHW parameter determination set, or if its first input is attacked by the second signal from the first output of the DHW parameter determination set parameters of 1? EUS and its second input is attacked by the first signal from the second output of the set of parameters determination of llECSv and celfusqut at the moment when its first input is for the first attacked by the second signal from the first output of the ETCS parameter determination set and its second input is at the same time attacked by the second signal from the second output of the parameter determination set of 1 'ECS, after which said set of initial conditions preselection will form at its outputs signals similar to those present at its respective inputs, that when this set of initial conditions preselection is put in the second of said three positions, it delivers at its first output a signal identical to the first signal present at the first output of the DHW parameter determination set, and at its second output, a signal identical to the first signal at the second output of the DHW parameter determination set the ECS, if its first input is attacked by the first signal from the first output of the set for determining the parameters of the ECS and its second input is attacked by the first signal from the second output of the DHW parameter determination set, or if its first input is attacked by the first signal from the first output of the DHW parameter determination set parameters of the DHW and its second input is attacked by the second signal from the second output of the set for determining the parameters of the DHW, or even if its first input is attacked by the second signal from the first output of the DHW parameter determination set and its second input is attacked by the second signal from the second output of the DHW parameter determination set, and this, until the moment where its first input will be attacked for the first time by the second signal from the first output of the DHW parameter determination set and its second input will be simultaneously attacked by the first signal from of the second output of the DHW parameter determination set, after which this initial condition preselection set will supply its outputs with signals analogous to those present at its respective inputs, and that when put into the third of said three positions, the set of preselection of initial conditions delivers to its outputs signals identical to those present at its inputs.

 The introduction, in the assembly of the apparatus, of a set of preselection of the initial conditions makes it possible to avoid an erroneous functioning of the apparatus at the start of the analysis of the DHW, after the switching on of this apparatus. In the event of a disturbed heart rhythm, there may appear, immediately after switching on the device, an interval between the R waves of the ECS which would have a normal duration, as in the cases of extrasystole, blockage or compensatory break. In such a case, by comparing the duration of the abnormal interval with that of a following interval, one will arrive at erroneous conclusions on the heart rate. However, the preselection of the initial conditions makes it possible to proceed with the heart rate analysis only under strictly determined conditions, avoiding any failure of the cardiac activity control device, so that a variation in the duration of the last RR interval appeared compared to that of the previous RR interval corresponds to the nature of the heart rate specific to the subject under examination. The initial conditions in question are imposed by the doctor based on the data previously obtained, relating to the patient's heart rate (by the interpretation of the electrocardiogram, the observation of the ECS on the screen of an oscilloscope , etc.).

 The set of preselection of the initial conditions is put in the first position in the event of frequent appearances of RR intervals of excessive length, corresponding to the interruptions of the ventricular contractions.

Under these conditions, the analysis of the rhythm begins only when a complex of signs appears corresponding to the increase in the last RR interval appeared in comparison with the previous interval.

 This set is placed in the second position in case of frequent appearances of shortened RR intervals corresponding to bigemina, grouped extrasystoles and unique but very frequent extrasystoles. In this case, the analysis of the heart rate starts only after obtaining a whole complex of characteristic signs of the shortening of the last RR interval appeared compared to the previous interval.

The unit is placed in the third position when the heartbeat has a regular character or when there is, on the background of such a correct rhythm, abrupt single arrhythmias, so that the probaUlite that the analysis of 1 ' ECS covers an interval
Modified RR is quite low With this reserve, you can carry out a rhythm analysis immediately after the device is activated.

It is advantageous for the logic circuit to comprise a first AND circuit, the first input of which is connected to the first output of the DHW parameter determination set and the second input of which is connected to the second output of said DHW parameter determination set. the DHW, a second AND circuit whose non-inverting input is connected to the first output of the set for determining the parameters of the EC :: S3 and whose inverting input is connected to the second output of said set of determination of DHW parameters, a NON circuit whose input is connected to the first output of the IOECS parameter determination set, a third AND circuit whose first input is connected to the output of the second AND circuit, a fourth circuit
AND whose first input is connected to the output of the circuit
NO, a fifth AND circuit, the first input of which is connected to the output of the first AND circuit, a sixth circuit
AND the first input of which is connected to the output of the second circuit AND, a seventh circuit AND the first input of which is connected to the output of the second circuit AND, an eighth circuit AND of which the first input is connected to the output of the first circuit AND, a ninth AND circuit, the first input of which is connected to the output of the first circuit
AND, a tenth AND circuit, the first input of which is connected to the output of the first circuit AND, an eleventh AND circuit, the first input of which is connected to the output of the circuit NO, a twelfth AND circuit, the first input of which is connected to the output of the second AND circuit, a thirteenth AND circuit, the first input of which is connected to the output of the NO circuit, a fourteenth AND circuit, the first input of which is connected to the output of the first AND circuit, a fifteenth AND circuit, the first input of which is connected at the output of the second AND circuit, a sixteenth AND circuit, the first input of which is connected to the output of the NO circuit, a seventeenth AND circuit, the first input of which is connected to the output of the NO circuit, an eighteenth AND circuit whose inverting input is connected to the third output of the DHW parameter determination set and whose non-inverting input is connected to the output of the sixth AND circuit, - a nineteenth circuit
AND the first input of which is connected to the third output of the set for determining the parameters of 1tECS and the second input of which is connected to the output of the sixth circuit AND, a first OR circuit the first input of which is connected to the output of the third AND circuit and whose second input is connected to the output of the fourth AND circuit, a second OR circuit whose first input is connected to the output of the eighth AND circuit and whose second input is connected to the output of the ninth circuit
AND, a third OR circuit whose first input is connected to the output of the tenth AND circuit and whose second input is connected to the output of the eleventh circuit AND, a fourth OR circuit whose first input is connected to the output of the thirteenth circuit AND, the second entry, at the exit of the fourteenth circuit AND, the third entry, at the exit of the fifteenth circuit AND, the fourth entry, at the exit of the sixteenth circuit AND, the fifth entry, at the exit of the seventeenth circuit AND, and the sixth input, at the output of the nineteenth circuit AND, that the memory includes a first OR circuit, the first input of which is connected to the output of the first OR circuit of the logic circuit, the second input, to the output of the seventh AND circuit of the logic circuit, and the third input, at the output of the eighteenth AND circuit of the logic circuit, a second OR circuit, the first input of which is connected to the output of the second OR circuit of the logic circuit, and the second input leaving the third circuit
OR of the logic circuit, a first flip-flop whose inflation # e is connected to the output of the first circuit OR of the memory, while its synchronization input is connected to the first output of the circuit # ndIroni ~ sant , its input resets to zero at the output of the reset unit, and its output at the second inputs of the third, fourth and fifth circuits AND of the logic circuit, a second flip-flop whose information input is connected to the output of the fifth circuit
AND of the logic circuit, while its synchronization input is connected to the first output of the synchronizing circuit, its reset input, to the reset lens output, and its output, to the second inputs sixth, thirteenth and fourteenth circuits AND of the logic circuit, a third flip-flop whose information input is connected to the output of the second OR circuit of the memory, while its synchronization input is connected to the first output of the synchronizing circuit , its reset input, at the output of the reset assembly, and its output, at the second inputs of the tenth, eleventh and twelfth circuits AND of the logic circuit, a fourth flip-flop whose input d information is connected to the output of the twelfth AND circuit of the logic circuit, while its synchronization input is connected to the first output of the synchronizing circuit, its reset input, to the reset set output and its output, at the second inputs is eighth, fifteenth and sixteenth AND circuits of the logic circuit, and a fifth flip-flop whose information input is connected to the output of the fourth OR circuit of the logic circuit, while its synchronization input is connected to the first output of the synchronizing circuit, its reset input, to the output of the reset assembly, and its output, to the second inputs of the seventh, ninth and seventeenth circuits AND of the logic circuit, and that the display unit comprises a first circuit
AND whose first input is connected to the output of the fourth OR circuit of the logic circuit, and the second input, to the second output of the synchronizing circuit, a second AND circuit whose first input is connected to the output of the first OR circuit of the circuit logic, and the second input, at the second output of the synchronizing circuit, a third AND circuit, the first input of which is connected to the output of the seventh AND circuit of the logic circuit, and the second input, to the second output of the synchronizing circuit, a fourth AND circuit, the first input of which is connected to the output of the second circuit
OR of the logic circuit, and the second input, at the third output of the synchronizing circuit, a fifth AND circuit, the first input of which is connected to the output of the third circuit OR of the logic circuit, and the second input, to the second output of the circuit synchronizing, a sixth AND circuit whose first input is connected to the output of the eighteenth AND circuit of the logic circuit, and the second input, to the second output of the synchronizing circuit, a first counter whose counting input is connected to the output of the second AND circuit of the display unit, and the reset input, at the output of the reset assembly, a second counter whose counting input is connected to the output of the third circuit AND of the display unit, the reset input, at the output of the reset assembly, a third counter whose counting input is connected to the output of the fourth circuit
AND of the display unit, and the reset input, at the output of the reset assembly, a fourth counter whose counting input is connected to the output of the fifth circuit AND of the display unit, and the reset input, at the output of the reset assembly, a fifth counter whose counting input is connected to the output of the sixth circuit AND of the display unit S and the reset input, at the output of the reset assembly, a first indicator control block, the input of which is connected to the output of the first circuit
AND of the display unit, a second indicator control block, the inputs of which are connected to the outputs of the first counter, a third indicator control block, the inputs of which are connected to the outputs of the second counter, a fourth indicator control block, the inputs of which are connected to the outputs of the third counter, a fifth indicator control block, the inputs of which are connected to the outputs of the fourth counter, a sixth indicator control block, whose inputs are connected to the outputs of the fifth counter, a first indicator displaying the normal rhythm, whose input is connected to the output of the first indicator control block, a second indicator to display the number of extrasystoles in case of grouped extrasystole, whose inputs are connected to the outputs of the second indicator control block, a third indicator to display the number of unique extrasystoles, whose inputs are connected to the outputs of the third indicator control block, a fourth indicator to display the number of blockages, the inputs of which are connected to the outputs of the fourth indicator control block, a fifth indicator to display the number of dangerous blocks, the inputs of which are connected to the outputs of the fifth indicator control block, and a sixth indicator to display the number of extrasystoles in the event of bigeminias, the inputs of which are connected to the outputs of the sixth indicator control block.

It is also advantageous that the set of preselection of the initial conditions comprises a first EXCLUSIVE OR circuit whose first entry constitutes the first entry of said set of preselection of the initial conditions, a second EXCLUSIVE OR circuit of which the first entry constitutes the second entry of l set of preselection of the initial conditions, an OR-NO circuit whose first and second inputs are respectively connected to the outputs of the first and second OR circuits
EXCLUSIVE, a NON circuit whose input is combined with the second input of the first circuit OR EXCLUSIVE, a circuit
OR whose first input is connected to the output of said circuit NO-AND and whose second input is connected to the output of said circuit NO, a first AND circuit whose first input is connected to the first input of the first circuit OR EXCLUSIVE, its se # wave input, at the output of the OR circuit, and whose output constitutes the first output of the set of preselection of initial conditions, a second AND circuit whose first input is connected to the first input of the second OR EXCLUSIVE circuit, its second input, at the output of the OR circuit, and the output of which constitutes the second output of the set of preselection of the initial conditions, a flip-flop whose input for bringing to the state is connected to the output of the OR circuit, while its reset input is connected to the output of the reset set, and the output, to the third input of the OR circuit, and a switch to apply, in its first position, to the second input of the first circuit OR EXC LUSIF a signal identical to the second signal present at the first output of the set for determining the ETCS parameters and at the second input of the second circuit OR EXCLUSIVE, a signal identical to the second signal at the second output of the set of determination of the parameters of the DHW, to apply in its second position, to the second input of the first circuit
OR EXCLUSIVE, a signal identical to the second signal present at the first output of the ETCS parameter determination set and at the second input of the second circuit OR EXCLUSIVE, a signal identical to the first signal present at the second output of l 'DHW parameter determination set, and to apply, in its third position, to the input of the NO circuit, a signal identical to the first signal at the first output of the parameter determination set of 1'] DHW.

 It is advantageous that the apparatus for controlling cardiac activity further includes a vibrator, the input of which is connected to the third control input of the synchronizing circuit and the output of which is connected to the second input of said synchronizing circuit of a generator. pulses whose trigger input is connected to the third synchronizing circuit input, the stop input, to the output of said univibrator, and the output, to the second information input of the parameter determination unit l1ECS, a flip-flop whose information input is connected to the fourth output of the set for determining the parameters of the ECS, while its status and synchronization inputs are connected to two outputs, among the plurality of outputs of the synchronizing circuit, connected to the control inputs of the set for determining the parameters of the DHW, the inverted output of this flip-flop being connected to the second reset input of the memo ire, and its direct output, to the authorization input of the display of the display unit, and a fault indicator whose input is connected to the reverse output of the scale.

The introduction, in the assembly of the device to control the cardiac activity, of a univibrator, a generator of impulses, a rocker and an indicator of failure makes it possible to carry out an automatic control of the operation of the main assemblies of the apparatus, that is to say of the R wave separation assembly of the DHW, of the DHW parameter determination assembly and of the synchronizing circuit, this is ie sets on which the correct measurement and comparison of the time parameters of the DHW depends. This control is carried out after each cycle of analysis of the rhythm of the cardiac contractions by way of the formation of a verification arrhythmia, the detection of which makes it possible to confirm the good state of the main assemblies of the apparatus. verification arrhythmia, a fault signal is formed and displayed, a combination of signals corresponding to the normal heart rhythm is stored in the memory, and subsequent analysis of the rhythm is carried out with reference to this combination
The invention will be better understood and other objects, details and advantages thereof appear better in the light of the explanatory description which will follow of various embodiments given solely by way of nonlimiting examples, with references to the accompanying non-limiting drawings in which
- Figure 1 shows the block diagram of the apparatus for controlling cardiac activity, in accordance with an embodiment of the invention;
- Figure 2 shows the block diagram of the device for controlling cardiac activity, according to another embodiment;
- Figure 3 shows the block diagram of the set for determining the parameters of the DHW in accordance with the preferred embodiment of the invention;
- Figure 4 shows the block diagram of the logic circuit produced according to the preferred embodiment;
- Figure 5 is a block diagram of the memory according to the preferred embodiment of the invention;
- Figure.6 shows the block diagram of the display unit designed according to the preferred embodiment;
- Figure 7 is a block diagram of the set of preselection of initial conditions, according to the preferred embodiment;
- Figure 8 shows the block diagram of the apparatus for controlling cardiac activity ,. produced in accordance with yet another embodiment of the invention;
FIGS. 9a to 9e illustrate the time diagrams of variation of the signals at the outputs of various assemblies as a function of time;
FIG. 10 is a table illustrating the change of state of the flip-flops of the memory as a function of the logic signals present on the lines of the set for determining the parameters of llECS; and
- Figures 11a to 11f are examples of electro-cardiosignals (ECS) illustrating the operation of the device.

The apparatus proposed for countering the cardiac activity of human beings starting from the electrocardiosignal comprises a set 1 (FIG. 1) for separating the R waves from the ECS having an input and an output, a set 2 for determining the parameters of the ECS provided with an information input, a plurality of control inputs, a reset input, an output 3, an output 4 and an output 5 , a logic circuit 6 with inputs 7, 8, 9, a plurality of inputs 10 and a plurality of outputs, a memory II provided with a plurality of information inputs, a control input, a reset input and a plurality of outputs, a display unit 12 having a plurality of information inputs, a control input and a reset input, a synchronizing circuit 13 provided with one input, of a plurality 14 of control outputs constituted by outputs 14a, 14b, 14c, 14d and
control outputs 15, 16, and a set 17 for resetting, having an output.

In this device, the input of the R wave separation assembly 1 of the DHW is connected to a sensitive element constituted for example by the electrodes (not shown) used for reading the subject's electrocardiogram. The output of this R wave separation assembly 1 of the DHW is connected to the information input of the assembly 2 for determining the parameters of the ETCS and to the input of the synchronizing circuit 13. The inputs of the plurality of control inputs of the set 2 for determining the DHW parameters are connected to the respective outputs of the plurality 14 of control outputs of the synchronizing circuit 15. The reset input of the set 2 for determining the DHW parameters is connected to the output of the reset 17 assembly. The output 3 of the set 2 for determining the DHW parameters is connected to the input 7 of the logic circuit 6 The output 4 of the set 2 for determining the DHW parameters is connected to 11 input 8 of the logic circuit 6 The output 5 of lt the set 2 for determining the parameters of the DHW is connected to the input 9 of the logic circuit
The outputs of the plurality of outputs of the logic circuit 6 are connected to the respective inputs constituting the plurality of information inputs of the memory 11 and to those of the plurality of information inputs of the display unit 12. The outputs of the plurality of outputs of the memory II are connected to the respective inputs of the plurality 10 of inputs of the logic circuit 6
The memory control input Il is connected to the control output 15 of the synchronizing circuit 13. The reset input of this memory It is connected to the output of the reset unit 17 .

 The control input of the display unit 12 is connected to the output 16 of the synchronizing circuit 13, while the reset input of this same display unit 12 is connected to the output of the assembly 17 reset.

 FIG. 2 represents the block diagram of the apparatus for controlling the cardiac activity starting from an electrocardiosignal, into which one has introduced, in order to exclude any possibility of erroneous functioning of the apparatus at the initial stage of analysis of the DHW, a set 18 for preselecting the initial conditions, having information inputs 19 and 20, a reset input and outputs 21 and 22. In this arrangement, the output 3 of the determination set 2 of the DHW parameters is connected to the information input 19 of said set 18 of initial condition preselection, the output 4 of this set 2 for determining the DHW parameters is connected to the information input 20 of said set 18 for preselecting the initial conditions, the output 21 of the latter is connected to the input 7 of the logic circuit 6, its output 22, to the input 8 of said logic circuit 6, and its reset input, to the exit from the reset unit 17.

 The set 2 for determining the parameters of the DHW comprises a pulse generator 23 (FIG. 3), a frequency divider 24 with a division ratio equal to 5, counters 25, 26 and 27, a reversible counter 28, registers 29, 30 and 31, a shift register 32, line conformers 33, 34, 35, 36, 37 and 38, a comparator 41 and flip-flops 42, 43 and 44.

 The input of the pulse generator 23 constitutes that of the assembly 2 for determining the parameters of the DHW and is connected to the output of the assembly 1 for separating the R waves of the DHW. The output of the generator 23 is connected to the input of the divider 24, to the counting input of the counter 26, to the counting input of the counter 27 and to the countdown input of the reversible counter 28. The output of the divider 24 is connected to the counting input of the counter 25. The reset inputs of the counters 25, 26 and 27 are connected to the output 14a forming part of the plurality of outputs 14 of the synchronizing circuit 13.

 The recording control input of the reversible counter 28 is connected to the output 14b forming part of the plurality of outputs 14 of the synchronizing circuit 13.

 The outputs of the plurality of outputs of the counter 25 are connected to the respective inputs of the plurality of information inputs of the register 29. The outputs of the plurality of outputs of the counter 26 are connected to the respective inputs of the plurality of inputs d register information 30. The outputs of the plurality of outputs of the counter 27 are connected to the respective inputs of the plurality of information inputs of the shift register 32 and to those of the plurality of information inputs of the reversible counter 28. The outputs of the plurality of outputs of the reversible counter 28 are connected to the respective inputs of the plurality of information inputs of register 31. The recording inputs of registers 29, 30, 31 and the offset input of the shift register 32 are connected to the output 14c forming part of the plurality 14 of control outputs of the synchronizing circuit 13.

 The outputs of the plurality of outputs of the register 29 are connected to the respective inputs of the plurality of information inputs of the line shaper 33.

 The outputs of the plurality of outputs of the register 30 are connected to the respective inputs of the plurality of information inputs of the line shaper 34.

 The outputs of the first plurality of outputs of the shift register 32 are connected to the respective inputs of the plurality of information inputs of the line shaper 35.

 The outputs of the second plurality of outputs of the shift register 32 are connected to the respective inputs of the plurality of information inputs of the line transformer 36.

 The outputs of the third plurality of outputs of the shift register 32 are connected to the respective inputs of the plurality of information inputs of the line shaper 37.

 The outputs of the plurality of outputs of register 31 are connected to the respective inputs of the plurality of information inputs of line shaper 38.

 The control inputs of the line conformers 33 and 38 are connected to the output 14b forming part of the plurality 14 of control outputs of the synchronizing circuit 13.

 The control inputs of the line transformers 35 and 36 are connected to the output 14c forming part of the same plurality 14 of control outputs of the synchronizing circuit 13.

 The control inputs of the line conformers 34 and 37 are connected to the output 14d of this same plurality 14 of control outputs of the synchronizing circuit 13.

 The outputs of the pluralities of outputs of the line conformers 33, 34 and 35 are combined in a common bar 39. Likewise, the outputs of the pluralities of outputs of the line conformers 36, 37 and 38 are associated in a common bar 40.

 The outputs of the bar 39 are connected to the respective inputs of the first plurality of information inputs of the comparator 41, while the outputs of the bar 40 are connected to the respective inputs of the second plurality of information inputs of the comparator 41.

 The output of the latter is connected to the information inputs of flip-flops 42, 43 and 440 The synchronization input of flip-flop 42 is connected to the output 14b of the plurality 14 of control outputs of the synchronizing circuit 13, l ' flip-flop synchronization input 43, at output 14a of the same plurality 14 of control outputs of the synchronizing circuit 13, and flip-flop synchronization input 44, at output 14d of said plurality 14 of control outputs of the synchronizing circuit 13.

 The direct output of the flip-flop 42 constitutes the output 3 of the assembly 2 for determining the parameters of the DHW. The inverted output of the flip-flop 43 constitutes the output 4 of said set 2 for determining the parameters of the DHW, and the inverted output of the flip-flop 44 forms the output 5 of the same set 2 for determining the parameters of the DHW.

Logic circuit 6 (Figure 4) includes circuits
AND 45.46, 47, 48, 49, 50, 51, 52, 53, 54, 55s 56, 57, 58, 59, 60, 61, 62, and 63, OR circuits 64, 65, 66 and 67, as well as a NON 68 circuit. The memory 11 (FIG. 5) comprises OR circuits 69, 70 and flip-flops 71, 72, 73, 74, and 75. The display unit 12 (FIG. 6) comprises circuits AND 76, 77, 78, 79, 80 and 81, counters 82, 83, 84, 85 and 86, indicator control blocks 87, 88, 89, 90, 91 and 92, as well as indicators 93, 94, 95, 96, 97 and 98.

 More specifically, the components of logic circuit 6 are interconnected as follows.

The first input of the AND 45 circuit (Figure 4), the first input of the AND 46 circuit and the input of the circuit
NO 68 are combined together by constituting the input 7 of said logic circuit 6.

The second input of the AND circuit 45 and the second (inverting) input of the AND circuit 46 are combined to form 1 t input 8 of the logic circuit 6
The output of the AND circuit 45 is connected to the first input of the AND circuit 50, to the first input of the circuit
AND 53, at the first input of the AND circuit 54, at the first input of the AND circuit 55 and at the first input of the AND circuit 59.

The output of the AND circuit 46 is connected to the first input of the AND circuit 48, to the first input of the circuit
AND 51, at the first input of the circuit AND 52, at the first input of the circuit AND 57 and at the first input of the circuit
AND 60.

The output of circuit NON 68 is connected to the first input of circuit AND 49, to the first input of circuit
AND 56, at the first input of the AND circuit 58, at the first input of the AND circuit 61 and at the first input of the AND circuit 47.

 The second inputs of the AND circuits 48, 49 and 50 are connected to the output of the flip-flop 71 (FIG. 5) of the memory Il.

 The second inputs of the AND circuits 51 <, 58, 59 (FIG. 4) are connected to the output of the flip-flop 72 (FIG. 5) of the memory 11.

 The second inputs of the AND circuits 52, 54, 47 (FIG. 4) are connected to the output of the flip-flop 75 (FIG. 5) of the memory Il.

 The second inputs of the AND circuits 53, 60, 61 (FIG. 4) are connected to the output of the flip-flop 74 (FIG.

5) from memory II.

 The second inputs of the AND circuits 55, 56, 57 (FIG. 4) are connected to the output of the flip-flop 73 (FIG. 5) of the memory 11.

The output of the AND circuit 48 (Figure 4) is connected to the first input of the OR circuit 67. The output of the circuit
ET 49 is connected to the second input of this same circuit
OR 67.

 The inverting input of the AND circuit 62 and the first input of the AND circuit 63, together, constitute the input 9 of the logic circuit 6. The second inputs of the AND circuits 62 and 63 are connected to the output of the AND circuit 51.

The output of the AND circuit 63 is connected to the first input of the OR circuit 66.

 The output of AND circuit 53 is connected to the first input of OR circuit 64, and the output of OR circuit 54, to the second input of this OR circuit 64.

 The output of AND circuit 55 is connected to the first input of OR circuit 65, and the output of AND circuit 56, to the second input of said OR circuit 65.

The output of the AND circuit 58 is connected to the second input of the OR circuit 66. The output of the AND circuit 59 is connected to the third input of the OR circuit 66. The output of the circuit 60 is connected to the fourth input of the circuit
OR 66. The output of circuit 61 is connected to the fifth input of circuit OR 66. Finally, the output of circuit AND 47 is connected to the sixth input of circuit OR 66.

 The elements of memory II are interconnected in the following manner.

 The first input of OR circuit 69 (Figure 5) is connected to the output of OR circuit 67 (Figure 4) of logic circuit 6. The second input of OR circuit 69 (Figure 5) is connected to the output of AND circuit 52 ( figure 4) of logic circuit 6. The third input of OR circuit 69 (figure 5) is connected to the output of AND circuit 62 (figure 4) of logic circuit 6. The output of OR circuit 69 (figure 5) is connected to the information input of scale 71.

The information input of the flip-flop 72 is connected to the output of the AND circuit 50 (Figure 4) of the logic circuit 6. The rear input of the OR circuit 70 (Figure 5) is connected to the output of the OR circuit 64 (Figure 4) of the logic circuit 6. The second input of the OR circuit 70 (FIG. 5) is connected to the output of the circuit
OR 65 (figure 4) of logic circuit 6.

The output of circuit # OR 70 is connected to the data input of flip-flop 73.

 The information input of flip-flop 74 (Figure 5) is connected to the output of AND circuit 57 (Figure 4) of logic circuit 6.

 The information input of the scale 75 ~ (Figure 5) is connected to. the output of the OR circuit 66 (FIG. 4) of the logic circuit 6.

The synchronization inputs of flip-flops 71, 72, 732 74 and 75 ligure 5) are connected to the control output 15 (figure 1) of the synchronizing circuit 13
The inputs for resetting the flip-flops 71, 72, 73, 74 and the input for resetting the flip-flop 75 are connected to the output of the reset 17 assembly (FIG. 1) .

The elements of the display unit 12 are interconnected as follows
The first input of AND circuit 76 (Figure 6) is connected to the output of OR circuit 67 (Figure 4) of logic circuit 6.

 The first inputs of the AND circuit 77 (FIG. 6) are connected to the output of the OR circuit 63 (FIG. 4) of the logic circuit 6.

 The first input of AND circuit 78 (Figure 6) is connected to the output of AND circuit 52 (Figure 4) of logic circuit 6.

The first input of AND circuit 79 is connected to the output of OR circuit 64 (Figure 4) of logic circuit 6
The first # input of AND circuit 80 (Figure 6) is connected to the output of OR circuit 65 (Figure 4) of logic circuit 6.

The first input of AND circuit 81 (Figure 6) is connected to the output of AND circuit 62 (Figure 4) of logic circuit 6
The second inputs of the AND circuits 76, 77, 78, 79, 80 and 81 (figure 6) are connected to the output 16 (figure 1) of the synchro.zqsant 13 circuit.

 The output of the AND circuit 76 (FIG. 6) is connected to the input of the indicator control block 87, the output of which is connected to the input of the indicator 93.

 The outputs of each of the AND circuits 77, 78, 79, 80 and 81 are respectively connected to the counting inputs of the counters 82, 83, 84, 85 and 86.

 The pluralities of outputs of counters 82, 83, 84, 85 and 86 are respectively connected to the pluralities of inputs of blocks 88, 89, 90, 91 and 92 of indicator control.

The pluralities of outputs of the indicator control blocks 88, 89, 90, 91 and q2 are linked to the pluralities of inputs of the respective indicators 94, 95, 96, 97 and 98
The inputs for setting the counters 82, 83, 84, 85 and 86 are connected to the output of the assembly 17 (FIG. 1) for resetting to the initial state.

 The indicator 93 (FIG. 6) is used to display the normal rhythm, the indicator 94, the number of extrasystoles in the event of grouped extrasystolies, the indicator 95, the number of unique ex trasystoles, the indicator 96, the number of ordinary blockages, the indicator 97, the number of dangerous blockages, and the indicator 98, the number of extrasystoles in the event of bigemia.

The set 18 for preselecting the initial conditions comprises a coupled switch 99 (FIG. 7) with three positions, EXCLUSIVE OR circuits 100 and 101, an OR circuit
NO 102, a circuit NO 103, a circuit OR 104, circuits
ET 105, 106 and a flip-flop 107e In this set, the first input of the circuit AND 105 and the first input of the circuit
OR EXCLUSIVE 100 are combined and constitute input 19 of the assembly. The first input of circuit AND 106 and the first input of circuit OR EXCLUSIVE 101, also combined together, form input 20 of the same set 18 for preselection of conditions initials
When the switch 99 is in its first position, the second input of the EXCLUSIVE OR circuit 100 and the second input of the EXCLUSIVE OR circuit 101 are connected to a voltage source E of the logic unit. When the switch 99 occupies its second position, the second input of the EXCLUSIVE circuit 100 connects to the aforesaid source E of voltage of the logic unit, while the second input of the EXCLUSIVE circuit 101 connects to the common conductor. in the third position of switch 99, the second input of the EXCLUSIVE OR circuit 100 and the second input of the EXCLUSIVE OR circuit 101 are connected to said common conductor. Leaving the circuit
OR EXCLUSIVE 100 is connected to the first input of the circuit
YES-NO 102. The output of the EXCLUSIVE OR circuit 101 is connected to the second input of said circuit YES-NO 102. The output of the latter is connected to the first input of the OR circuit 104. The second input of the circuit EXCLUSIVE 100 is connected to switch 99 and to the input of circuit NO 103.

The output of the latter is connected to the second input of the OR circuit 104. The output of the OR circuit 104 is connected to the second input of the AND circuit 105, to the second input of the AND circuit 106 and to the reset input. the state of the scale 107.

 The reset input of the flip-flop 107 is connected to the output of the reset assembly 17 (FIG. 1). The input of flip-flop 107 (Figure 7) is connected to the third input of the OR circuit 104.

 The output of the AND circuit 105 constitutes the output 21 of the assembly 18 for preselecting the initial conditions, while the output of the AND circuit 106 forms the output 22 of this assembly 18.

 FIG. 8 illustrates the block diagram of the apparatus for controlling the cardiac activity of human beings starting from an electrocardiosignal, the mounting of which, in order to improve the certainty of the diagnosis of arrhythmias, is equipped with a univibrator 108 having a trigger input and an output, of a pulse generator 109 having a trigger input, a stop input. and. an output, a flip-flop 110 and a fault indicator 111. The assembly 2 for determining the parameters of the DHW is also provided with a second information input and a fourth output 112. The synchronizing circuit 13 is further provided with a second input, and the plurality of outputs 14 of this synchronizing circuit includes outputs 14a, 14b, 14c, 14d, 14e, 14f, 14g. In addition, the synchronizing circuit 13 is provided an output 113, the memory 11, a second zero entry, and the display unit 12, a display authorization input.

 In this arrangement, the trigger input of the univibrator 108 is connected to the control output 113 of the synchronizing circuit 13. The output of this univibrator 108 is connected to the second input of the synchronizing circuit 13 and to the input of pulse generator 109 stop. The trigger input of the latter is connected to the output 113 of the synchronizing circuit 13 and the output of the generator 109, to the second information input of the set 2 for determining the parameters of the 'ECS. The information input of the flip-flop 110 is connected to the output 112 of the assembly 2 for determining the parameters of the DHW.

The synchronization input and input for bringing the state of the flip-flop 110 are connected to the outputs 14f and 14g of the synchronizing circuit 13. The inverted output of the flip-flop 110 is connected to the input of the fault indicator 111 and to the second memory reset input 11. The direct output of the flip-flop 110 is connected to the display authorization input of the display unit 12.

 In this variant, the assembly 2 (FIG. 3) for determining the parameters of the DHW also comprises a register 114 for intermediate storage of the interval duration RR. The inputs of the plurality of information inputs of register 114 are connected to the respective outputs of the plurality of outputs of counter 27.

The register input 114 is connected to the output 14b of the plurality 14 of control outputs of the synchronizing circuit 13. The outputs of the plurality of outputs of the register 114 are connected to the respective inputs of the plurality of inputs d reversible counter information 28.

The reset input of each of the counters 25, 26 and 27 is connected to the outputs 14a and 14g of the synchronizing circuit 13 via an OR circuit 115 (Figure 8), The recording control input of the reversible counter 28 (figure 3) is connected to the outputs 14b and 14g of the synchronizing circuit 13 through an OR circuit 116 (figure 8). The recording input of each of the registers 29 and 31 (figure 3) is connected to the outputs 14c and 14e of said synchronizing circuit 13 via a circuit
OR 117 (Figure 8) Finally, the control input of each of the line conformers 33 and 38 (Figure 3) is connected to the outputs 14b and 14f of this synchronizing circuit 13 via an OR circuit 118 (Figure 8)
The input of the frequency divider 24 (FIG. 3), the counting inputs of the counters 26 and 27 and the countdown input of the reversible counter 28 are connected to the output of an OR circuit 119 whose first input is connected to the output of the pulse generator 23, and the second input, to the output of the pulse generator 109 in the assembly 2 for determining the parameters of the DHW.

 An OR circuit 120 has been introduced into memory 11 (FIG. 5), the output of which is connected to the reset inputs of flip-flops 71, 72, 73 and 74 and to the reset flip-flop of the flip-flop ~ 750 The first input of the OR circuit 120 is connected to the output of the set: 17 for resetting, and the second input of this OR circuit 120, to the direct output of the flip-flop 110 The inputs of the OR circuit constituting memory reset inputs 11.

In the display unit 12 (FIG. 6), the circuits
AND 76, 77, 78, 79, 80 and 81 each have three inputs, the third inputs of these circuits being connected to the output; reversed from flip-flop 110.

 The control device which has just been described operates as follows.

 The electrocardiosignal (FIG. 9a) coming from the examined subject is taken, for example9 by means of electrodes to be applied to 11 input of assembly 1 of separation of R waves of the DHW, which delivers, for each R wave of the DHW, peaks or "tops" of synchronization S (Figure 9b). The time intervals between the synchronization peaks S correspond to the intervals RR of the cardiosignal: RRi-1, RRi and so on. These synchronization peaks S are injected into the information input of the assembly 2 (FIG. 1) for determining the parameters of the DHW and into # the input of the synchronizing circuit 13.

 Each synchronization peak S (FIG. 9b) triggers the pulse generator 23 (FIG. 3) which supplies pulses of sequence C (FIG. 9c) with the aid of which the time parameters of the DHW are measured.

 During the period of time between the first and the second sequence pulse of each cycle of analysis of the DHW, the synchronizing circuit 13 (FIG. 1) develops instructions T1 T2, T T49 T5 and T6 (FIG. 9d) to control the operation. of the device as a whole.

 It should be noted that the instructions to be applied by the synchronizing circuit 13 to the assemblies of the device devoid of chaste intended for the control of its operation, that is to say theivibrator 108, the pulse generator 109, the flip-flop 110 and 17 fault indicator 111, are indicated on the drawings without parentheses.

 In assembly 2 (figure 33 for determining DHW parameters, the counter 25 counts, during each DHW analysis cycle, the number of pulses of sequence C having passed through the frequency divider 24 to division ratio equal to 5. In this way, at the arrival of a next synchronization peak S, the counter 25 displays a number corresponding to the duration 0.2 RRi. The counter 26, which counts from d 'a value corresponding, for example, to -0.06 seconds, displays a number corresponding to the duration RRi = 0.06 s.

 As for the counter 27, a number corresponding to RRI is obtained there.

 At the end of the previous DHW analysis cycle, the reversible counter 28 receives the value RRi-1 During a following DHW analysis cycle, the pulses of sequence C are successively subtracted from the content of this counter 28 , as a result of which we obtain a number corresponding to RR = (RRi - RRi-1).

 On receipt of the instruction T1 formed by the synchronizing circuit 13, the information is carried from the counter 25 in the register 29, from the counter 26 in the register 30, from the counter 27 in the shift register 32, and from the reversible counter 28, in register 31.

 At the same time, in the shift register 32, the values of the durations of the preceding intervals RRi 1 and RRi 2 continue to be kept.

il se met à l'unité logique. Le résultat de la comparaison est prélevé sur la sortie 3 de la bascule- 42.The T2 instruction triggers the following operations
- In the reversible counter 28 are carried the data coming from the counter 27;
- the comparator 41 performs the comparison of the values 0.2 RRi and tRRi arriving respectively at the bars 39, 40 by the respective line conformers 33, 38 from the registers 29 and 31;
- in flip-flop 42 is recorded the result of the comparison mentioned between 0.2 RRi and u is so that, if
At # iZ / 0.2 Mi, (3) flip-flop 42 is set to logic zero, and if

he goes to logical unity. The result of the comparison is taken from output 3 of the flip-flop-42.

On receipt of the T3 instruction, the following operations take place
- counters 25, 26 and 27 are reset to the initial state (for counters 25 and 27 this will be logical zero, and for counter 26, the state corresponding to the duration 0.06 s) ~
- the comparator 41 compares the values RRi and RRi 1 arriving respectively at the bars 39 and 40 by the line conformers 35 and 36 coming from the outputs of the shift register 32;
- in flip-flop 43 is saved the result of the comparison between RRi and RRi 1 so that, if
RRi # RR 1, (5)
flip-flop 43 is put in the logical unit state, and if
RRi # RRi-1, (6) this flip-flop is set to logical zero. The result of the comparison is taken from the inverted output 4 of flip-flop 43. The instruction T4 triggers the following operations
- The comparator 41 performs the comparison between the values RRi - 0.06 a and '. RRi # 2 which arrive respectively at bars 39 and 40 by the respective conformers 34 and 37 from the outputs of register 30 and shift register 32 ;;
- in flip-flop 44 is saved the result of the comparison between RRi - 0.06 and RRg ~ 2, so that, if
RRi - RRi-2 <O, O6s, (7) flip-flop 44 goes to the logical unit state, and if
RRi - RRi-2 0.06s, (8) it goes to the logic zero state, said comparison result being taken from the inverted output 5 of this flip-flop 44.

 In logic circuit 6 (FIG. 4), the signals driving the inputs 7, 8 and 9 coming from the respective outputs 3, 4 and 5 (FIG. 1) of the assembly 2 for determining the parameters of the DHW, are combined. as follows.

 If the inequalities (4) and (6) are achieved, there is operation of the AND circuit 45 (FIG. 6) which sends the signal from the logic unit to the "+" line. When the inequalities (4) and (5) are realized, it is the AND circuit 46 which functions, by sending the signal from the logic unit to the line "-". Finally, if the inequality (i) is valid, the NON 68 circuit sends a logic unit in line ## '1.

The process of subsequent analysis of the available information, which results in the detection, counting and display of disturbances in the heart rhythm, is illustrated using the table shown in Figure 10. The boxes in this table include various detected variations in heart rate by adopting the following conventional symbols
N = normal rhythm
E = single extrasystole
GE = grouped extrasystole
B = ordinary blocking
D3 = dangerous blockage
Big = bigemina.

In the Table, arrows connect these symbols with the numbers of the flip-flops in memory II which go to the logical unit state upon detection of the corresponding variants of the heart rate
As soon as the apparatus for controlling the cardiac activity is switched on, the reset unit 17 (FIG. 1) delivers, during the time of appearance of at least three successive RR intervals of loECS, a reset signal which is applied to the reset input of the flip-flop 42 (FIG. 3) of the assembly 2 for determining the parameters of the DHW, to the reset inputs of the flip-flops 71, 72, 73, 74 (FIG. 5), and for setting the state of the flip-flop 75 in the memory 11, as well as at the reset inputs of the flip-flops 82, 83, 84, 85 and 86 (FIG. 6) of the display unit 12.

 During the initialization signal formation time, which is 10 seconds for example, in the set 2 (FIG. 1) for determining the parameters of the ETCS, the information accumulates over three successive RR intervals. of the DHW, while in the logic circuit 6 (figure 4) the level of the logic unit is applied to the line "#", and the flip-flop 75 (figure 5) of the memory It is maintained in the state logic unit. There is then operation of the AND circuit 47 (FIG. 4) and of the OR circuit 66, the signal of the unit passing, following the instructions T5 coming from the output 16 (FIG. 1) of the synchronizing circuit 13, through the AND circuit 76 (FIG. 6) of the display unit 12 and the indicator control block 87, which has the effect of displaying, on the indicator 93, the normal heart rate.

 In this case, the presence of a logic unit at the output of the OR circuit 66 corresponds to the seventh combination of signals at the # outputs of the logic circuit 6.

 The existence of a logic unit at the output of flip-flop 75 (figure 5) of the memory It means that in this memory is recorded a code corresponding to the seventh combination of signals at the outputs of the logic circuit 6 (figure 4).

 In addition, on receipt of the instructions T6 formed at the output 15 of the synchronizing circuit 13, the signal from the logic unit coming from the output of the OR circuit 66 puts the flip-flop 75 (FIG. 5) into the logic unit state. memory 11, each time preparing the latter for the next cycle of rhythm analysis.

The condition which has just been described corresponds to box E 2 of the table in FIG. 10. Consequently, after the time for formation of the reset signal, the cardiac activity monitoring device accumulates the information on the report of the durations of the three successive RR intervals of the ECS and will analyze the data thus obtained in relation to the normal rhythm which took place before the analyzed intervals
In the event of a normal heartbeat (figure 11) of the subject examined, the operations described according to the instructions T1,, T2, T3 T4 T5 and T6 are carried out at the appearance of each of the waves R. Given the realization of the inequality (3), the flip-flop 42 (figure 3) is put at the logic zero state, the line "~" of the logic circuit 6 (figure 4) becomes active, and the circuits AND 47, OR 66, AND 76 (figure 6 ) and the indicator control block 87 operate, as a result of which the indicator 93 displays the normal heart rate ~ In memory 11 (FIG. 5), the flip-flop 75 ge sets to the logic unit state.

 In the case where a single extrasystole (figure 11b) appears on the bottom of the normal rhythm, one obtains the realization of the inequalities (4) and (5), a logical unit being then recorded in rockers 42 and 43 (figure 3) of the set 2 for determining the parameters of the DHW.

Under these conditions, it is the line "-" of the logic circuit 6 (FIG. 4) which becomes active. As the level "unit" is maintained at the output of the flip-flop 75 (figure 5), the circuits ET 52 (figure 4) and ET 78 (figure 6) operate, the content of the counter 83 is added by one unit and l indicator 95 displays in decimal code, by means of indicator control block 89, the number of unique extrasystoles. It then occurs the unit, via the OR circuit 69 (Figure 5), the flip-flop 71.

 The presence of a logic unit at the output of the AND circuit 52 (FIG. 4) corresponds to the third combination of signals at the outputs of the logic circuit 6.

The appearance of a logic unit at the output of flip-flop 71 (Figure 5) means that in memory A code is recorded which also corresponds to the third combination of signals at the outputs of logic circuit 6. In the Table of the FIG. 10, such a condition is represented by box El.

 In the event of a compensatory break following the extrasystole (figure 11b), the inequalities (4) and (6) are produced. La.bascule 42 (Figure 3) then goes to the logic unit state, and flip-flop 43, to the logic zero state. Line "+" of logic circuit 6 (figure 4) becomes active, circuit E50 works, which corresponds to the establishment of the second combination of signals at the outputs of logic circuit 6, and a logic unit is recorded in the flip-flop 72 (Figure 5).

The existence of a logic unit at the output of the flip-flop 72 means that in the memory A code corresponding to the second combination of signals at the outputs of the logic circuit 6 is recorded (FIG. 4). Such a condition of the apparatus corresponds to box A3 of the Table (FIG. 10) and constitutes an intermediate state, since, in this case, in order to be able to distinguish a single extrasystole from the case of bigeminia (FIG. 11 f), it is necessary to '' analyze the duration of yet another RR interval. For a normal interval following the compensatory break (figure lob), the inequalities (4), (5), (8) are valid. Then, it is the line "-" of the logic circuit 6 (FIG. 4) which becomes active. A logic unit passes through the circuits ET 51, ET 63,
OR 66, AND 76 (Figure 6) and the indicator control block 87, so that the indicator 93 displays the normal heart rate.

 The flip-flop 75 (FIG. 5) of the memory 11 is set to the unit, which corresponds to the bottom line of the box B1 of the Table of FIG. 10.

In the event of the appearance, on the background of the normal rhythm (figure lita), of a bigemia (figure 11f), the first extrasystolic contraction of the heart is diagnosed as a single extrasystole (see box El of
Table in Figure 10). At the onset of an interval
Longer RR (figure 11f) following the first extrasystole, the device goes to an intermediate state (box
A3 in the Table in Figure 10). Then, at the appearance of another extrasystolic contraction of the heart (figure 11f), the inequalities (4), (5) and (7) are made for the corresponding RR intervals. The level of the logical unit is established on line ! of logic circuit 6 (Figure 4). A unit is added, via the circuits ET 51, ET 62 (figure 4) and
ET 81 (FIG. 6), to the content of counter 86. The indicator control block 92 actuates the indicator 98 to display in decimal code the number of extrasystoles in the event of bigemina. The logic unit signal from the output of the AND circuit 62 (figure 4) of the logic circuit 6 passes through the OR circuit 69 (figure 5) of the memory Il to set the flip-flop 71 (see the upper line of box 31, figure 10).

Under these conditions, the presence of a logic unit at the output of the AND circuit 62 (FIG. 4) corresponds to the eighth combination of signals at the outputs of the logic circuit 6, while the appearance of the logic unit at the output of flip-flop 71 (FIG. 5) means that in the memory A code is also recorded corresponding to said eighth combination of signals at the outputs of the logic circuit 6 This same code in the memory it corresponds to the third combination of signals at the outputs of the logic circuit 6th
The subsequent diagnosis in the event of bigeminism is carried out identically #, which is illustrated by boxes A3 and 31 (upper line) of the table in FIG. 100
In the case of a grouped extrasystole (Figure lIc), the first extrasystole is interpreted as a single extrasystole (box E1 of the Table in Figure 10), while at the appearance of a second extrasystole and subsequent extrasystoles (figure 11c) the inequality (1) is realized, and the line "#" of the logic circuit 6 (FIG. 4) becomes active.

Since, during the previous cycle of heart rate analysis, it was flip-flop 71 (Figure 5) which was set to the unit state, in this case it is the circuits
AND 49 (FIG. 4) and OR 67 of the logic circuit 6 which operate. Via the AND circuit 77 (FIG. 6), the content of counter 82 is added by one unit. The indicator control block 88 ensures the action of the indicator 94 which displays, in decimal code, the number of extrasystoles in the event of a grouped extrasystole. The logic unit signal passes from the output of the OR circuit 67 (FIG. 4) through the OR circuit 69 (FIG. 5) to be recorded in the flip-flop 71. The diagnosis of such a grouped extrasystole is illustrated by box A2 of
Table of figure 10.

 In this case, the presence of a logic unit at the output of the OR circuit 67 (FIG. 4) corresponds to the first combination of signals at the outputs of the logic circuit 6.

The appearance of the logic unit at the output of flip-flop 71 (FIG. 5) testifies to the fact that, in memory 11, a code corresponding to the first combination of signals at the outputs of logic circuit 6 is recorded, which code is analogous to that which corresponds to the eighth and the third combination of signals at the outputs of said logic circuit. The normalization of the rhythm is analyzed in the same way as the normalization after a single extrasystole (see box A3 and the bottom line of box B1 of the Table in Figure 10).

 A grouped extrasystole with successive shortening of the extrasystolic RR intervals is diagnosed in a similar manner. The process of analyzing such a rhythm is illustrated by the boxes El Ai, AD and 31 (bottom line) of the table in FIG. 10.

 The diagnosis of a blockage (omission of a subsequent contraction of the heart) (Figure 11d) is carried out as follows. If a longer RR interval appears on the background of the normal rhythm, the inequalities (4) and (6) are produced.

In logic circuit 6 (FIG. 4), it is then the line "+" which becomes active. Since, during the normal rhythm, it was in flip-flop 75 (FIG. 5) of memory 11 that the logic unit was recorded, there is, in this case, operation of the AND circuits 54 (FIG. 4) , OR 64 and AND 79 (FIG. 6), and addition of a unit to the content of the counter 84. The indicator control block 90 ensures the display, by the indicator 96, of the number of blockings in decimal code. In the memory II (FIG. 5), the signal from the logic unit which passes through the OR circuit 70 is recorded in the flip-flop 73 (see box E3 of the table in FIG. 10). The formation of a logic unit at the output of the OR circuit 64 (FIG. 4) corresponds to the establishment of the fourth combination of signals at the outputs of the logic circuit 6. The memorization of this combination of signals in the memory II (FIG. 5 ) corresponds to the setting of flip-flop 73 to the logic unit state.

 At the appearance of an RR interval of normal duration (figure îîd) - succeeding that of blocking, the inequalities (4) and (5) are accomplished, and this is the line "-" of logic circuit 6 (figure 4) which becomes active. It is then the circuits 57 which functions, and the flip-flop 74 (FIG. 5), which establishes at the outputs of said logic circuit the sixth combination of signals, stores the state of the logic unit, thus indicating that in the memory A corresponding code is recorded to said sixth combination of signals.

 This condition (see box C1 of the Table in Figure 10) constitutes an intermediate state. To be able to diagnose such a rhythm, it is necessary to have information on yet another RR interval.

When another normal RR interval appears (figure 11d), the inequality (3) becomes valid. It is then the line "~" (figure 4) which becomes active and it is the circuits ET 61, OR 66, ET 76 (figure 6) which function. Block 87 activates the indicator 93 which displays the normal heart rate. A logic unit is stored in flip-flop 75 (Figure 5). In the
Table of Figure 10, this condition. Is represented by box D2.

In the event of dangerous blockages (Figure 11e), which are characterized by a successive increase in RR intervals, the first increased interval is considered to reveal a single blockage (see box E3 in the Table in Figure 10). The subsequent extension of an interval
RR following corresponds to the realization of the inequalities (4) and (6), so that the line "+" (figure 4) becomes active.

Since in the previous stage of the analysis it was the flip-flop 73 (figure 5) which was in the unit, it is now the circuits ET 55 (figure 4), OR 65 AND 80 (figure 6) which function , the content of the counter 85 being added with ur.eunity. The indicator 97, brought into play by the control block 91, displays in decimal code the number of dangerous blockages. A logic unit is then recorded, via the OR circuit 70 (FIG. 5), in the flip-flop 73. This diagnosis is illustrated in the Table of FIG. 10 by the box
C3.

 In this case, the presence of a logic unit at the output of the OR circuit 65 (FIG. 4) corresponds to the fifth combination of signals at the outputs of the logic circuit 6.

The state. unit of the flip-flop 73 (FIG. 5) means that in the memory is stored a code corresponding to said fifth combination of signals at the outputs of logic circuit 6, this code being analogous to that corresponding to the fourth combination of signals at outputs of the same logic circuit. The diagnosis of the return to standard is the same as in the single blocking described above.

 In practice, the number of possible combinations of RR interval durations that the cardiac activity monitor is capable of analyzing is quite large. Above, only typical examples have been studied, relating to the best known cases, the functioning of the apparatus for the purpose of diagnosis of any other modifications of the heart rate which can be examined using the Table of Figure 10 and the accompanying drawings, as in the examples described.

 Thus, the proposed apparatus for monitoring cardiac activity makes it possible to carry out continuous and prolonged monitoring of various types of disturbance in the frequency and rhythm of the heart of human beings during the treatment of cardiovascular diseases, in the event of prophylaxis, rehabilitation, tests under physical efforts, as well as in extreme conditions.

 The conclusion on the heart rate is formed on the basis of a relatively small volume of information, concerning the report of the durations of, at most, three successive RR intervals of the ECS, as well as data illustrating the heart rate which were obtained during the previous analysis cycle This reduces the amount of logical operations to be undertaken for the diagnosis and simplifies the production of the device.

Following such a control of the disturbances of the frequency and of the rhythm of the heart, the apparatus provides the number of appearances of each of the above-mentioned disturbances, by displaying them in decimal code.
In FIG. 7, the assembly 18 for preselecting the initial conditions is shown in more detail.
As soon as the apparatus for controlling the cardiac activity is switched on, set 17 (FIG. 2) for resetting the initial state resets the flip-flop 107 (fugre 7), ensuring that a logic zero is obtained. at output 3 (figure 2) of the set 2 for determining the parameters of 1 t DHW. In this case, when the switch 99 (FIG. 7) is set to first or second position, the second input of the EXCLUSIVE OR circuit 100 and the input of the NON circuit 103 are attacked by the level of the logic unit which is shifted in time with respect to the zero signal applied to input 19 (FIG. 2) of the set 18 for preselecting the initial conditions and arriving at the first input of the EXCLUSIVE OR circuit 100 (FIG. 7). Under these conditions, the logic unit present at the output of said circuit OR EXCLUSIVE 100 causes the appearance of a logic zero at the output of the circuit
YES-NO 102. Since the logic zero is also maintained at the outputs of circuit NO 103 and of flip-flop 107, the logic zero signal coming from the circuit output
OR 104 blocks AND circuits 105 and 106 thus supplying outputs 21 and 22 with null signals. Logic circuit 6 (Figure 2) in this case receives information on the absence of appreciable variations in interval durations
RR.

Once the formation of the reset signal has been completed, the inputs 19 and 20 (FIG. 7) receive the signals carrying the information on the ratio of the durations of two neighboring RR intervals. As long as these signals differ from those present at the second circuit inputs
OR EXCLUSIVE 100 and 101, respectively, the initial state of the set 18 of preselection of the initial conditions is maintained. In other words, at outputs 21 and 22 are always maintained the logical zeros,
When the signals at inputs 19 and 20 coincide with those existing at the second inputs of the respective EXCLUSIVE OR circuits 100 and 101-, the outputs of these circuits provide logic zero signals, whereas at the output of the YES-NO circuit 102 appears a logic unit signal which passes through the OR circuit 104 to set the flip-flop 107 to the unit. Consequently9 the logic unit is permanently maintained at the output of the OR circuit 104, this logic unit unlocking the circuits AND 105 and 106 and let the signals from the respective inputs 19 and 20 pass to outputs 21 and 22.

 If the switch 99 is set to its first position, the set 18 for preselecting the initial conditions does not allow the signals coming from the inputs 19, 20 to the respective outputs 21 and 22 to pass until after the simultaneous appearance of the levels of logic unit at the inputs mentioned 19 and 20. The signals existing at the first inputs of the EXCLUSIVE circuits 100 and 101 coincide with those present at their second outputs and imposed by the position of switch 99. The presence of the signals of the logic unit at the inputs 19 and 20 is indicative of a notable increase in the last RR interval appeared in comparison with the previous interval, in other words, the realization of inequalities (4) and (6).

 When the switch 99 is set to its second position, the second input of the EXCLUSIVE OR circuit 100 is attacked by the logic unit signal, and the second input of the EXCLUSIVE OR circuit 101, by that of the logic zero.

So that the set 18 for preselecting the initial conditions can now be switched to the conducting state, it is necessary to obtain the simultaneous presence of the logic unit level at input 19 and that of logic zero at input 20 or in other words, the simultaneous appearance of the second signal at output 3 (FIG. 2) of the assembly 2 for determining the parameters of the DHW, and of the first signal, at output 4 of this assembly. This condition is fulfilled when the inequalities (4> and (5) are valid, that is to say in the case where there is a considerable shortening of the RR interval which appeared last compared to the previous one.

 When the switch 99 (FIG. 7) is in the third position, the level of logic zero is applied to the input of the circuit NON 103. From the output of the latter, the logic unit goes through the OR circuit 104 to set the l 'corresponding state flip-flop 107, thus ensuring the application of the level "unit" authorizing the circuits ET 105 and 106. In this way, the set 18 of preselection of the initial conditions lets pass all the signals immediately after the setting of the switch 99 in third position, from inputs 19, 20 to outputs 21, 22, respectively.

 Thus, by imposing by means of the switch 99 the initial conditions which correspond to the heart rate of the subject examined, we exclude any possibility of proceeding to the diagnosis starting from an RR interval of abnormal duration, which would lead to the formation of erroneous conclusions. Action is taken so that the cardiac activity monitoring device does not intervene, to analyze the rhythm, until after the appearance of a combination of durations of the RR intervals characteristic of the particular subject examined.

 FIG. 8 represents the block diagram of an apparatus for monitoring the cardiac activity of a human being according to the electrocardiosignal, in which an automatic control of the operation of the main assemblies of this apparatus is provided in order to improve the certainty of diagnosis.

 In this case, the instructions sent by the synchronizing circuit 13 to the assemblies of the apparatus are designated in the drawing in parentheses.

 The operating principle of this device is similar to that of the device shown in Figure 1.

 Below, we only highlight the functional features of such a cardiac activity control device with increased diagnostic certainty, without going into detail on the generalities already studied.

The synchronizing circuit 13 (FIG. 11) develops instructions (FIG. 9e) which trigger the following operations
T1- Transfer of information
from counter 25 (Figure 3) to register 29;
from counter 26 to register 30;
from counter 27 to shift register 32 ';
from the reversible counter 28 to the register 31.

T2- Transfer of information:
from counter 27 to register 114 and to the counter
reversible 28;
Comparison between RRi and 0.2 RR in the
comparator 41. i
T3 - Reset counters-25, 26
and 27.

Comparison between RRi 1 and RRi in the compa
rator 41.

T4 - Comparison, in comparator 41, between RRi 2
and RRi-1 - 0.06 s
The execution of operations according to the T1 instructions,
T2, T3 and T4 (figure 9e) has the effect of storing, in flip-flops 42, 43 and 44 (figure 3), data concerning the ratio of the durations of the three consecutive RR intervals.

The instruction T5 activates the pulse generator 109 (FIG. 8) and the univibrator 108. The generator 109 delivers verification pulses Ct (FIG. 9c) with a frequency exceeding N times that of the pulses of sequence C supplied pulse generator part 23 (figure 3). The pulses C and Ct pass through the circuit
OR 119. The reversible counter 28 generates a verification value t RRi by subtracting values of the durations RRi 1 which are recorded therein according to the instruction T2, the verification pulses Ct (FIG. 9c), until the univibrator 108 (figure 8) provides a control pulse St (figure 9b) which stops the pulse generator 109 (figure) 0
The counter 25 (FIG. 3) counts one-fifth of the duration of the RRi verification interval.

The number N is chosen so that the period of time between the instruction T5 (FIG. 9e) and the control role pulse St (FIG. 9b) can contain a number of verification pulses Ct (FIG. 9e) which ensures , by comparing the content of the reversible counter 28 (FIG. 3) with that of the counter 25, the detection of a reference arrhythmia.

In this choice, it is necessary to be based on the minimum value of the duration of the real interval RRi 1 7 recorded in the reversible counter 28, so that the inequality (4) is always achieved during the verification, the operation of the being assumed to be correct.

 After the appearance of the control pulse (FIG. 9b), the synchronizing circuit 13 (FIG. 8) provides verification instructions Tît and T2t (FIG. 9e).

 The Tît instruction is sent to the recording inputs of registers 29 and 31 (FIG. 3) to control the transfer in the first of the information of the counter 25 (verification value 0.2 RRi), and in the second, of the information from the reversible counter 28 (verification value sRRi).

On receipt of the instruction T2t (FIG. 9e), the comparator 41 (FIG. 3), compares the verification values a and and 0.2 RRi, after which the result is entered.
ii saved in flip-flop 110 (figure 8) If it is Inequality (4) which is valid, flip-flop 110 is put in the logic unit state, thus confirming the correct functioning of the device.

In this case the fault indicator 111 does not work, and the display unit 12 (FIG. 6) receives an authorization potential which arrives at the third inputs of the AND circuits 76, 77, 78, 79, 80 and 81
Since at the OR circuit 120 (figure 5) of the memory, the logic zero level is applied from the output. reversed from flip-flop 110, no change occurs in said memory
Upon receipt of the instruction T6 (FIG. 9e), in the display unit 12 (FIG. 8), the detected arrhythmias are counted, their number being displayed on an appropriate indicator. The analysis of the heart rate is carried out in the same way as in the assembly of FIG. 1.

 The instruction T7 (FIG. 9e) ensures the storage in memory II (FIG. 8) of the result of analysis of the rhythm in the preceding cycle, the result which is formed by the logic circuit 6.

The T8 instruction (figure 9e) triggers the following operations
- setting the initial state of the counters 25 (FIG. 3), 26, and 27;
- transfer of information from register 114 to reversible counter 28;
- setting the flip-flop 110 to the unit state (Figure 8).

At this point, the device is ready for the next stage of heart rate analysis. In the reversible counter 28 (FIG. 3) is saved the value of the duration of the previous interval RRi # î
During the sending of the instructions from the synchronizing circuit 13 (FIG. 8), the OR circuits 115, 116, 117 and 118 ensure the electrical decoupling of the signals at the outputs of the plurality of outputs 14 of this synchronizing circuit 13.

 If the inequality (4) is not achieved during the verification on instruction T2t ':, the flip-flop 110 (FIG. 8) is set to logical zero by switching on the fault indicator 111. The passage of the information in the the display unit 12 is inhibited; the memory II (FIG. 5) is attacked, via the OR circuit 120, by the reset signal, so that in this memory the information is recorded corresponding to the normal heart rate at the previous analysis stage.

 As the flip-flop 110 (FIG. 8) memorizes the fault state Until the arrival of the instruction T85 the appearance of the instructions T6 and T7 does not change the state of the display unit 12 and the memory 11. After the breakdown, the subsequent analysis of the heart rate is done relative to the normal condition.

 In this way, after each cycle of analysis of the rhythm of the contractions of the heart, there is # ensured the proper functioning of the assembly 1 for separation of the R waves of the DHW (FIG. 8), of the assembly 2 of determination of the parameters of the DHW and of the synchronizing circuit 13, which results in an improvement in the certainty of the information obtained using the apparatus for monitoring the cardiac activity of a human being at from the DHW.

 Thus, the use of the proposed device makes it possible to obtain continuous and prolonged monitoring of various varieties of disturbances in the frequency and rhythm of cardiac contractions in various conditions of vital activity both of a patient and of an individual. healthy. This gives the possibility of obtaining truthful information on the state of the cardiovascular system of the subject examined in conditions of active life, prophylaxis, treatment, rehabilitation and tests under physical exertion, as well as to judiciously regulate the action of external factors affecting the behavior of the heart.

 The limited volume of information processed by the device during the diagnosis makes it possible to simplify its design and reduce its bulk as well as ensuring its operating reliability. The apparatus according to the invention makes it possible to reduce the probability of developing a false diagnosis and to obtain the most truthful data possible on the patient's heart rate.

 The use of the decimal code indication of the number of arrhythmias detected, as well as displaying only the number of the most common types of disturbances of the heart rhythm, ensure the speed of reading and the convenience of analysis of the information obtained, as well as the compactness of the display system.

 The possibility of controlling the behavior of the heart, offered to any individual under very varied conditions of his vital activity, makes it possible to reduce to a minimum the number of threatening terminal states leading to ventricular Latin fibrt- and heart failure. , hence a decrease in the number of lethality due to diseases of the cardiovascular system.

Claims (5)

REVERDICATIONS  1.- Device for monitoring cardiac activity, comprising a set (i) for separating the waves of an electrocardiosignal, a set (2) for determining the parameters of the electrocardiosignal, which reacts to the signal from the output of said set (i) of separation of the R waves of the DHW and provides at its output (3) a first signal when the absolute value of the difference between the duration of the last interval appeared between the R waves of ltECS and that of the interval between the R waves of the DHW immediately preceding it - is less than a determined percentage of the duration of the last interval appeared between the R waves of the DHW, and a second signal when the absolute value of the difference between the duration of the last interval between Rt waves of ltECS and that of the interval between R waves of ECS which immediately precedes it is equal to said determined percentage of the duration of the last interval appeared between R waves of ECS or greater than this for determined entage of the duration of the last interval appeared between the R waves of the ECS, and at its exit (4), a first signal when the duration of the last interval appeared between the R waves of l9ECS is less than that of the interval between the waves R of the ECS which immediately precedes it, and a second signal when the duration of the last interval appeared between the R waves of 11 ECS is equal to that of the interval between the R waves of the ECS which immediately precedes it, or greater than this duration of the immediately preceding interval between the R waves of the DHW, a logic circuit (6) whose input (7) is connected to the output (3) of said set (2) for determining the parameters of IGUES and whose the input (8) is connected to the output (4) of this, assembly (2) for determining the parameters of the EC5s a memory (ii) whose inputs are connected to the outputs of said logic circuit (6), a display unit (12) which counts and displays the results of the cardiac activity control, the input of this unit (12) being connected to the output of the logic circuit (6), and a synchronizing circuit (13) whose input is connected to the output of said wave separation assembly (2) (R) of the DHW, while its output (14) is connected to the input d e set command (2) for determining the parameters of the DHW, its output (15) at the memory control input (11) 5 and its output (16) 7 at the control input display unit (12), characterized in that said set (2) for determining the parameters of the DHW is provided with an output (5) to which a first signal is formed when the difference between the duration of the last interval appeared between the R1 waves of the ECS and that of the interval between the R waves of the ECS which immediately precedes the interval immediately preceding the said interval which appeared last is less than a preset value, and a second signal when the said difference between the duration of the last interval appearing between the R waves of the DHW and that of the interval between the R waves of the DHW which immediately precedes the interval immediately preceding the interval which appeared last is equal to or greater than said preset value, said circuit logic (6) being furthermore provided with an input ée (9) and a plurality of inputs (10), said input (9) being connected to the output (15) of the assembly (2) for determining the parameters of the DHW and said plurality of inputs (io) being connected to the memory output (11), the set reset inputs (2) for determining the parameters of the DHW, of the memory (ii) and of the display unit ( 12) being connected to a reset unit (17), the logic circuit (6) being designed so that it supplies its outputs a first combination of signals when its input (7) is attacked by the second signal from the output (3) of the set (2) for determining the parameters of the DHW, that its input (8) is attacked by the first signal from the output (4) of said set (2 ) for determining the parameters of the DHW and that the memory contains the recorded code corresponding to the first, the third or the eighth combination of signals at the outputs of this logic circuit (6), that it supplies its outputs with the same first combination of signals when its input (7) is attacked by the first signal from the output (a) of the set (2) for determining the parameters of ETCS and that the memory (it) contains the code corresponding to the first, the third or the eighth combination of signals at the outputs of this logic circuit (6), that it provides at its outputs a second combination of signals when its input (7) is attacked by the second signal from the output (3) for determining the DHW parameters, that its input (8) is attacked by the second signal coming from the output (4) from the set (2) for determining the parameters of the DHW, and that the memory (11) contains a code corresponding to the first, the third or the eighth combination of signals at the outputs of this logic circuit (6), that it provides at its outputs a third combination of signals when its input (7) is attacked by the second signal from from the output (3) of the DHW parameter determination set (2), that its input (8) is attacked by the first signal from the output (4) of the determination set (2) parameters of the DHW and that the memory (it) contains a code corresponding to the seventh combination of signals at the outputs of this logic circuit (6), that it provides at its outputs a fourth combination of signals when its input ( 7) is attacked by the second signal from the output (3) of the assembly (2) for determining the parameters of the DHW, that its input (8) is attacked by the second signal from the output (4 ) of the set (2) for determining the parameters of the DHW and that the memory (11) contains a code corresponding to the sixth combination of signals at the outputs of this logic circuit (6), which it supplies at its outputs the same fourth combination of signals when its input (7) is attacked by the second signal from the output (3) of the assembly (2) for determining the parameters of the DHW, that its input (8) is attacked by the second signal coming from the output (4) of the assembly (2) for determining the parameters of the DHW and that the memory (it) contains a code corresponding to the seventh combination of signals at the outputs of this logic circuit (6), that it provides at its outputs a fifth combination of signals when its input (7) is attacked by the second signal from the output ( 3) of the set (2) for determining the parameters of the E.CS, that its input (8) is attacked by the second signal of the output (4) of the set (2) for determining the parameters of the DHW and that the memory (11) contains a code corresponding to the fourth or the fifth combination of signals at the outputs of this logic circuit (6), that it provides at its outputs the fifth combination of signals when its input ( 7) is attacked by the first signal from the output (3) of the set (2) for determining the para meters from the DHW and that the memory (it) contains a code corresponding to the fourth or the fifth combination of signals at the outputs of logic circuit (6), that it provides at its outputs a sixth combination of signals when its input '(7) is attacked by the second signal from the output (3) of the set (2) for determining the parameters of the DHW, that its input (8) is attacked by the first signal from the output ( 4) of the assembly (2) for determining the parameters of the DHW and that the memory (it) contains a code corresponding to the fourth or the fifth combination of signals at the outputs of this logic circuit (6), provide its outputs with a seventh combination of signals when its input (7) is attacked by the second signal from the output (3) of the set (2) for determining the parameters of the DHW, as its input (8) is attacked by the second signal from the output (4) of the set (2) for determining the parameters of the E CS and that the memory (11) contains a code corresponding to the second combination of signals at the outputs of this logic circuit (6), that it provides at its outputs the seventh combination of signals when its input (7) is attacked by the first signal from the output (3) of the set (2) for determining the DHW parameters and that the memory (11) contains a code corresponding to the second combination of signals at the outputs of this logic circuit (6 ), that it supplies its outputs with the seventh combination of signals when its input (7) is attacked by the second signal from the output (3) of the set (2) for determining the parameters of the DHW, that its input (8) is attacked by the first signal of the output (4) of the assembly (2) determining these parameters of the ECS, that its # input (9) is attacked by the second signal coming from the output (5 ) of 19 sets (2) for determining the DHW parameters and that the memory (11) contains a corresponding code waving at the # second combination of signals at the outputs of this logic circuit (6) that it provides at its outputs the seventh combination of signals when its input (7) is attacked by the first signal from the output (3) of the set (2) for determining the parameters of the ETCS and that the memory (11) contains a code corresponding to the seventh combination of signals at the outputs of this logic circuit (6), which it supplies at its outputs seventh combination of signals when at its input (7) is applied the second signal coming from the output (3) of the assembly (2) for determining the parameters of LPECS, that at its input (8) is applied the first signal from the output (4) of the assembly (2) for determining the DHW parameters and that the memory (11) contains a code corresponding to the sixth combination of signals at the outputs of this logic circuit (6) , that it provides at its outputs the same seventh combination of signals when its input (7) is applied the first signal from the output (3) of the set (2) for determining the parameters of the ETCS and that the memory (11) contains a code corresponding to the sixth combination of signals at the outputs of this logic circuit ( 6), and that it supplies to its outputs an eighth combination of signals when its input (7) is attacked by the second signal of the output (3) of the assembly (2) for determining the parameters of the DHW, that its input (8) is attacked by the first signal of the output (4) of the set (2) for determining the parameters of the DHW, that its input (9) is attacked by the first signal of the output ( 5) of the set (2) for determining the parameters of the DHW and that the memory (ii) contains a code corresponding to the second combination of signals at the outputs of this logic circuit (6), and in that the display unit (12) is designed so that it can display the extrasystoles in the event of a grouped extrasystole, the single extrasystoles s, ordinary blockages, dangerous blockages, the extrasystoles in the event of bigemia, and the normal rhythm, the extrasystole in the event of grouped extrasystole being displayed when at the outputs of the logic circuit (6) is formed the first combination of signals , the unique extrasystole, when at the outputs of the logic circuit (6) is formed the third combination of signals, ordinary blocking, when at the outputs of the logic circuit (6) is formed the fourth combination of signals, the dangerous blocking, when at the outputs of the logic circuit (6) is formed the fifth combination of signals, l7evtrasys- tole in case of bigeminisms when at the outputs of the logic circuit (6) is formed the eighth combination of signals, and the normal rhythm , when the outputs of the logic circuit (6) is formed the seventh combination of signals.  2.- Apparatus according to claim 1, characterized in that it comprises a set (18) of preselection of the initial conditions, capable of being placed in any one of three positions and having its input (19) connected to the output (3) of the assembly (2) for determining the DHW parameters, its input (20), at the output (4) of the assembly (2) for determining the parameters of the DHW, its input reset, at the output of the lens (17) reset, its output (21), at the input (7) of the logic circuit (6), and its output (22) , at the input (8) of the logic circuit (6), so that, when this set (18) of preselection of the initial conditions is put in a first of its three positions it provides at its output (21) an identical signal at the first signal present at the output (3) of the set (2) for determining BECS parameters, and at its output (22), a signal identical to the first signal at the output (4) of the set ( 2) determining the parameters es of the DHW, if the input (19) is applied - the first signal from the output (3) of the set (2) for determining the parameters of the DHW, and at the input ( 20), the first signal from the output (4) of the DHW parameter determination set (2), or if its input (19) is attacked by the first signal from the output (3) of the assembly (2) for determining the parameters of the DHW, and its input (20), by the second signal coming from the output (4) of the assembly (2) for determining the parameters of the DHW, still naked if its input (19) is attacked by the second signal from the output (3) of the set (2) for determining the parameters of the DHW, and its input (20) by the first signal from the output (4) of the set (2) for determining the parameters of the DHW, until the moment when its input (19) is for the first time attacked by the second signal of the output (3) of the set (2) for determining the parameters of the DHW and where its e input (20) is at the same time attacked by the second signal from the output (4) of the set (2) for determining the parameters of the DHW, after which said set (18) for preselecting the initial conditions forms at its outputs (21, 22) signals similar to those present at its respective inputs (19, 20), that when said set (18) of preselection of the initial conditions occupies a second of its three positions, it delivers at its output ( 21) a signal identical to the first signal present at the output (3) of the assembly (2) for determining the parameters of the DHW, and at its output (22), a signal identical to the first signal at the output (4 ) of the set (2) for determining the parameters of the DHW, if its input (19) is attacked by the first signal coming from the output (3) of the set (2) for determining the parameters of the DHW, and its input (20), by the first signal from the output (4) of the set (2) for determining the parameters of the DHW, o u if its input (19) is attacked by the first signal from the output (3) of the set (2) for determining the parameters of the DHW, and its input (20), by the second signal from the output (4) of the set (2) for determining the DHW parameters, or even if its input (19) is attacked by the second signal of the output (3) of the set (2) for determining the parameters of the DHW, and its input (20), by the second signal of the output (4) of the set (2) for determining the parameters of the DHW, until the moment when its input (19) is for the first time attacked by the second signal from the output (3) of the set (2) for determining the parameters of ETCS and its input (20) is simultaneously attacked by the first signal coming from the output (4) of the assembly (2) for determining the parameters of the DHW, after which this assembly (18) for preselecting the initial conditions provides at its outputs (21, 22) signals analogous to this ux present at its respective inputs (19, 20), and when said set (they) of preselection of the initial conditions is put in the third of said three positions, it forms at its outputs (21, 22) signals identical to those present at its respective entries (19, 20).  3.- Apparatus according to one of claims 1 and 2, characterized in that said logic circuit (6) comprises an AND circuit (45) of which a first input is connected to the output (3) of the assembly (2) determining the parameters of the DHW and a second input of which is connected to the output (4) of said assembly (2) determining the parameters of the DHW; an AND circuit (46) whose non-inverting input is connected to the output (3) of the assembly (2) for determining the parameters of - the DHW and whose inverting input is connected to the output (4 ) of said set (2) for determining the parameters of 1BECS a NON circuit (68) whose input is connected to the output (3) of the set (2) for determining the parameters of the DHW; an AND circuit (48), a first input of which is connected to the output of the AND circuit (46); an AND circuit (49), a first input of which is connected to the output of the circuit NO (68); an AND circuit (50), a first input of which is connected to the output of the AND circuit (45); a circuit AND (51), a first input of which is connected to the output of the AND circuit (46); an AND circuit (52), a first input of which is connected to the output of the AND circuit (46); an AND circuit (53), a first input of which is connected to the output of the AND circuit (45); an AND circuit (54), a first input of which is connected to the output of the AND circuit (45) an AND circuit (55), of which a first input is connected to the output of the AND circuit (45); an AND circuit (56), a first input of which is connected to the output of the NON circuit (68); an AND circuit (57), a first input of which is connected to the output of the AND circuit (46) 9 an AND circuit (58) of which a first input is connected to the output of the circuit NO (68) g an AND circuit (59) of which a first input is connected to the output of the AND circuit (45) gun AND circuit (60) of which a first input is connected to the output of the circuit AND (46); an AND circuit (61), a first input of which is connected to the output of the NON circuit (68); an AND circuit (47), a first input of which is connected to the output of the circuit NO (68); an AND circuit (62) whose inverting input is connected to the output (5) of the assembly (2) for determining the parameters of the DHW and whose non-inverting input is connected to the output of the AND circuit (51); a circuit AND (63), a first input of which is connected to the output (5) of the assembly (2) for determining the parameters of the DHW and a second input of which is connected to the output of the AND circuit (51); an OR circuit (67), a first input of which is connected to the output of the AND circuit (48) and a second input of which is connected to the output of the AND circuit (49); an OR circuit (64), a first input of which is connected to the output of the AND circuit (53) and a second input of which is connected to the output of the AND circuit (54); an OR circuit (65), a first input of which is connected to the output of the AND circuit (55) and a second input of which is connected to the output of the AND circuit (56); an OR circuit (66), a first input of which is connected to the output of the circuit AND (58), a second input at the output of the circuit: AND (59), a third input, at the output of the AND circuit (60), a fourth input, at the output of the AND circuit (61), a fifth input, at the output of the AND circuit (47), and a sixth input, at the output of the AND circuit (63); in that the memory (îî) comprises an OR circuit (69) of which a first input is connected to the output of the OR circuit (67), a second input, to the output of the AND circuit (52), and a third input, at the output of the AND circuit (62); an OR circuit (70), a first input of which is connected to the output of the OR circuit (64), and a second input, of the output of the OR circuit (65); a flip-flop (71), the information input of which is connected to the output of the OR circuit (69), the synchronization input, to the output (15) of the synchronizing circuit (13), the reset input to zero, at the output of the reset assembly (17), and the output, at the second inputs of the AND circuits (48, 49, 50); a flip-flop (72) whose information input is connected to the output of said AND circuit (50), the synchronization input, to the output (15) of the synchronizing circuit (13), the reset input at the output of the reset assembly (17), and the output, at the second inputs of the AND circuits (51, 58, 59); a flip-flop (73) whose information input is connected to the circuit output OR (70), the synchronization input, at the output (15) of the synchronizing circuit (13), the reset input, at the output of the reset assembly (17), and the output, at the second inputs of the AND circuits (55, 56, 57); a flip-flop (74) whose information input is connected to the output of the AND circuit (57), the synchronization input, to the output (15) of the synchronizing circuit (13), the reset input , at the output of the reset unit (17), and the output, at the second inputs of the AND products (53, 60, 61); and a flip-flop (75) the information input of which is connected to the output of the OR circuit (66), the synchronization input, to the output (15) of the synchronizing circuit (13), the reset input the state, at the output of the reset assembly (17), and the output, at the second circuit inputs AND (52, 54, 47); and in that the display unit (12) comprises an AND circuit (76), a first input of which is connected to the output of the OR circuit (66), and a second input, of the output (16) of the synchronizing circuit (13) ;; an AND circuit (77), a first input of which is connected to the output of the OR circuit (67) and a second input, of the output (16) of the synchronizing circuit (13), a circuit AND (78), a first input of which is connected to the output of the AND circuit (52), and a second input, of the output (16) of the synchronizing circuit # (13); an AND circuit (79), a first input of which is connected to the output of the circuit OR (64), and a second input, to the output (16) of the synchronizing circuit (13); an AND circuit (80), a first input of which is connected to the output of the OR circuit (65), and a second input, of the output of the synchronizing circuit (13); an AND circuit (81), a first input of which is connected to the output of the AND circuit (62), and a second input, of the output (16) of the synchronizing circuit (13); a counter (82), the counting input of which is connected to the output of the AND circuit (77), and the reset input, of the output of the reset assembly (17); a counter (83), the counting input of which is connected to the output of the AND circuit (88), and the reset input, of the output of the reset assembly (17); a counter (84), the counting input of which is connected to the output of the AND circuit (79), and the reset input, of the output of the reset unit (17); a counter (85), the counting input of which is connected to the output of the AND circuit (80), and the reset input to the output of the reset assembly (17); a counter (86), the counting input of which is connected to the output of the AND circuit (81), and the reset input, of the output of the reset assembly (17); an indicator control block (87) whose input is connected to the output of the AND circuit (75); an indicator control block (88) whose inputs are connected to the outputs of the counter (82); an indicator control block (89) whose inputs are connected to the outputs of the counter (83); an indicator control block (90) whose inputs are connected to the outputs of the counter (84); an indicator control block (91) whose inputs are connected to the outputs of the counter (85); an indicator control block (92) whose inputs are connected to the outputs of the counter (86); an indicator (93) for displaying the normal rhythm, the inputs of which are connected to the outputs of the indicator control block (87); an indicator (94) for displaying the number of extrasystoles in the case of grouped extrasystoles, the inputs of which are connected to the outputs of the indicator control block (88); an indicator (95) for displaying the number of unique extrasystoles, the inputs of which are connected to the outputs of the indicator control block (89); an indicator (96) for displaying the number of blockages, the inputs of which are connected to the outputs of the indicator control block (90); an indicator (97)  for displaying the number of dangerous blockages, the inputs of which are connected to the outputs of the indicator control block (91); and an indicator (98) for displaying the number of extrasystoles in the event of bigeminias, the inputs of which are connected to the outputs of the indicator control block (92).  4. Apparatus according to one of claims 1, 2 and 3 * characterized in that the assembly (18) for preselecting the initial conditions comprises a circuit OR EXCLUSIVE (100) whose first entry constitutes the entry (19) of said set (they) of preselection of the initial conditions; an EXCLUSIVE OR circuit (101), a first input of which constitutes the input (20) of the set (18) for preselecting the initial conditions; an OU-NON circuit (102) of which a first and a second input are respectively connected to the outputs of the circuits EXCLUSIVE OR (1.00, 101) ^ a NO circuit (103) of which the input is combined the second input of the circuit OR EXCLUSIVE (100); an OR circuit (104), a first input of which is connected to the inverted output of said circuit YES-NO (102) and a second input of which is connected to the inverted output of said NO circuit (103); an AND circuit (105), a first input of which is connected to a first input of the EXCLUSIVE OR circuit (100), a second input, of the output of the OR circuit (104), and the output of which constitutes the output (21) of the 'set (18) of preselection of the initial conditions; an AND circuit (106) of which a first input is. connected to a first input of the OR circuit EXCLUSIVE (101), a second input, - at the output of the circuit OR (104), and the output of which constitutes the output (22) of the set (screws) for preselecting the initial conditions; a flip-flop (107), the reset input of which is connected to the output of the OR circuit (104), the reset input, of the output of the reset assembly (17) initial state, and the output, at a third circuit input OR (104); and a switch (99) which, in a first position, ensures the application to the second input of the EXCLUSIVE OR circuit (100) of a signal identical to the second signal present at the output (3) of the assembly (2) for determining the DHW parameters, and at the second input of the EXCLUSIVE OR circuit (101) of a signal identical to the second signal at the output (4) of the assembly (2) for determining the DHW parameters , while, in a second position, said switch (99) ensures the application to the second input of the EXCLUSIVE OR circuit (100) of a signal identical to the second signal present at the output (3) of the assembly ( 2) for determining the parameters of the DHW, and at the second input ## of the EXCLUSIVE OR circuit (101), of a signal identical to the first signal present at the output (4) of the determination assembly (2) parameters of the DHW, and that in a third position said switch (99) ensures the application to the input of the NO circuit (103) of a signal identical to the first signal l at the output (3) of the assembly (2) for determining the DHW parameters.  5. Apparatus according to one of the preceding claims, characterized in that it further comprises a univibrator (108) whose input is connected to the output (113) of the synchronizing circuit (13) and whose output is connected to a second input of said synchronizing circuit (13); a pulse generator (109) whose trigger input is connected to the output (113) of the synchronizing circuit (13), the input dvarr8t, at the output of said univibrator (108), and the output, to the second information input from the set (2) for determining the parameters of the DHW; ; a flip-flop (îîo) whose information input is linked to the output (112) of the assembly (2) for determining the parameters of the DHW, the status and synchronization inputs, to the outputs (14g and 14f ) from the synchronizing circuit (13), the inverted output, at the second zero reset input from the memory (11), and the direct output, at the display authorization authorization input of the display unit (12); and a fault indicator (111) whose input is connected to the reverse output of the scale (110).