FR2582855A1 - DECOUPLING CAPACITOR AND MANUFACTURING METHOD THEREOF - Google Patents

Abstract

A DECOUPLING CAPACITOR AND A METHOD FOR MANUFACTURING THE SAME ARE PROPOSED, THE DECOUPLING CAPACITOR CONSISTING OF A CONDUCTIVE WIRE ARMATURE WHICH CONTAINS THE FOUR CONDUCTIVE WIRES OF THE CONDENSER (TWO OF WHICH ARE ELECTRICALLY INACTIVE) IN THE PLANE. THE USE OF A CONDUCTIVE WIRE REINFORCEMENT AUTOMATICALLY PROVIDES THE DIMENSIONAL TOLERANCES REQUIRED FOR THE MOLDING COVER OF THE DECOUPLING CAPACITOR. IN A FIRST EMBODIMENT, THE DECOUPLING CAPACITOR IS A HERMETICALLY SEALED CAPACITOR ELEMENT, CONSISTING OF A SINGLE-LAYER CERAMIC CAPACITOR 26, ACTIVE CONDUCTIVE WIRES 18, 22 ATTACHED TO THE CAPACITOR 26 AND OF FACTORY PINS 20, 24 ENABLING IT -INSERT IN PRINTED CIRCUIT BOARDS. IN A SECOND EMBODIMENT, THE DECOUPLING CAPACITOR IS A TIGHTLY SEALED CAPACITOR ELEMENT, CONSISTING OF A MULTI-LAYER 90 MONOLITHIC CERAMIC CAPACITOR (TO OBTAIN HIGH CAPACITY VALUES, COMBINED WITH PROPERTIES OTHER THAN DESIRED CHARACTERS FLAT, DEPENDING ON TEMPERATURE), FACTICED CONDUCTIVE WIRES 58, 66 ATTACHED TO CAPACITOR 90 AND FACTIZED PINS 60, 66 ALLOWING SELF-INSERTION IN PRINTED PLATES.

Description

1 The present invention relates to the field of capacitors

  decoupling for integrated circuits. More particularly, this invention relates to decoupling capacitors

  new and improved methods of making the same

  ci in which the capacitors consist of a conductor which contains the four conductors

  of the capacitor (two of which are artificial dummy pins

  trically inactive) in the same plane. This arrangement with

  wires on the conductive armature allows the condensing

  decoupling to a coating by molding, so

  to obtain decoupling capacitors. which are self-

  insertable in printed circuit boards intended to be used in combination with integrated circuits

  online duplicates or other electronic components.

  American patent 4,502,101 has already described a capacitor

  of decoupling for an integrated circuit assembly 6. The conden-

  The decoupling element specific to this prior patent is a micro-

  thin rectangular plate of ceramic material which is

  metallized on opposite sides and which has wires

  ductors starting from the metallized coatings of the oppo-

  s6es of the microchip in two adjacent points of a pair of diagonally opposite angles of the ceramic microchip of rectangular shape.

  folded down and the discovering capacitor assembly

  beach is wrapped in a film of non-conductive material

  tor. In accordance with the principles of this prior patent, the decoupling capacitor is dimensioned so as to be able to be housed in the space between the two strands of conductive wires starting from a conventional integrated circuit

  double online. The 2 conducting wires starting from the condensa-

  decoupling switches are inserted in a circuit board

  these conductors coming from the capacitor being inserted

  res in the printed circuit by holes to which are con

  connected the earthing and current supply 1 conductors. The associated integrated circuit or the other electronic component is then placed over the capacitor

  and is inserted into the plate, so that the wires

  current supply conductors of the integrated circuit or of the other component are arranged in the same holes, right through the printed circuit board in which the

  two capacitor conductor wires have been inserted.

  The diagonally opposite conductors or pins of the conden-

  Decoupling elements specific to US Pat. No. 4,502,101 have given rise to difficulties when it is desirable to automatically insert the decoupling capacitors into the printed circuit board. The classic self-insertion equipment available allows the insertion of integrated circuit elements into printed circuit boards. The

  insertion heads of conventional self-insertion apparatus

  tion grasp the printed circuit by the pins oufilscon-

  conductors of folded terminals of the integrated circuit. Since there are two symmetrical rows of pins on the element to

  integrated circuit, the self-insertion apparatus can

  symmetrically sir the integrated circuit element in a way

  re stable, allowing its insertion. However, when we

  attempts to insert the decoupling capacitor specific to the bre-

  previous American vet n 4.502.101 with the same device-

  self-insertion age, conditions of instability are observed.

  misalignment due to the fact that the conden-

  decoupling separator does not have two rows of symmetrical pins but two pins located in the corners

  diagonally opposite of the rectangular capacitor. The pre-

  If only two pins are used, the conden-

  baler in the insertion head, resulting in

  as a result of a misalignment between the terminals

  of the capacitor in the corresponding holes in the plate

than with printed circuit.

$

  1 As it is extremely desirable to ensure self-insertion

  tion of the decoupling capacitors in the circulating plates

  cooked printed and since it is also desirable to perform

  kill this self-insertion with the same self-apparatus

  insert which is used for internal circuit elements

  If you like, you encounter a major difficulty

  the decoupling capacitor specific to the previous patent,

  not from the point of view of its efficiency and function

  electronic operation, but rather from the point of view of its

  adaptation to assembly techniques in large series.

  There is therefore a need for a condensing arrangement.

  decoupling tor also allowing self-insertion,

  hermetic closure, while offering the possibility of

  put the manufacturing according to assembly processes au-

  tomatoed. U.S. Patent No. 4,475,143 describes a method for

  eliminate the self-insertion difficulty mentioned above

  above, by incorporating dummy or stabilizing pins into a decoupling capacitor assembly. U.S. patents 4,491. 895, 4.494.169, 4.494.170,4.407.012 and 4.532.572 propose other arrangements and other methods for producing the decoupling capacitors with

  dummy pins or molded stabilizing tabs.

  Currently, decoupling capacitors of the type

  crit above and mentioned in the published patents already cited do not easily adapt to a coating process by molding, on the one hand, because they consist of a

  two-layer assembly, i.e. a conductor

  with two conductors and a lower conductor

  eur with two conductor wires, one wire from each conductor

  being an electrically inactive dummy wire. Unhappy-

  the assembly methods commonly used to

  1 these decoupling capacitors do not provide tolerance

  that of parallelism and perpendicularity between the two conductive layers which are required to allow good coating by molding. All specialists in this technique will understand that a molding coating is essential to protect the capacitor against

  influences of the environment and to give it stability

  dimensional unity, mass, weight, etc. required for

  automatic insertion, using insertion devices

DIP for integrated circuits.

  On the other hand, and this is of equal importance, the

  manufacturing processes currently used for con-

  decoupling densifiers of the type mentioned above (i.e.

  that include dummy drivers) is not suitable

  are not particularly good for incorporating mid

  multi-ceramic monolithic ceramic capacitor plates

  three-layer as capacity elements for the device to con-

  decoupling densifier. As a result, this situation

  limits the capacitor element to be a mo-

  nocouche, or that the achievable capacity per unit of

volume remains limited.

  The difficulties mentioned above, and others

  inherent in the prior art, are eliminated or felt

  significantly attenuated thanks to the new decoupling capacitors

  calves and young animals specific to the present invention and to the process

  manufacturing thimble. The decoupling capacitor specific to the present invention consists of a framework of conductive wires which contains the four conductive wires

  densifier (2 of which are dummy electrical conductors

  inactive) in the same plan. The use of an arma-

  ture of conductive wires of this type automatically ensures dimensional tolerances allowing a coating by

  efficient and good quality molding of the entire container

  1 decoupling densifier. The present invention therefore proposes

  arrangements and methods for manufacturing conden-

  Improved decoupling sectors, which are hermetically sealed, self-absorbing and manufactured in a frame of conductive wires with subsequent coating by a molding process. According to a first embodiment of the method specific to the present invention, a lower conductor and four conductive wires are obtained from a continuous strip of electrically conductive material. One of the conductors is attached to the lower conductor and the three

  other conductive wires are isolated therefrom. A micro-

  single layer ceramic wafer and upper conductor

  are then placed on the lower conductor and assem-

  wheat, the ceramic chip thus being included in

  be the upper and lower conductors. One of the three electrically insulated (dummy) conductive wires is then

  electrically connected to the upper conductor in use

  sant, for example, a folded tail, two of the leads

  electrically active sensors (one of which is connected to each

  conductor) and two dummy conductor wires remaining elect

  trically inactive. Preferably, the dummy conductive wires and the active conductive wires are diagonally

  arranged, 'opposite to each other. Finally, the wires con-

  conductors, the ceramic capacitor and the conductors are all coated by a molding process, the conductive wires

  passing through the coating material. The discovery capacitor

  range is then separated from the wire frame. The decoupling capacitor specific to the present invention

  is therefore both hermetically sealed and automatic-

  insertable, which allows its use in devices

  DIP insertion positive for integrated circuits.

  According to a second embodiment of the method of ú 1 the present invention, a pair of conductors, each comprising a conductive wire which is connected thereto, are formed from a continuous strip of electrically conductive material. A pair of dummy conductor wires, each associated with but isolated from a conductor, is

  also formed from this strip. Then a con-

  monolithic multilayer ceramic densifier is disposed between the two conductors (preferably on a mount

  constituted by the conductors). The multi-layer capacitor

  che has a first conductive standing surface and a

  second conductive standing surface, which are connected respec-

  each driver. Then the lead wires, the ceramic chip and the leads are all

  coated by a molding process, the conductive wires pass through

  pouring the coating material. Finally, the decoupling capacitor is separated from the wire frame. The decoupling capacitor specific to the present invention is therefore both hermetically sealed and automatically insertable, so as to allow its use in

  DIP insertion devices for integrated circuit.

  The features and advantages described above and other

  very still, specific to the present invention, will become clear and will be understood by all specialists in

  the technique upon examination of the detailed description below-

  close up and corresponding figures.

  Figures, where similar items received the same

  numbering in the different figures, represent res-

  pectively: Figure 1, a plan view of a conductor armature used to constitute the decoupling capacitor

  and comprising a single-layer ceramic chip,

  in accordance with the present invention;

  1 Figure 2, a plan view of the conductive wire frame

  teuis of figure 1, representing a first phase of the

  formation of the decoupling capacitor specific to the present

  the invention; Figure 3, a side elevational view of the armature of filsconducteus of Figure 2; Figure 4, a plan view of the armature defi] s conductors

  in Figure 1, representing a second phase of training

  tion of the decoupling capacitor specific to this in-

  vention; Figure 5, a side elevational view of the wire frame of Figure 4;

  FIG. 6, a plan view of the wire reinforcement

  Figure 1 representing a third phase of the

  formation of the decoupling capacitor of this in-

  vention; Figure 7, a side elevational view of the conductive armature of Figure 6; Figure 8, a sectional view in elevation of a portion of the wire frame of Figure 6;

  FIG. 9, a sectional view in elevation, along the line

gene 9-9 of Figure 10;

  FIG. 10, a plan view of the decoupling capacitor

  ge of the present invention, comprising a single-layer ceramic chip; Figure 11, a side elevational view of the decoupling capacitor 1 of Figure 10; Figure 12, an end view of the decoupling capacitor of Figure 10;

  Figure 13, a plan view of a wire reinforcement

  head used to make a decoupling capacitor

  comprising a multilayer ceramic chip and con-

  form of the present invention; Figure 14, a side elevational view of the armature of conductive son of Figure 13; FIG. 15, a plan view of the framework of the conductive challenges

  of figure 13 representing a first phase of the realization

  sation of a decoupling capacitor with ceramic chip

  multilayer mique specific to the present invention; FIG. 16, a side elevation view of the conductive armature of FIG. 15;

  FIG. 17, a side elevation view of a condensate

  decoupling unit with multilayer microchip, according to the present invention and before coating; FIG. 18A, an enlarged sectional view in elevation of part of the uncoupling capacitor of FIG. 17; Figure 18B, an enlarged sectional view of an

  part of the decoupling capacitor of figure 17, my-

  trant an alternative arrangement; Figure 19, a sectional elevational view of the decoupling capacitor of Figure 17 after the coating and along the line 19-19 of Figure 20;

  1 Figure 20, a plan view of a discovery capacitor

  multi-layer ceramic chip plate, in accordance with the present invention; and Figure 21, an end view of the decoupling capacitor

  with a multilayer chip in FIG. 20.

  The present invention includes arrangements and methods

  sold to make improved decoupling capacitors

  res, which are hermetically sealed and self-inserting, and which are produced in a frame of fi conductors with, subsequently, a coating by molding process. The figures

  i - 12 relate to a process for producing a condensate

  coated decoupling tor with a mid-capacitor

  single layer ceramic croplaquette. FIGS. 13 - 21 relate to a method for producing a coated decoupling capacitor, starting from an armature of thin conductors and comprising a capacitor with a multilayer ceramic chip. If we first look at Figure 1, we see a

  wire reinforcement used in accordance with this

  the invention and generally designated by 10. The reinforcement of conductive wires 10 is a continuous flat strip of material

  conductor, for example of copper, which is provided with an opening

  tures 12 on its side edges to allow guidance

  and transportation. It will be understood that FIG. 1 does not represent

  you only a small part of a wire frame which

  suitable for making a simple decoupling capacitor

  ple, according to the present invention. We will also understand

  ment that the reinforcement of conductive fibers10 is preferably

  a stamped part of which all the components are rigid.

  The arrangement with armature of desired conductive wires is therefore obtained by eliminating the superfluous material from the strip

  of conductive material, using any conventional technique

  1 sic and appropriate. The reinforcement of conductive wires 10 comprises

  te a lower conductor 14 which generally has a rectangular shape and which is fixed to the rest of the wire frame

  conductor by four support bars 16.

  The conductive wire frame 10 further comprises four conductive wires or pins 18, 20, 22 and 24. At this point in the manufacturing process of the decoupling capacitor, the

  conductive wire 18 is mechanically fixed to the conductor

  lower 14 and therefore becomes an electrically active spindle

  ve, while the other conductors 20, 22 and 24 are i-

  soles of the lower conductor 14 and are therefore dummy or electrically inactive pins. However, as will be explained in more detail below, the conductive wire 22 which is arranged diagonally with respect to the conductive wire

  18 electrically active, will be transformed into a conductive wire

  active, just like the common thread 18. One characteristic

  An important aspect of the present invention is that the four conductive wires or pins, 18, 20, 22 and 24 are

  all in the same plane. Therefore, if the wires conduct-

  at the same time, we can reach the required tolerances which have an influence on the process

molding (injection, transfer).

  If we now examine Figures 2 and 3, we see

  a single-layer capacitive ceramic chip,

  pinned by 26 (Figure 3), which is placed on the lower conductor 14 and which is fixed by an adhesive suitable for

  the mass of the conductor. The ceramic micro-plate capa-

  citive consists of a ceramic capacitor element,

  such as barium titanate, in the form of a plaque

  te, usually rectangular. The ceramic microchip

  that 26 comprises an upper conductor, or conductive cap

  trice 28, which can be fixed by gluing; this last é-

  the element may also consist of a coating of material

  1 conductive wire applied to the ceramic chip 26.

  Ceramic microchip 26 and the upper conductor

  28 will be arranged on the lower conductor 14, so that

  to cover it and parts of the lug of the active spindle 18 and the lug of the dummy spindle 20 (the conductive wire 20 being placed directly opposite

  the active pin 18, as shown in Figure 2). He con-

  has just noted that the two dummy conducting wires 22 and 24 do not come into contact with the chip of

capacitor 26.

  Preferably, the dummy conducting wire 20 (disposed opposite the

  laid active conductive wire 18) will be electrically isolated from the chip by an appropriate coating, such as a welding mask, etc. If we still look at Figures 2 and 3, we see a thread

  dummy conductor 22, which is arranged diagonally in the op-

  laid active conductive wire 18 to ensure contact a-

  with ceramic chip 26 by the upper conductor

  laughing 28. The upper conductor 28 is fixed by gluing to the ceramic chip and is provided with a part 30, in the form of a folded tail (see FIG. 9), which provides the electrical and mechanical connection to the dummy conducting wire 22. This contact between the folded tail portion 30 of the upper conductor 28 and the dummy conductive wire 22 therefore makes the dummy conductive wire 22 electrically

  active, like the electrically active lead 18.

  It will be understood that the attachment of the folded tail 30 to the conductive wire 22 can be carried out by welding, by gluing

  conductive, by riveting, by pinning, by self-welding

  gene, by ultrasonic welding or by any other suitable process. Alternatively, if a folded tail-shaped portion is not provided on the upper conductor 28, wire fixing techniques can be used to transform the dummy conductor wire 22 into an active conductor wire, as necessary. It will be understood that at this point in the manufacturing process of the decoupling capacitor the partially assembled decoupling capacitor, specific to the present

  invention, will include two conductive wires 18 and 22 elect

  trically active and diagonally opposite each other and two dummy wires 20 and 24, electrically

  inactive and diagonally opposite to each other.

  If we now examine Figures 4 and 5, we see

  the next phase of manufacturing the capacitor

  coupling specific to the present invention, o the bars of

  support or fixing 16 are removed. These support bars

  port maintain in position the mass of the conductor 14 during the various previous operations, that is to say the fixing of the upper conductor and the assembly of its

  two components. As these support bars would make sail-

  ties of the assembly after final molding and would hinder the operation

  molding ration, they are removed at this stage of manufacturing. If we now examine Figures 6 to 8, we can see the reinforcement of the conductive wires 10 after coating by molding and deburring. The molding coating, designated by 22, can

  be made using all well-known molding methods

  naked and appropriate. It should be noted that all sur-

  conductive sides of the decoupling capacitor are re-

  covered, with the exception of the two active conducting wires 18 and 22 and the two dummy conducting wires 20 and 24, which

  protrude from the coating. The material used for the

  sealing by molding 32 therefore ensures a hermetic seal

  and protects the various components of the de-capacitor

  coupling 34. After molding, the decoupling capacitor

* Age 1 is preferably subjected to a deburring operation. The ebu-

  rage is an operation that removes excess material from

  valve that can remain attached to the coated element during molding. This excess material generally occurs on the joint surfaces of the mold. Note that the assembly

  of the wire frame is returned for

  Make sure that the pins are correctly oriented before the molding operation. After molding and deburring, the decoupling capacitor according to the present invention and now designated by

  34, is separate from all remaining support structures

  tes, designated in Figures 1 - 4 by 36, 38, 40 and 42. In

  a preferred embodiment, at least a pair of pro-

  tubers 44 and 46 are molded in the decoupling capacitor, so as to be able to separate the decoupling capacitor from a circuit board for cleaning

or for any other reason.

  In Figures 10 - 12, the decoupling capacitor 34 is

  shown after assembly and after the wires have

  tors 18, 20, 22 and 24 have been folded to present their correct and final orientation. As already mentioned, Figure 9 is a sectional elevation view showing

  how the folded tail portion 30 of the conduc-

  upper tor 28 constitutes an electrical and mete

  canique towards the thread 22, so as to transform

  sea the latter from dummy conductive to active conductive.

  In the case of the decoupling capacitor specific to the pre-

  invention, which is achieved by the illustrated method

  in FIGS. 1 - 12, a reinforcement of new conductive wire

  velle 10 is used, in order to ensure the dimensional tolerances

  required to allow efficient coating and -4

  1 correct by molding the whole of the discovering capacitor

  beach. As already mentioned, the conductive armature 10 comprises the four conductive wires of the capacitor which are located in the same plane. The use of a conductive armature of this kind automatically provides the critical dimensional tolerances required to allow the molding of the decoupling capacitor. The ultimately obtained decoupling capacitor device is therefore both hermetically sealed and automatically insertable when machines are used to insert the

DIP integrated circuits.

  If we now examine Figures 13 - 21, we see another embodiment of the present invention, in

  which of the ceramic microchip capacitors

  Multilayer lithic (MLC) are used in place of the flat and thin monolayer capacitive chips used in the embodiment shown in Figures 1-12. In FIG. 13, an armature of conductive fibs which can be

  made in the same way as the wire reinforcement

  teurS10 (already described above) has holes 49, per-

  putting alignment and transport and is designated gener

  ralement par 50. The armature of conductive wires 50 comprises two parts of the mass of the conductor 52 and 54, which are separated from one another by a space or an opening 56 in the shape of an "H". The conductor 52 comprises a spindle or conductive wire 58, electrically active and produced in one piece with this and a spindle or conductive wire 60

  and electrically inactive, which can be isolated from the conduc-

  tor by a space 62. In an analogous manner, the conduc-

  tor 54 comprises a spindle or electric conductor wire 64

  only active, which is made in one piece with it

  and a dummy and electric pin or wire 66

  inactive, which is separated from conductor 54 by the space

  ce 68. As already explained with regard to the armature 1 with conductive wires 10 of FIGS. 1 - 12, the armature with conductive wires 50 comprises different support structures

  which support the conductors 52, 54 and the conductive wires

  58, 60, 64 and 66 of the reinforcement during the different

  your operations. These support structures include the

  supports 70, 72, 74 and 76, which serve to hold in place

  this conductors 52 and 54 on the conductive wire frame

  tores as well as the supports 78, 80, 82 and 84, which serve to support the various conducting wires 58, 60, 64 and 66. If we now examine Figures 15 and 16, we see there

  a mount arranged to receive and maintain a conden-

  Multilayer ceramic microchip indicator. This mon-

  ture consists of two parts 86 and 88, facing inwards, of conductors 52 and 54 which are folded back so as to constitute a support or a mount (see fig.

  re 16). Next, a multilayer ceramic capacitor 90

  is attached to each conductor part 86, 88 (mount).

  The fixing can be carried out with a solder paste or by any other well-known and suitable method. FIG. 18A is an enlarged view showing the method of fixing the capacitor 90 and the conductor part 86. In an alternative embodiment shown in FIG.

  18B, we remove the phase of formation of the frame in -

  fitted with the multilayer capacitor chip

  lugs 92, arranged at 90 or any other suitable angle

  property. It will be understood that any other well-structured

  bare and appropriate can be performed to ensure con-

  connection between the multilayer capacitor and the conductors 52 and 54, such as, for example, butt joints or shanks.

  The multilayer ceramic capacitor 90 is preferably

  this, of a commercially available type and comprising 1 of the successive layers of ceramic 91 and of metallic coating with alternative layers of metal 94 and 96 which are connected to the end electrodes 98 and 100

  respectively and welded to form a single block

  lithic. However, it will be understood that any other suitable arrangement comprising a ceramic chip

  multilayer can be used as part of this

the invention.

  0 Figures 19 - 21 show the discovery capacitor

  multi-layer ceramic chip plate after coating

  bage by molding and after the removal of the various support structures 70 to 84. The final arrangement of the decoupling capacitor, generally designated by 102,

  therefore includes a pair of conductive wires 60 and 66 fac-

  electrically insulated and a pair of conductive wires

  teurs 58 and 63, electrically active, which form only one

  does not work with conductors 52 and 54 respectively.

  On the other hand, the conductors 52 and 54 are electrically

  connected to electrodes 98 and 100 respectively of the con-

  90 multilayer densifier. All of this assembly is then

  wrapped in a suitable material 104, only the two electrically active conducting wires 58 and 64 and the two electrically inactive conducting wires 60 and 66 making

protrusion of this coating.

  As in the realization with single-layer microchip-

  che of Figures 1 - 12, the realization with microchip

  multilayer ceramic in Figures 13 - 21 uses a reinforcement

  ture of filsconducteus 50, in which the four wires

  conductors 58, 60, 64 and 66 are located in the same plane.

  The use of this armature of wire conductors 50 automatically ensures the critical dimensional tolerances

  required for the molding coating of the de-capacitor

  coupling. For many applications, the decoupling capacitor 1 of FIGS. 13 - 21 may be preferred to the decoupling capacitor of FIGS. 1 - 12. This is because

  that the decoupling capacitor 102 uses a capacitor

  90-layer monolithic multi-layer ceramic chip tor with high capacity. A capacitor of this kind allows

  achieve significantly higher capacities than

  achievable using ceramic capacitors

  monolayer planes, while presenting other characteristics

  interesting, such as a flat curve of the varia-

  tion of capacity as a function of temperature.

  The embodiment of the present invention shown

  in Figures 13 - 21 provides certain other characteristics

  ques and advantages that make it preferable to the mode of re-

  alisation with monolayer capacitor of figures 1 - 12.

  For example, and unlike the process for producing the

  decoupling capacitor 34 of Figures 1 to 12, the con-

  decoupling densifier 102 does not require a conduct

  upper toroid or a conductive cap is applied to the condenser chip. It follows that

  it is not necessary to adhere the upper conductor

  eur to the condenser chip if using the

  decoupling capacitor 102. It will therefore be understood that the e-

  eliminating at least these two manufacturing phases makes it possible to reduce the costs and the production times required for manufacturing the decoupling capacitor 102 (by

  comparison with the manufacture of the discovery capacitor

track 34).

Claims (40)

  1. A method of manufacturing a capacitor comprising the steps of removing superfluous material from a strip of electrically conductive material to obtain a first   conductor to which a first conductive wire is connected   active guardian and to get a second, a third and   a fourth isolated conductor wire from said first con-   conductor, said first, second, third and fourth-   me conductors being located in the same plane;   - the placement of a single-layer capacitive element on the -   said first conductor, said capacitive element comprises   both a first and a second conductive surface   tip, said first standing conductive surface 6-   both in electrical contact with said first conduc-   said capacitive element covering essentially   said first conductor and partially covering   said first and second conductive wires; - placing a second conductor on said capacitive element with said second conductive end thereof coming into electrical contact with said second conductor; - the formation of a mechanical and electrical connection between said second conductor and said third conductive wire;   - the assembly of the above elements to obtain a seems; and   - the coating of said assembly, so as to coat her-   m6tique all this assembly, with the exception of one   part of said first, second, third and fourth- me son conductors.   2. Proc6dé according to claim 1, characterized in that   the phase of forming an electrical connection and m6-   1 channel between said second conductor and said third   my main thread comprises the phases of: - transformation of part of said second conductor into a curved tail, and - fixing of said curved tail to said third common thread.   3. Method according to claim 1, characterized in that   the phase of removal of the superfluous material from ladi-   the strip of electrically conductive material further comprises the steps of: - forming a support structure, to support said first conductor in said conductive strip and - removing said support structure before the coating phase.   4. Method according to claim 1, characterized in that   the phase of removal of the superfluous material from ladi-   The strip of electrically conductive material further comprises the phases of:   - formation of support structures to support the-   said first, second, third, fourth son conduc-   contents in said conductive strip, and   - removal of said support structure after pha- of coating.   5. Method according to claim 1, characterized in that   the two active conductive wires are arranged diagonally   relative to each other and that both   dummy conductors are arranged diagonally one by compared to each other.   6. Method according to claim 1, comprising fixing   from the first and second conductor to the first and second D2o   conde conductive tip surfaces of the capacitive element   tif using a conductive adhesive.   7. The method of claim 1, comprising the forma-   tion of alignment holes in said strip of material to the electrically conductive.   8. The method of claim 1, comprising the forma-   tion of at least one protuberance on said assembly coated.   9. Capacitor comprising: - a first electrical conductor (10); - a second electrical conductor (28);   - a first active conducting wire (18) starting from the first   mier conductor (10) in a first location; - a second active conductor wire (22), starting from said second conductor (28) at a second location; - a device for electrically connecting said first or second active conductor wires to said first or second conductor;   - a pair of dummy conducting wires (22, 24), the-   said dummy conductors being electrically isolated from said first and second conductors (10,28) one of said dummy conductors from the first conductor (10) in a third location and the second dummy conductor from the second conductor (28) in a fourth location; - at least part of said first and second active conductive wires (18, 22) and of said pair of dummy conductive wires (22, 24) being located in the same plane;   - a single-layer capacitive element (26), located between the   said first and second conductors (10,28), said é-   capacitive element (26) having first and second electrically conductive tip surfaces;   - said first and second conductors (14, 28) and the-   said capacitive element being assembled with said pre-   mier conductor (10) and said first electrically connected conductive standing surface and said second conductor (28) and said conductive tip surface being electrically connected; and - a coating envelope (32) obtained by molding and covering said conductors (10, 28) and the capacitive element (26) with said active conductive wires   and dummies (18, 20, 22 and 24) coming out of said set   coating cover for said first, second, three fifth and fourth locations.   10. Capacitor according to claim 9, characterized in   what said devices to connect electric   only said first and second conducting wires ac-   tifs to the said first and second conductors comprising nent:   - a curved tail (30) in part of said pre-   mier or second conductor, said curved tail (30)   being electrically connected to said first or second conductive conductive cond.   11. Capacitor according to claim 10, characterized in that said curved tail (30) is fixed to said   first or second active conductor wire by means of the driver.   12. Capacitor according to claim 9, characterized in   that said capacitive element (26) is a material   branched out with a pair of conductive tip surfaces.   13. Capacitor according to claim 9, characterized in   that the two active conductors (18, 22) are available   1 its in two diagonally opposite locations and that the dummy conducting wires (20, 24) are arranged   in two diagonally opposite locations.   14. The capacitor according to claim 9, comprising a   protuberance (46) on said coating envelope (32).   15. Capacitor according to claim 9, characterized in that one of said first or second active conductor wires is fixed in one piece to one of said first or second conductors.   16. A system of decoupling capacitors arranged between a pair of strips used to form a conductor and   the active and dummy conductors of the condensa-   each of said capacitors being in accordance with   any one of claims 9 to 15.   17. A method of manufacturing a capacitor comprising the phases of:   - removal of excess material from a strip of material   electrically conductive line, so as to obtain   a first conductor comprising a first wire   active conductor connected to it and a second con-   conductor comprising a second active conducting wire connected thereto; removing another part of the superfluous material from said strip of electrically conductive material, so as to obtain a first dummy conductive wire   associated with said first conductor but isolated electrically   only of this and a second facet wire   tice, associated with said second conductor but electric   only isolated therefrom, said first and second   active conductors and said first and second con-   , dummy ductors being located in the same plane; 1 - placement of a multilayer capacitive element between said first and second conductors, said element   capacitive comprising a first and a second sur-   conductive end faces, with said first electrically conductive end surface in electrical contact with said first conductor and said second end surface. conductive being in electrical contact with said second conductor;   - assembly of the above elements, so as to obtain   hold a set with said first and second cons   ductors and said multilayer capacitive element assembled wheat to each other; and   - coating of this assembly so as to seal hermé   tically all this assembly, with the exception of a portion of said first and second active conductive wires and said first and second dummy conductive wires.   18. The method of claim 17, comprising the pha-   its of: - formation of a support in said first and second conductors; and - placement of said multilayer capacitive element on said support.   19. The method of claim 18, characterized in that said support comprises a first folded part   in said first conductor and a second part re-   folded in said second conductor, said parts   folded being turned inward and constituting ant a mount.   20. The method of claim 17, comprising the pha-   ses de: - creation of a first lug on the first 4 'surface   1 conductive end of said capacitive element and creates   tion of a second lug on said second conductive tip surface of said capacitive element; and - fixing said first and second lugs to said first and second conductors respectively. 21. Method according to claim 20, characterized in that   that said first and second lugs are folded back to 90.   22. Method according to claim 17, characterized in that the phase of removal of the superfluous material from the   said electrically conductive material includes or   tre the phases of: - formation of a support structure to support   said first and second conductors in said bank   driver; and - removal of said support structure before the coating phase.   23. The method as claimed in claim 17, characterized in that said phase of removing the superfluous material from said electrically conductive material further comprises the phases of: - forming a support structure to support said first and second conductive wires and said   first and second dummy leads in the-   said conductive strip; and - removal of said support structure after the coating phase.   24. The method of claim 17, comprising fixing   tion of said first and second end surfaces con-   conductive of the capacitive element, with an adhesive conductive.   1 25. The method of claim 17, comprising the form   alignment holes in said strip of ma- electrically conductive material.   26. The method of claim 17, characterized in that said active conductive son are located in   two diagonally opposite locations and that the-   said dummy conductors are located in two em- diagonally opposite placements.   27. The method of claim 17, characterized in that said capacitive element is a ceramic material comprising conductive layers interposed with   a pair of conductive tip surfaces.   28. The method of claim 17, comprising the pha-   to provide a protrusion on said coated assembly. 29. Capacitor comprising: - a first electrical conductor (52); - a second electrical conductor (54); - a first active conductive wire (58) starting from said first conductor (52) at a first location;   - a second active conductor (64) starting from said se-   cond conductor (54) at a second location; - A first dummy conducting wire (60) associated with the   said first conductor (52) but electrically iso-   of it in a third location; - a second dummy conductive wire (66) associated with said second conductor (54) but electrically isolated from it in a fourth location; - at least part of said first and second active conductive wires (58, 64) and said first and second dummy conductive wires (60, 66) located in the same plane; 1 - a multilayer capacitive element (90) included between said first and second conductors (52, 54), said capacitive element (90) comprising first and second conductive end surfaces (98, 102) with said first end surface. conductive (98) in electrical contact with said first conductor (52) and said end conductive surface (100) in electrical contact with said second conductor (54) and   - a molded coating envelope (104) coating the   so-called conductors (52, 54) and the capacitive element   (90) with said active conductive wires and   these (58, 60, 64, 66) starting from said coating envelope (104) in a first, second, third and fourth locations.   30. The capacitor according to claim 29, comprising a support device in said first and second   conductors (52, 54), said multi-capacitive element   layer (90) being disposed on said support device   Harbor. 31. Capacitor according to claim 30, characterized in that said support device comprises a   first folded part (86) in said first container   conductor (52) and a second folded part (88) in   said second conductor (54), said folded portions   ées (86, 88) being turned inward and constituting a frame.   32. A capacitor according to claim 29, comprising: - a first lug (92) on said first conductive standing surface (98) of said capacitive element (90);   - a second lug (92) on said second surface of-   conductive end (100) of said capacitive element (90) and 1 said first and second pins being fixed to said   first and second conductors (52, 54) respectively.   33. Capacitor according to claim 32, characterized in that the first and the second lug (92) are folded to 90.   34. Capacitor according to claim 29, characterized in   what said first and second conductive surfaces   these (98, 100) of said capacitive element (90) are fi   fixed respectively to the first and second conductors (52, 54).   35. Capacitor according to claim 34, characterized in   that said connection is achieved by means of a collar- the driver.   36. Capacitor according to claim 32, characterized in   that said connection is achieved by means of a collar- the driver.   37. Capacitor according to claim 24, characterized in that said active conducting wires (58, 64) are located in two diagonally opposite locations and that said dummy conducting wires (62, 66) are   located in two diagonally opposite locations.   38. Capacitor according to claim 29, characterized in that said capacitive element (90) is a material   ceramic with inter-conductive layers   laid (94, 96) with a pair of butt surfaces conductive (98, 100).   39. Capacitor according to claim 29, comprising   a protrusion on said coating envelope. 2582-855   40. System of capacitors arranged between a pair of strips used to form a pair of conductors and   the active and dummy conductors of the condensa-   each of said capacitors being in conformity   to one of claims 29 to 39.