FR2560440A1 - Self-firing thyristor with integrated structure for on/off switching of high currents and its control circuit. - Google Patents

Abstract

THYRISTOR STRUCTURE WITH AMPLIFIER TRIGGER WHICH IS CONTROLLED BY SHORT-CIRCUITS (SWITCHES I AND I) BETWEEN THE TRIGGER AND THE AUXILIARY AND MAIN THYRISTOR CATHODE, RESPECTIVELY, THE LATTER BEING HIGH SENSITIVITY. A CASS IGNITION ASSISTANCE CAPACITOR CONNECTS THE COMMON ANODE TO THE GA TRIGGER CONTACT OF THE AUXILIARY THYRISTOR. THE MAIN THYRISTOR GP TRIGGER CONTACT IS PLACED OUTSIDE OF TRANSMITTER 4, AND AN ISOLATION 7 TRACK, CUTTING THE ENTIRE THICKNESS OF BASE P AND MADE FOLLOWING "PLANAR-SILLON" TECHNOLOGY, IS PRACTICAL AROUND TRANSMITTER 5, TO AVOID A SHORT-CIRCUIT THROUGH THE AUXILIARY THYRISTOR TRANSMITTER JUNCTION, WHICH WILL GENERATE ITS SELF-PRIMING. APPLICATION TO THE SWITCHING OF STRONG CURRENTS (100 A 1000A).

Description

INTEGRATED THYRISTOR STRUCTURE WITH AUTO-IGNITION FOR
SWITCHING ON ALL OR NOTHING OF STRONG CURRENTS, AND
CONTROL CIRCUIT.

The invention relates to the structures of the genus thyristor> self-ignition and, in particular, to those described in the French patent application filed by the DemanX deresse on March 1, 1983 under No. 83 03306 for: "Circuit for controlling a sensitive semiconductor device of the thyristor or triac type, with self-ignition assistance impedance and its application to the realization of a switch arrangement associating a less sensitive thyristor sensitive thyristor ".

In the patent application filed November 25, 1982, under No. 8219728, for: "Intrinsically-ignited thyristor structure and its application to the realization of a bidirectional device", there are described structures of thyristor auto intrinsic ignition, that is to say, starting at the zero voltage under the sole effect of the internal displacement current CdV / dt, this auto-ignition being inhibited by means of a trigger-cathode short-circuit and the advantages have been explained.

These structures with intrinsic self-ignition, as also those which are the subject of the aforementioned patent No. 83 03306, comprise successive semiconductor layers forming a first emitter region (preferably N-type), a first region base, or base of inhibition (preferably P-type), a second base region (main base, preferably of N> type and a second emitter region (preferably P-type), the first region of the emitter being provided with at least one cathode contact, the first base region being connected to at least one inhibit switch contact, the second emitter region being provided with an anode contact, and at least one switch means-arranged to create a short circuit between the inhibition gate and the cathode and thus to inhibit the self-ignition capability of the thyristor, and are characterized in that said base and emitter regions are carried out in such a way as to constitute a thyristor of very great sensi militia.
For this purpose, the thicknesses and the dopings of the first emitter and base regions are chosen so that the intrinsic gain of the first NPN transistor is high at a low level and passivation of the junctions is particularly careful, in accordance with the indications given in FIG. Patent 8219728.

Since it has proved very difficult to industrially achieve "intrinsic" self-ignition structures, it was subsequently planned (patent 83 03306) to initialize the autoignition using a low admittance (resistance of assistance of a few megohms, or capacitor of the order of ten nF).

When these self-ignition structures are assisted by a capacitor, the ignition time is greatly reduced compared to the resistance assistance, so that their NOS transistor control, which has been considered and is very practical in the applications to static relays, becomes difficult because of the load time constant of the MOS gate. On the other hand, when said structures are assisted by a resistor, the assist current does not exceed a few microamperes and is very localized, which limits the possibilities of switching high currents.

If the trigger area is increased, the assist current density becomes low and the assistance is inefficient. It has therefore been necessary to carry out amplifying gate structures, as described in the aforementioned patent 83 03306: the assisted thyristor, of small size and very high sensitivity, then becomes the pilot of a main transistor having itself a very high power. great sensitivity.

In this amplifying trigger structure, however, the high sensitivity is not sufficient to obtain "intrinsic" self-ignition, that is to say without assistance admittance.

A first object of the invention is to provide such an amplifying gate structure of the integrated type, which has particular advantages. It will be noted that such a structure, despite its analogies with the known amplifying trigger thyristor structures, differs radically in its operation, which results from its particularities and its mode of control.

According to a first feature of the invention, the main thyristor of said amplifying gate structure is of the "mesa" type, while the pilot thyristor consists of a small central portion of the "mesa" structure, and delimited according to the technical "planar", with no edge effect, the main base of the pilot thyristor being isolated from that of the main thyristor, unlike the known structure of a thyristor amplifying gate, the amplifying gate structure of the invention being further characterized, in relation to said known structure, in that its control is by gate-cathode short circuits of the pilot thyristor and the main thyristor, that the main thyristor has a clean trigger and a high sensitivity and that the resistance between the inhibition base of the pilot thyristor and that of the main thyristor is very high (more than one megohm).

This last characteristic, advantageously obtained by producing an isolation groove cutting the entire thickness of the base diffusion P, groove itself passivated by thermal oxidation according to the technique called "planar-groove" which allows to maintain low levels of surface recombination and, consequently, high sensitivity of the pilot thyristor, avoids a short circuit across the emitter junction of the pilot thyristor which would hinder its self-priming.

According to another feature of the invention, the pilot and main thyristors are arranged so that the apparent shunt resistance with respect to the corresponding emitter-base junction is very low, for example, for a crystal of 1 cm 2, a resistance of a few hundredths to a few tenths of Ohms at most, thanks to a low layer resistance of the layer P (for example of the order of 10 51 GI) and a strong interdigitation with narrow emitter bands.

 This characteristic, advantageously obtained by conforming the emitter and / or trigger region of the main thyristor to obtain a perimeter to a high surface area ratio, ensures an efficient flow of the flow in blocked mode and, consequently, provides an excellent performance of the blocking, even in case of high dV / dt parasites.

As in the aforementioned patent application 83 03306, a self-ignition assistance impedance, preferably a few megohm resistor, or a capacitor of the order of 10 nF, connects the common anode of the two thyristors. at the pilot trigger contact and priming is achieved by removing a short circuit normally established between the gate and the cathode of the pilot thyristor.

Such a structure, in which the injection surface of the assist current in the pilot thyristor (surface of its transmitter) is reduced, has the advantage that the pilot thyristor, which has a significant gain even at very low level, It is a primer for the very small control current provided by the assist resistor, whereas, thanks to the large surface area of the main thyristor, the structure can drive a high current and, consequently, control a large power.

As indicated above, this structure is radically different from the conventional structure of amplifying gate thyristor, in which, in particular, the ignition of the pilot thyristor is done by applying a control voltage to its trigger. It has, in relation to it, significant advantages and, from binding: greater strength of the component because the ignition is homogeneous over a large part of its surface; a simplification of the control circuit, which simply has to discharge a weak current in a short circuit; better resistance to voltage and dV / dt.

In power applications, on industrial networks of 220 V, the structure must hold inverse voltages of approximately 750 V. It will be noted that the gate-cathode short-circuit transforms the BVCEO voltage withstand into a BVCES voltage withstand. which facilitates obtaining the desired result.

In practice, the thyristor structure having the above features will, however, be unable to operate on network 380 Veff. The change from a supply voltage of 220 Vrms to 380 Vrms would, in particular, lead to a multiplication of the life of the minority carriers in the N base by a factor of 3.6, which would require obtaining a duration of of life more than 90 microseconds instead of 26 microseconds t such a feature is currently unachievable.

According to another feature of the invention, to increase the low-level gain of the NPN transistor which is part of the structure of the pilot thyristor and thus compensate for the gain-loss of the PNP transistor resulting from the increase in the thickness of its base N which is necessary If one wants to hold inverse voltages of 1200 V for example, one carries out its emitter in the form of a double layer structure NN
It has already been proposed to make double-layer emitters in bipolar transistors (see, in particular, the article entitled: "New bipolar device with a low emitter impurity concentration structure"
IEDM Technical Digest 1971, pages 262 to 265). These structures, called "LEC", are intended for high frequency or low power uses and it has not been suggested so far to apply such a method to the realization of thyristor structures and, a fortiori, amplifying gate structures.

Other features, as well as the advantages of the invention, will become clear in the light of the description below.

In the attached drawing
Figure 1 is a block diagram of the structure
a self-igniting thyristor according to
the invention; and
FIG. 2 illustrates a first embodiment of
this structure, which
Figure 3 illustrates a variant.

FIG. 1 shows a thyristor structure comprising a P type 1 inhibition base, a N type main base 2 and a second P type 3 emitter region, which are common to the two thyristors that constitute the structure.

By a "planas" technique, we have formed first N + type emitter regions designated by 4 for the main thyristor, by 5 for the pilot or auxiliary thyristor. Region 5 is located in the center of the silicon wafer and is for example 1 mm in diameter, for a wafer of 1 cm for example. These values are not limiting, and the actual values will depend on the desired power. An anode contact, in Kp, of the cathode contacts of the main thyristor connected to the cathode terminal is represented at 6.
K of the set, in Gp of the trigger contacts of the main thyristor, in Ga of the trigger contacts of the auxiliary thyristor, connected to the anode terminal A of the assembly through a resistance of a few megohms or in the example shown, by a capacitor Cass of the order of 10 nF, in Ka the cathode contact of the auxiliary thyristor, connected to the contacts Gp, and to the terminal K via a switch Il. The common point to Cass and Ga is connected to the terminal K via a switch I2 and switch II in series.

For example, in a first embodiment where the N + emitter is a single layer, the concentrations of impurity atoms per cm3 are
1019 to 1020 A / cm3 for regions 4 and 5,
1017 A / cm3 for region 1,
1014 A / cm3 for region 2,
1017 A / cm3 for region 3.

A groove 7 cutting the entire thickness of the layer 1 and completely surrounding the transmitter 5 is produced according to the technique, known per se, called "planar-groove", which consists of a deep etching of the entire layer 1, followed by additional stripping of the entire surface to suppress the sharp angle created by the deep stripping, and finally, a thermal oxidation for "planar" passivation. The additional stripping will be imperatively carried out by a technique ensuring a very good surface condition (absence of micro crystalline defects and very low trap density), for example by reactive ion etching. This quality of surface preparation of the furrow is indeed necessary if we want to find the characteristics of very low density of recombination centers on the surface that have adopted the technique "planar" to obtain very high sensitivities.

This planar-groove technique makes it possible to maintain low levels of recombination on the surface and, consequently, a high sensitivity of the pilot thyristor. It avoids a short circuit across the emitter junction of the pilot thyristor, which would interfere with its initiation.

Trigger 8 and emitter 7 preferably have a strongly interdigitated structure (or any other equivalent structure), so that, as explained above, the apparent shunt resistance with respect to the emitter-to-emitter junction base of the main thyristor is, for a crystal of 1 cm2, a few hundredths of Ohms for example, thanks to # a layer resistance of the layer P which will be for example of the order of 10 ohms per square (which is note generally 10 Qa). Such a structure will generally not be essential for the emitter junction of the auxiliary thyristor, because of its very small size.

 Preferred embodiments of the structure which has just been described are given below, processes which make it possible in particular to produce a very sensitive main thyristor.

The main structure is of the "mesa" type (i.e. isolated by lapping and etching at the periphery of the wafer, followed by passivation). When a supply voltage of 220 Veff for example is applied to the anode terminal A, the terminal K being at a voltage of zero (when I1 and 12 are open), the same applies to the region 5 , and the low current injected into the gate Ga through the capacitor Cass is sufficient to cause the auxiliary thyristor to ignite shortly after the first zero crossing of the supply voltage, according to the principle of self-ignition assisted operation described in The above-mentioned patent application will note that the emitter junction of the auxiliary thyristor is protected from the short-circuit by the resistance which exists between the corresponding inhibition base portions of the two thyristors.

At this moment, the common base P being at a potential close to that of the anode, and the short circuit between the trigger
Gp and the transmitter 4 being deleted since it is still or ~ green, the main current of the auxiliary thyristor goes into the first emitter junction of the main thyristor, and it starts quickly. The ignition propagates very quickly to the entire surface of the transmitter contact.

This ignition surface can occupy about 80% of the total surface of the wafer.

The amplifying gate structure according to this first embodiment of the invention is capable of switching currents ranging for example from several tens to several hundred amperes.

Note, however, that the PNP transistor gain of such a structure is relatively low, because its base N must have a relatively large thickness to ensure the voltage withstand. As a result, as described above, the structure will no longer be likely to self-ignite for supply voltages of 380 Veff for example, unless one succeeds in giving the transistor NPN a very high gain very low level.

Therefore, according to a second embodiment, illustrated in FIG. 2, the structure is made with double-layer emitters, advantageously according to the following method, given in a nonlimiting manner.
a) one starts from a substrate 2 of weakly doped N silicon
(for example 1014 A / cm3) to hold the high voltage,
b) a P + diffusion is carried out on the rear face, for
constitute the second emitter region 3,
c) a thick P-type epitaxy is made on the face
before, with a concentration of impurities of
1017 A / cm3 for example, followed by an ex-diffusion
intended to reduce the concentration of impurities in
in order to reduce the risk of migrations im
purities in the N layer that will be carried out at the stage
(d). This gives the first base region P of
the structure,
d) the whole surface of the chip is
thin epitaxy (a few microns) of type N with a
concentration of impurities of rape5 A / cm3 for example,
e) Performs all over the face of the trigger contacts
te, thin diffusion or ion implantation of
type P +, at reduced temperature, to receive the
trigger contacts; this superfi base layer
Heavily doped surface makes it possible to obtain
this basic internal very reduced (a few tenths
ohms) which guarantees a very good performance in dV / dt,
f) the groove 7 is made in the manner that has been indi
previously,
g) locally, in transmitter regions 4
and 5, a very thin diffusion (1 micron for example),
type N + (concentration: 1019 A / cm3 for example),
reduced temperature, or ion implantation,
h) a deposit of silicon oxide is carried out.

The contacts are then made in a conventional manner.

The peripheral isolation of the two PN junctions is done in a conventional manner and various known devices are used to increase the voltage withstand. However, it is also possible, independently of the subject of the patent, to carry out PLANAR type isolation.

All the critical surface operations (growth or oxide deposition, passivations, and others) are carried out with great care of cleanliness, as indicated in the aforementioned French patent application No. 82 19728. This double-layered transmitter technology achieves beta gains of the order of 1000 to 1 mA, by reducing the recombination current of the minority carriers through the emitter-base gap charge region.

As a variant, the operation (b) may furthermore comprise a P + diffusion on the front face, and the step (c) will then be suppressed.

In Figure 3, there is illustrated a third embodiment of the structure, consisting of producing doped ultrathin emitters from polysilicon deposited.

More difficult to implement than the method according to the second embodiment described above, this method has, in counterpart, the following advantages:
- It allows the realization of isolation "planai"; thanks to the self-alignment of the diffused zone with respect to the diffusion window,
it makes it possible to reduce the basic parasitic lateral resistance by a buried layer P +,
it reduces the risk of deprodation of the N-emitter layer by P-type ion retro-diffusion during the development of the P + layer.

Although it provides a lower voltage withstand for the emitters, it is sufficient for the proper functioning of the device and is therefore not a disadvantage in the application described here.

The process will be identical to that described above with respect to operations, a - b - c.

We will then perform
d - local implementation, on the front face, of bases
buried type P +,
e - a second thin epitaxy (for example 2 microns) of
N type, with for example an impure concentration
1015 A / cm3, made on the entire front,
f - a thin diffusion P + local, carried out at the level of
local P + sites buried, or a second
ion implantation; this operation is intended to
forming contact regions Gp and Ga,
g - the realization of groove 7 in the manner already described,
h - a thin reoxidation at reduced temperature, with
photogravure to expose the emitter regions,
i - depositing a layer of doped polycrystalline silicon
N +, then photoengraving to delimit the regions
issuers,
j - the very thin diffusion (1 micron) of this layer
polycrystalline N + in the solid state, by treatment
temperature reduced heat (800 to 9000C).

This diffusion gives the N layer of the transmitters to
double layer.

The contact and peripheral isolation of the junctions will be as explained above and all critical surface operations will also be performed with the precautions indicated.

It goes without saying that various other modes of execution can be imagined, without departing from the spirit of the invention. If it is desired to make a thyristor structure capable of delivering at even higher powers, it may be envisaged to use the structure described in the present application as the pilot of a larger thyristor structure which it would trigger. the self-priming.

Claims (7)

Patent claims  1. Integrated thyristor structure comprising a main thyristor of "mesa" type and an auxiliary thyristor consisting of a small central portion of the "mesa ~" structure and delimited according to the "planas" technique with no edge effect, characterized in that the main base of the auxiliary thyristor is isolated from that of the main thyristor, that the main thyristor has a clean trigger (Gp) and a high sensitivity, that the resistance between the base of inhibition of the auxiliary thyristor and that of the main thyristor is at least of the order of one megohm, and the control is effected by short-circuit (12) between trigger <Ga) and cathode (Ka) of the auxiliary thyristor and by short-circuit <Ii) between trigger (Gp) and cathode (Rp) of the main thyristor.  2. Structure according to claim 1, characterized by an isolation groove (7) intersecting the entire thickness of the base diffusion (P), groove itself passivated by thermal oxidation according to the "planar-groove" technique.  3. Structure according to claim 2, characterized in that the gate contact (Gp) of the main thyristor is placed outside the transmitter (4) of said thyristor.  4. Structure according to one of claims 1 to 3, characterized in that the pilot and main thyristors are arranged so that the apparent shunt resistance relative to the corresponding emitter-base junction is very low, preferably of the order of a few hundredths to a few tenths of ohms.  5. Structure according to one of claims 1 to 4, characterized by a high sensitivity auxiliary thyristor and an ignition assistance admittance connecting the anode (A) common to the two thyristors in contact with trigger (Ga) auxiliary thyristor.  6. Structure according to one of claims 1 to 5, characterized in that the first emitter region (5) of the auxiliary thyristor is formed in the form of a double layer structure N + N (Figures 2 or 3) of concentration of dopers.  7. Structure according to claim 6, characterized in that the first emitter region (5) of the auxiliary thyristor is made by doping from a polycrystalline silicon layer deposited (Figure 3) doped N + and very thin diffusion of this layer in the solid state.