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FR2366625A1 - Systeme de traitement de donnees - Google Patents

Systeme de traitement de donnees

Info

Publication number
FR2366625A1
FR2366625A1 FR7726006A FR7726006A FR2366625A1 FR 2366625 A1 FR2366625 A1 FR 2366625A1 FR 7726006 A FR7726006 A FR 7726006A FR 7726006 A FR7726006 A FR 7726006A FR 2366625 A1 FR2366625 A1 FR 2366625A1
Authority
FR
France
Prior art keywords
data processing
processing system
zones
memory
addressable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7726006A
Other languages
English (en)
Other versions
FR2366625B1 (fr
Inventor
David E Finlay
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2366625A1 publication Critical patent/FR2366625A1/fr
Application granted granted Critical
Publication of FR2366625B1 publication Critical patent/FR2366625B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
  • Executing Machine-Instructions (AREA)
  • Control By Computers (AREA)

Abstract

Système de traitement de données à unités de commande programmables avec possibilités de multiprogrammation. Le système comporte une mémoire ayant un domaine d'adresses dans lequel se trouve une mémoire de commande, et une mémoire de lecture-écriture comprenant plusieurs zones et adresses, ainsi que des registres d'entrée/sortie adressables, communs à certaines zones prédéterminées, ce qui les rend adressables dans chacune des zones comme si ils étaient affectés uniquement à ladite zone Ce système est particulièrement adapté pour la commande d'une machine de production de copies.
FR7726006A 1976-10-04 1977-08-19 Systeme de traitement de donnees Granted FR2366625A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/729,451 US4086658A (en) 1976-10-04 1976-10-04 Input/output and diagnostic arrangements for programmable machine controllers having multiprogramming capabilities

Publications (2)

Publication Number Publication Date
FR2366625A1 true FR2366625A1 (fr) 1978-04-28
FR2366625B1 FR2366625B1 (fr) 1980-02-01

Family

ID=24931090

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7726006A Granted FR2366625A1 (fr) 1976-10-04 1977-08-19 Systeme de traitement de donnees

Country Status (8)

Country Link
US (1) US4086658A (fr)
JP (1) JPS6041377B2 (fr)
AU (1) AU513759B2 (fr)
CA (1) CA1099024A (fr)
DE (1) DE2743284C2 (fr)
FR (1) FR2366625A1 (fr)
GB (1) GB1532609A (fr)
IT (1) IT1115396B (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5352029A (en) * 1976-10-22 1978-05-12 Fujitsu Ltd Arithmetic circuit unit
JPS54114687A (en) * 1978-02-27 1979-09-06 Toyoda Mach Works Ltd Sequence controller
US4213190A (en) * 1978-08-28 1980-07-15 International Business Machines Corporation Programmed copier control
US4347566A (en) * 1978-12-11 1982-08-31 Tokyo Shibaura Denki Kabushiki Kaisha Data processor with register file and arithmetic logic circuit on one chip and register means directly connected to the chip
US4317203A (en) * 1979-09-19 1982-02-23 International Business Machines Corporation Collator error recovery
US4317629A (en) * 1980-02-04 1982-03-02 International Business Machines Corporation Job recovery method and system
JPS61208152A (ja) * 1985-03-12 1986-09-16 Matsushita Electronics Corp 集積回路
US4855905A (en) * 1987-04-29 1989-08-08 International Business Machines Corporation Multiprotocol I/O communications controller unit including emulated I/O controllers and tables translation of common commands and device addresses
US5206953A (en) * 1987-11-18 1993-04-27 Ricoh Company, Ltd. Data communication system
JP2674081B2 (ja) * 1988-04-26 1997-11-05 富士ゼロックス株式会社 記録装置の表示装置
JPH04284511A (ja) * 1991-03-14 1992-10-09 Toyota Motor Corp プログラマブルコントローラ異常検出装置
US5182607A (en) * 1991-08-13 1993-01-26 Braswell Charles D High-volume duplicator system and method providing efficient tower and duplicator operation and facilitated unloading in the collated duplex mode
US5287503A (en) * 1991-09-27 1994-02-15 Sun Microsystems, Inc. System having control registers coupled to a bus whereby addresses on the bus select a control register and a function to be performed on the control register

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3970999A (en) * 1975-03-24 1976-07-20 Hewlett-Packard Company Memory expansion apparatus

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3238510A (en) * 1961-12-29 1966-03-01 Ibm Memory organization for data processors
US3601812A (en) * 1969-01-22 1971-08-24 Rca Corp Memory system
US3771131A (en) * 1972-04-17 1973-11-06 Xerox Corp Operating condition monitoring in digital computers
US3748650A (en) * 1972-08-21 1973-07-24 Ibm Input/output hardware trace monitor
DE2364408C3 (de) * 1973-12-22 1979-06-07 Olympia Werke Ag, 2940 Wilhelmshaven Schaltungsanordnung zur Adressierung der Speicherplätze eines aus mehreren Chips bestehenden Speichers
JPS5444537B2 (fr) * 1974-10-04 1979-12-26
JPS5171648A (fr) * 1974-12-18 1976-06-21 Panafacom Ltd
US4020470A (en) * 1975-06-06 1977-04-26 Ibm Corporation Simultaneous addressing of different locations in a storage unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3970999A (en) * 1975-03-24 1976-07-20 Hewlett-Packard Company Memory expansion apparatus

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NV8032/75 *

Also Published As

Publication number Publication date
AU513759B2 (en) 1980-12-18
DE2743284C2 (de) 1987-01-22
JPS5352030A (en) 1978-05-12
JPS6041377B2 (ja) 1985-09-17
US4086658A (en) 1978-04-25
FR2366625B1 (fr) 1980-02-01
AU2887477A (en) 1979-03-22
GB1532609A (en) 1978-11-15
IT1115396B (it) 1986-02-03
CA1099024A (fr) 1981-04-07
DE2743284A1 (de) 1978-04-06

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