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FI946015A7 - Electroless contact nodule formation method - Google Patents

Electroless contact nodule formation method Download PDF

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Publication number
FI946015A7
FI946015A7 FI946015A FI946015A FI946015A7 FI 946015 A7 FI946015 A7 FI 946015A7 FI 946015 A FI946015 A FI 946015A FI 946015 A FI946015 A FI 946015A FI 946015 A7 FI946015 A7 FI 946015A7
Authority
FI
Finland
Prior art keywords
formation method
nodule formation
electroless
contact
electroless contact
Prior art date
Application number
FI946015A
Other languages
Finnish (fi)
Swedish (sv)
Other versions
FI946015L (en
FI946015A0 (en
Inventor
Ahti Aintila
Original Assignee
Picopak Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FI943276A external-priority patent/FI943276A0/en
Application filed by Picopak Oy filed Critical Picopak Oy
Priority to FI946015A priority Critical patent/FI946015L/en
Publication of FI946015A0 publication Critical patent/FI946015A0/en
Priority to PCT/FI1995/000392 priority patent/WO1996002122A1/en
Publication of FI946015A7 publication Critical patent/FI946015A7/en
Publication of FI946015L publication Critical patent/FI946015L/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/05599—Material
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    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2924/30105—Capacitance

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Chemically Coating (AREA)
FI946015A 1994-07-08 1994-12-21 Electroless contact nodule formation method FI946015L (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FI946015A FI946015L (en) 1994-07-08 1994-12-21 Electroless contact nodule formation method
PCT/FI1995/000392 WO1996002122A1 (en) 1994-07-08 1995-07-06 Electroless method of forming contact bumps

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI943276A FI943276A0 (en) 1994-07-08 1994-07-08 Electroless-foil Foer bildning av kontaktstudsar
FI946015A FI946015L (en) 1994-07-08 1994-12-21 Electroless contact nodule formation method

Publications (3)

Publication Number Publication Date
FI946015A0 FI946015A0 (en) 1994-12-21
FI946015A7 true FI946015A7 (en) 1996-01-09
FI946015L FI946015L (en) 1996-01-09

Family

ID=26159774

Family Applications (1)

Application Number Title Priority Date Filing Date
FI946015A FI946015L (en) 1994-07-08 1994-12-21 Electroless contact nodule formation method

Country Status (2)

Country Link
FI (1) FI946015L (en)
WO (1) WO1996002122A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI954922L (en) * 1995-10-16 1997-04-17 Picopak Oy Manufacturing method and contact bump structure for dense surface connections of semiconductor chips
DE19616373A1 (en) * 1996-04-24 1997-08-14 Fraunhofer Ges Forschung Forming galvanically deposited contact bumps for integrated circuits
US5989993A (en) * 1996-02-09 1999-11-23 Elke Zakel Method for galvanic forming of bonding pads
DE102004019445A1 (en) * 2004-04-19 2005-11-03 Siemens Ag With planar connection technology on a particular electrically conductive substrate constructed circuit
DE102004047730B4 (en) * 2004-09-30 2017-06-22 Advanced Micro Devices, Inc. A method for thinning semiconductor substrates for the production of thin semiconductor wafers

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4182781A (en) * 1977-09-21 1980-01-08 Texas Instruments Incorporated Low cost method for forming elevated metal bumps on integrated circuit bodies employing an aluminum/palladium metallization base for electroless plating
US5226232A (en) * 1990-05-18 1993-07-13 Hewlett-Packard Company Method for forming a conductive pattern on an integrated circuit

Also Published As

Publication number Publication date
FI946015L (en) 1996-01-09
FI946015A0 (en) 1994-12-21
WO1996002122A1 (en) 1996-01-25

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