FI3457574T3 - Tietojenkäsittelymenetelmä ja -laite jäsenneltyä ldpc-koodia varten - Google Patents
Tietojenkäsittelymenetelmä ja -laite jäsenneltyä ldpc-koodia varten Download PDFInfo
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- FI3457574T3 FI3457574T3 FIEP16901513.8T FI16901513T FI3457574T3 FI 3457574 T3 FI3457574 T3 FI 3457574T3 FI 16901513 T FI16901513 T FI 16901513T FI 3457574 T3 FI3457574 T3 FI 3457574T3
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/033—Theoretical methods to calculate these checking codes
- H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/114—Shuffled, staggered, layered or turbo decoding schedules
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
- H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
- H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
- H03M13/1188—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal wherein in the part with the double-diagonal at least one column has an odd column weight equal or greater than three
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/615—Use of computational or mathematical techniques
- H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/635—Error control coding in combination with rate matching
- H03M13/6356—Error control coding in combination with rate matching by repetition or insertion of dummy data, i.e. rate reduction
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
- H03M13/6516—Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
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- General Physics & Mathematics (AREA)
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- Mathematical Analysis (AREA)
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Claims (7)
1. Digitaalinen tiedonsiirtomenetelmä, jossa: hankitaan (S202) koodilohkokoko jäsenneltyä matalan tiheyden pari- — teettitarkastus- (eng. Low Density Parity Check), LDPC, -koodausta varten; määritetään (S204) koodinlaajennuskerroin z koodinlaajennuskertoi- mien joukosta koodilohkon koon ja perustarkistusmatriisiin liittyvän parametrin kb perusteella, missä koodinlaajennuskertoimien joukko käsittää joukon luon- nollisia lukuja; ja koodataan tai dekoodataan (S206) datasekvenssi perustarkistusmatrii- sin ja koodinlaajennuskertoimen z perusteella, missä parametri kb ja koodinlaajennuskerroin z ovat kokonaislukuja, jotka ovat suurempia kuin 1, missä kukin arvo koodinlaajennuskertoimien joukossa on yhtä suuri — kuin luvun 2 positiivisen kokonaislukupotenssin ja alkuluvun tulo; ja missä alkuluku on sama kuin jokin seuraavista: 3, 5, 7, 11 tai 13.
2. Patenttivaatimuksen 1 mukainen menetelmä, jossa perustarkistus- matriisissa on mb riviä ja nb saraketta, ja jossa kb on yhtä suuri kuin nb miinus mb.
3. Patenttivaatimuksen 1 mukainen menetelmä, jossa koodinlaajennus- kerroin z on jokin seuraavista: 6, 12, 24, 48, 96, 192 tai 384; 10, 20, 40, 80, 160 tai 320; tai 14, 28, 56, 112 tai 224.
4. Digitaalinen tiedonsiirtolaitteisto, joka käsittää: prosessorin (102) ja muistin (104), joka käsittää prosessorilla suoritettavissa olevaa koodia, joka prosessorilla suoritettavissa oleva koodi prosessorilla suoritettaessa kon- figuroi prosessorin: hankkimaan (S202) koodilohkon koon jäsenneltyä matalan tiheyden pariteettitarkastus- (eng. Low Density Parity Check), LDPC, -koodausta var- — ten;
määrittämään (S204) koodinlaajennuskertoimen z koodinlaajennus- kertoimien joukosta koodilohkon koon ja perustarkistusmatriisiin liittyvän para- metrin kb perusteella, missä koodinlaajennuskertoimien joukko käsittää joukon luonnollisia lukuja; ja koodaamaan tai dekoodaamaan (S206) datasekvenssin perustarkistus- matriisin ja koodinlaajennuskertoimen z perusteella, missä parametri kb ja koodinlaajennuskerroin z ovat kokonaislukuja, jotka ovat suurempia kuin 1, missä kukin arvo koodinlaajennuskertoimien joukossa on yhtä suuri — kuin luvun 2 positiivisen kokonaislukupotenssin ja alkuluvun tulo; ja missä alkuluku on sama kuin jokin seuraavista: 3, 5, 7, 11 tai 13.
5. Patenttivaatimuksen 4 mukainen laitteisto, jossa perustarkistusmatrii- sissa on mb riviä ja nb saraketta, ja jossa kb on yhtä suuri kuin nb miinus mb.
6. Patenttivaatimuksen 6 mukainen laitteisto, jossa koodinlaajennus- kerroin z on jokin seuraavista: 6, 12, 24, 48, 96, 192 tai 384; 10, 20, 40, 80, 160 tai 320; tai 14, 28, 56, 112 tai 224.
7. Pysyvä tallennusväline, johon on tallennettu koodia, joka koodi proses- sorilla suoritettaessa saa prosessorin toteuttamaan jonkin patenttivaatimuk- sen 1-3 mukaisen menetelmän.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610322409 | 2016-05-13 | ||
| CN201610879343.9A CN107370489B (zh) | 2016-05-13 | 2016-09-30 | 结构化ldpc码的数据处理方法及装置 |
| PCT/CN2016/104744 WO2017193558A1 (zh) | 2016-05-13 | 2016-11-04 | 结构化ldpc码的数据处理方法及装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| FI3457574T3 true FI3457574T3 (fi) | 2025-06-27 |
Family
ID=60266148
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FIEP16901513.8T FI3457574T3 (fi) | 2016-05-13 | 2016-11-04 | Tietojenkäsittelymenetelmä ja -laite jäsenneltyä ldpc-koodia varten |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US11683051B2 (fi) |
| EP (1) | EP4576584A3 (fi) |
| ES (1) | ES3024210T3 (fi) |
| FI (1) | FI3457574T3 (fi) |
| WO (1) | WO2017193558A1 (fi) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117060932A (zh) * | 2023-08-10 | 2023-11-14 | 上海思朗科技有限公司 | 基于基本图的并行ldpc译码方法、装置、设备及介质 |
| CN119154892B (zh) * | 2024-11-14 | 2025-02-25 | 深圳鹏龙通科技有限公司 | 低密度奇偶校验码的译码方法、装置、电子设备及存储介质 |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7996746B2 (en) * | 2004-10-12 | 2011-08-09 | Nortel Networks Limited | Structured low-density parity-check (LDPC) code |
| CN100502245C (zh) * | 2005-10-21 | 2009-06-17 | 中兴通讯股份有限公司 | 支持任何码率/码长的低密度奇偶校验码编码装置和方法 |
| CN101217337B (zh) | 2007-01-01 | 2013-01-23 | 中兴通讯股份有限公司 | 一种支持递增冗余混合自动重传的低密度奇偶校验码编码装置和方法 |
| KR101364160B1 (ko) | 2007-01-24 | 2014-02-17 | 퀄컴 인코포레이티드 | 가변 크기들의 패킷들의 ldpc 인코딩 및 디코딩 |
| KR101103605B1 (ko) | 2007-04-30 | 2012-01-09 | 노키아 지멘스 네트웍스 오와이 | 자도프-추, 수정된 자도프-추, 및 블록-방식 확산 시퀀스들에 대한 조정된 순환 시프트 및 시퀀스 호핑 |
| CN101141133B (zh) * | 2007-10-23 | 2011-09-14 | 北京邮电大学 | 一种结构化低密度校验码的编码方法 |
| CN101459430B (zh) | 2007-12-14 | 2010-12-08 | 中兴通讯股份有限公司 | 低密度生成矩阵码的编码方法及装置 |
| PL3462638T3 (pl) * | 2008-11-18 | 2020-07-27 | Viasat Inc. | Skuteczna sygnalizacja sterowania przez współdzielone kanały komunikacyjne o rozszerzonym zakresie dynamiki |
| CN101834613B (zh) | 2009-03-09 | 2012-11-21 | 电信科学技术研究院 | 一种ldpc码的编码方法及编码器 |
| US8559539B2 (en) | 2009-06-26 | 2013-10-15 | Nokia Corporation | Method, apparatus and computer readable storage medium |
| CN102412842B (zh) * | 2010-09-25 | 2016-06-15 | 中兴通讯股份有限公司 | 一种低密度奇偶校验码的编码方法及装置 |
| CN102457286B (zh) | 2010-10-21 | 2013-08-28 | 航天信息股份有限公司 | 准循环ldpc码编码方法、装置及校验矩阵生成方法 |
| CN104868925B (zh) * | 2014-02-21 | 2019-01-22 | 中兴通讯股份有限公司 | 结构化ldpc码的编码方法、译码方法、编码装置和译码装置 |
-
2016
- 2016-11-04 ES ES16901513T patent/ES3024210T3/es active Active
- 2016-11-04 FI FIEP16901513.8T patent/FI3457574T3/fi active
- 2016-11-04 WO PCT/CN2016/104744 patent/WO2017193558A1/zh not_active Ceased
- 2016-11-04 EP EP25165678.1A patent/EP4576584A3/en active Pending
-
2021
- 2021-10-04 US US17/493,612 patent/US11683051B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US11683051B2 (en) | 2023-06-20 |
| US20220038115A1 (en) | 2022-02-03 |
| EP4576584A3 (en) | 2025-09-17 |
| EP4576584A2 (en) | 2025-06-25 |
| WO2017193558A1 (zh) | 2017-11-16 |
| ES3024210T3 (en) | 2025-06-04 |
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