FI20245066A1

FI20245066A1 - Indium attached bumps

Info

Publication number: FI20245066A1
Application number: FI20245066A
Authority: FI
Inventors: Joel Hätinen; Tuure Rantanen; Janne Lehtinen; Mika Prunnila
Original assignee: Teknologian Tutkimuskeskus Vtt Oy
Priority date: 2024-01-23
Filing date: 2024-01-23
Publication date: 2025-07-24
Also published as: WO2025158106A1

Abstract

According to an example aspect of the present invention, there is provided a bonding structure, which comprises at least a first substrate (110) and a second substrate (120). The bonding structure features interconnects between the at least two substrates (110, 120). The interconnects comprise at least one metal bump (112) on a first face of the first substrate (110), at least one metal bump (122) on a first face of the second substrate (120); and a layer of indium (133) interposed between said metal bumps (112, 122). A thickness of the layer of indium (133) is at most 500 nanometres, nm.

Description

INDIUM ATTACHED BUMPS

FIELD

[0001] The present disclosure relates to the field of electronics assembly.

BACKGROUND

[0002] A flip chip arrangement, also known as a controlled collapse chip connection, can be used for upscaling electronic semiconductor microchip designs through three- dimensional integration. Such approaches are useful, for example, in upscaling guantum computing solutions. Flip chips are produced by layering and connecting two or more substrates via interconnects known as bumps constructed, for example, from a hard metal such as niobium, gold, copper or aluminium. Such bumps may be connected to one another using appropriate bonding schemes to provide suitable electrical and/or thermal conductivity between the layered integrated circuits in the flip chip design.

SUMMARY

[0003] Summary to be finalized once claims are final.

[0004] According to some aspects, there is provided the subject-matter of the < independent claims. Some embodiments are defined in the dependent claims.

N

O

N 20 — [0005] According to a first aspect of the present disclosure, there is provided a bonding structure, which comprises at least a first substrate and a second substrate. The bonding ™

N structure features interconnects between the at least two substrates. The interconnects

I

= comprise at least one metal bump on a first face of the first substrate, at least one metal bump © on a first face of the second substrate, and a layer of indium interposed between said metal

O

0 25 bumps. A thickness of the layer of indium is at most 500 nanometres, nm.

S

[0006] According to a second aspect of the present disclosure, there is provided a method for manufacturing bonding structures. The method involves: — obtaining at least a first substrate and a second substrate,

— obtaining at least one metal bump on a first face of the first substrate, — obtaining at least one metal bump on a first face of the second substrate, — compressing together the metal bumps on the first face of the first substrate with the metal bumps on the first face of the second substrate at a temperature of between 10-80 °C such that a layer of indium is compressed between respective ones of the metal bumps, thereby forming the bonding structure with the layer of indium bonded between the respective ones of the metal bumps, wherein the layer of indium is at most 500 nm in thickness.

[0007] Some embodiments may include one or more than features from the following itemized list: — the thickness of the indium layer is at most 400 nm; — the thickness of the indium layer is at most 200 nm; — dimensions of the at least one metal bump are between 80 um and 125 um parallel to the first face of the substrate; — dimensions of the at least one metal bump are between 60 - 100 um perpendicular to the first face of the substrate; — at least one of the substrates comprises a control chip; — at least one of the substrates comprises a device chip; — the metal bumps comprise at least one of gold Au, niobium Nb, copper Cu and aluminium Al at a concentration of at least 20% weight; — the arrangement comprises more than two substrates; — the second substrate has a further layer of indium of at most 500 nm thickness attached + to at least one metal bump on a second face of the second substrate;

S — athird substrate has attached on a first face thereof at least one second metal bump, 5 25 — the at least one second metal bump is further attached to the further layer of indium; & — the layer of indium extends solely on a single face of the metal bumps;

E — the layer of indium comprises indium which comprises less than 1% weight of © ferromagnetic material;

D — a layer of indium comprises indium which comprises less than 1% weight of metallic

O 30 material: — the bonding structure is a flip chip interconnect arrangement; — the thickness of the layer of indium layer after compression is at most 200 nm;

— the compressing is applied for a duration of between 30 seconds and 30 minutes; — the temperature is between 20 — 50 °C; — the layer of indium comprises indium which comprises less than 5% weight of ferromagnetic material, — alayer of indium comprises indium which comprises less than 5% weight of metallic material.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIGURE 1A illustrates an example structure of indium attached metal bump interconnects in a flip chip arrangement in accordance with at least some embodiments of the present invention;

[0009] FIGURE 1B illustrates a separated example structure of two substrates with indium attached metal bump interconnects thereon;

[0010] FIGURE 1C illustrates a perspective representation of an example structure of —two substrates with indium attached metal bump interconnects thereon in a flip chip arrangement in accordance with at least some embodiments of the present invention;

[0011] FIGURE 2A illustrates indium attached bumps in a flip chip arrangement with an intermediate substrate in accordance with at least some embodiments of the present invention;

[0012] FIGURE 2B illustrates indium attached bumps in a flip chip arrangement with

N two intermediate substrates in accordance with at least some embodiments of the present

N invention; > = [0013] FIGURE 3 is a flow graph of a method in accordance with at least some

E embodiments of the present invention. a 3 25

O

LO

+

N EMBODIMENTS

N

[0014] In the present disclosure, the term “chip” may comprise, for example, a microcontroller or other device produced from a semiconductor material, typically silicon.

[0015] In the present disclosure a bonding structure, such as, for example, a flip chip interconnect arrangement, and a bonding method are introduced, wherein indium attached metal bumps are interposed between two substrates. Superconductivity of the interconnect structure is obtained by selecting the thickness of the applied layer of indium to be sufficiently thin, which alters a critical temperature of the interconnects through the proximity effect. An interconnect is herein used to refer to a layer of indium on a metal, such as gold, niobium, copper or aluminium. The flip chip interconnect arrangement comprises at least two substrates, and an at most S00 nanometre, nm, thick layer of indium attached as an interconnect material between metal bumps attached on faces of the at least two substrates. In other words, the flip chip interconnect arrangement comprises at least one metal bump on a first face of a first substrate, at least one metal bump on a first face of a second substrate and interposed between the at least one metal bump on the first face of the first substrate and the at least one metal bump on the first face of the second substrate, a layer of indium, wherein the thickness of the layer of indium is at most 500 nm.

Superconductivity of the interconnect may also be suppressed by using e.g. copper or gold as the material for the metal.

[0016] FIGURE 1A illustrates an example structure of a flip chip arrangement with indium attached metal bump interconnects therein in accordance with at least some embodiments of the present invention. In the embodiments of FIGURE 1A, the flip chip arrangement comprises a first substrate 110 and a second substrate 120. Interposed between the two substrates 110, 120 are interconnects comprising metal bumps 112, 122 and a layer of indium 133. In some embodiments, the layer of indium 133 is at most 500 nm thick. In some embodiments, the layer of indium 133 is at most 400 nm thick. In some embodiments,

N the layer of indium 133 is at most 200 nm thick, or at most 100 nm thick. As illustrated, s 25 — some bumps attached on substrate 120 may be attached, via indium layer 133, to more than = one bump attached on substrate 110.

N

E [0017] Currently especially for guantum computing, superconductivity may be © needed, which is a material-specific property with behaviour governed by the overall

D temperature of the system. Below a critical temperature T. of the material, typically in

N 30 temperatures of only few kelvins, superconductivity is achieved. In other words, a = superconductor exhibits superconductivity when its temperature is below the critical temperature T.. Superconductivity is also needed, for example, for the appropriate function of superconducting tunnel junctions, such as Josephson junctions used in transmon gubits.

However, the superconductivity of a system may be effectively governed by the element of the system with the lowest critical temperature Tc. Materials and elements with suitable processing and fabrication characteristics may be used to combine superconductive and/or ordinary metal bump interconnects between two or more substrates and as such, the 5 — superconductivity, or lack thereof, may depend to an extent on the applied bonding material between the bumps.

[0018] Thermocompression bonding, TCB, may be utilized to bond two or more substrates using bumps for flip chip systems using a combination of compressive stress and an elevated or otherwise appropriate temperature. For many materials, the temperature — needed for bonding using thermal compression is above 150 °C, a temperature range where parts of flip chip systems may be irreversibly changed, damaged or destroyed. For example, a copper-copper connection with thermocompression bonding typically requires temperatures above 300 °C. However, indium, In, can be applied using TCB at temperatures greatly below its melting point, for example at room temperature, 10 - 80 °C, or even up to — the melting point of Indium at 150 °C. Indium can be used as a part of an interconnect medium between two substrates but its critical temperature Tc of approximately 3.4 K may dictate superconductivity behaviour of the entire flip chip interconnect. Thus, superconductivity at higher temperatures is not achievable with interconnects utilizing substantially thick layers of indium. For example, the performance of superconducting — electron coolers using aluminium may be degraded due to the superconducting gap of indium, and sensor arrays operating at, for example, 4 K require critical temperatures significantly higher temperatures for wiring layers, where a niobium Nb — niobium Nb interface is a typical solution. Further, the performance of superconducting electron coolers

N is strongly dependent on efficient guasiparticle evacuation for which the appropriate critical s 25 temperature is useful. By superconducting gap it is herein meant the density of states region = where no electron (or electron-hole) states exist in the superconductor. For efficient

N quasiparticle transport, the gap of the interconnect has to be smaller than the gap of the & material where the quasiparticles are conducted away from.

O

2 [0019] In a phenomenon known as the proximity effect, or the Holm-Meissner effect,

N 30 the critical temperature Tc of a material is affected by its adjacent non-superconducting, = insulating or superconducting material. For example, the critical temperature of a superconductive material may be suppressed by an addition of a non-superconducting element in its proximity. As such, this effect can be applied to either improve or degrade the superconductive characteristics of a material. In the present disclosure, indium in a thin layer is used to attach metal bumps to each other, wherein the superconductivity and the critical temperature of such metal bumps greatly dictate the superconductivity of the system.

[0020] In some embodiments of the flip chip interconnect arrangement, dimensions of the metal bumps are between 10 micrometres, um, and 200 um, such as, for example, between 80 um and 125 um parallel to a face of a substrate, that is in thickness, and 1 — 100 um, such as 60-100 um, perpendicular to the face of the substrate, that is in height.

Alternatively, the bumps may be between 1.7 and 3.4 um in height.

[0021] In some embodiments, at least one of the substrates 110, 120 comprises a — control chip and another one of the substrates 110, 120 comprises a device chip. The control chip may be a detector readout, control or routing chip, for example. The device chip may be a chip for computing using qubits, it may be a detector of various types or a superconducting microrefrigerator, for example.

[0022] In some embodiments, the metal bumps 112, 122 comprise at least one of gold — Au, niobium Nb, copper Cu, silver Ag, degenerately doped silicon Si and aluminium Al.

The metal bumps may comprise one of these metals at a concentration of at least 20% weight, for example.

[0023] In some embodiments, the layer of indium 133 extends solely on a single face of the metal bumps attached on a face of a substrate. The other surface(s) of the metal bumps, — not substantially parallel with the face of the substrate to which the bump is attached, comprise exposed surfaces of the metal bumps in these embodiments.

[0024] In some embodiments, the layer of indium 133 comprises indium which

N comprises less than 1% weight of ferromagnetic material such as, iron, cobalt, or nickel. <Q

S [0025] In some embodiments, a layer of indium 133 comprises indium which

E 25 comprises less than 1% or 5% weight of other material. Such other material may be, for

W example, gold, silver or copper. 3S 3 [0026] FIGURE 1B illustrates a separated example structure of a flip chip

R arrangement with indium attached metal bump interconnects thereon in accordance with at least some embodiments of the present invention. In some embodiments, an indium layer 113, 123 is attached on facing metal bumps 112, 122 of the first 110 and second 120 substrates. In other embodiments, indium is attached on bumps 112 attached to a single substrate 110 only, prior to attachment of the respective bumps 112, 122 together. In some embodiments, each bump to be attached with the indium is provided with indium at a 200 — 300 micrometre thickness prior to attachment. Substrates 110, 120 may be comprised of — silicon or another semiconductor, such as germanium. For example, they may be comprised of high resistivity or doped silicon.

[0027] FIGURE 1C illustrates a perspective representation of an example flip chip arrangement comprising a first and a second substrate with indium attached metal bump interconnects thereon in accordance with at least some embodiments of the present invention. In the state illustrated in FIGURE 1C, the respective bumps 112, 122 have been attached together, leaving the layer of indium 133 therein between. The thickness of the indium layer 133, following the attachment, may be at most 500 nm.

[0028] To arrive at the state illustrated in FIGURE 1C, the bumps on the respective substrates may be attached using TCB at 10 - 150 °C, at 20 — 80 °C or 15 to 70 °C, for example, leaving the indium layer 133 therein between, as illustrated.

[0029] In general, superconductivity of the interconnect may also be suppressed by using a non-superconducting material e.g. copper or gold as the metal. In some embodiments, superconductivity is desired for some, but not all, of the interconnects, wherefore in these embodiments the interconnects for which superconductivity is not wanted are between metal bumps of copper or gold, while interconnects for which superconductivity is wanted are between aluminium or niobium bumps. + [0030] FIGURE 2A illustrates indium attached bumps in a flip chip arrangement with

S three substrates in accordance with at least some embodiments of the present invention. Like = numbering denotes like structure as in FIGUREs 1A — 1C. The three substrates, that is, a e 25 — first 110, a second 120, and a third 140 substrate are layered as a stack of substrates, as metal = bumps 122 are obtained on a first face 120A of the second substrate 120 and metal bumps

W 124 are obtained a second face 120B of the second substrate 120, respectively. The third

S substrate 140 may be comprised of a same substance, or a similar substance, as substrates

X 110 and 120, for example. Indium layers 133 may be at most 500 nm thick. — [0031] In some embodiments, the arrangement comprises more than two substrates 110, 120, 140, wherein the second substrate 120 has a further layer of indium of at most 500 nm thickness attached to at least one metal bump on a second face 120B of the second substrate 120. A first face of the third substrate 140 has attached thereon at least one second metal bump 142 which is further attached to the layer of indium 133, connecting this at least one second bump 142 with the at least one bump 124 on the second face 120B of second substrate 120. In other words, the third substrate 140 forms, together with the first 110 and second 120 substrate, a layered stack of substrates in a flip chip arrangement. In some embodiments, more than three substrates may be stacked in the flip chip arrangement. Thus, one or more additional substrates, not illustrated in FIGURE 2A, may be attached to the flip chip arrangement by attaching the additional substrate(s) to substrate 110 and/or substrate 140 The second face of a substrate is considered to be the face opposite of the first face of the same substrate. In other words, a normal of the first face of a substrate and a normal of the second face of the substrate are substantially antiparallel, that is, parallel and pointing in opposite directions.

[0032] FIGURE 2B illustrates indium attached bumps in a flip chip arrangement with two substrates 120, 140 are attached between two substrates 110, 150, in accordance with at least some embodiments of the present invention. In some embodiments, the dimensions of the metal bumps may substantially vary from one to another. The bumps 112, 122, 124, 142, 143, 152 attaching these substrates 110, 120, 140, 150 together are attached to respective bumps such that a layer of indium 133 is left, of a thickness of at most S00 nm, between the — respective bumps. Also in the cases of FIGURE 2A and 2B, the indium layer 133 may be at most 400 nm, or at most 200 nm, or at most 100 nm alternatively to being at most 500 nm.

[0033] FIGURE 3 is a flow graph of a bonding method in accordance with at least + some embodiments of the present invention. The bonding method for manufacturing

S bonding structures, such as flip chip arrangements, comprises, in phase 310, obtaining at = 25 least a first substrate and a second substrate. Phase 320 comprises obtaining at least one e metal bump on a first face of the first substrate. Phase 330 comprises obtaining at least one

I metal bump on a first face of the second substrate. In phase 340, respective ones of the metal

W bumps on the first face of the first substrate and on the first face of the second substrate are

S then compressed together at a temperature of between 10-80 °C, for example between 15-

N 30 35°C, such that a layer of indium is compressed between respective ones of the metal bumps. = Thus, the bonding structure is formed, comprising a layer of indium bonded between the respective ones of the metal bumps, wherein the layer of indium is at most 500 nm in thickness after the compressing. In some embodiments of the bonding method, the thickness of the layer of indium layer after compression is at most 400 nm. In some embodiments of the bonding method, the thickness of the layer of indium layer after compression is at most 200 nm. In some embodiments of the bonding method, the thickness of the layer of indium layer after compression is at most 100 nm. In some embodiments of the bonding method, the thickness of the layer of indium layer after compression is at most 20 nm.

[0034] Advantageously, as the temperature at which the compressing takes place is low, temperature sensitive structures on or in the substrates are not damaged by heat.

Likewise, the thinness of the indium layer enables the proximity effect to work with regard to superconductivity of the bumps.

[0035] In some embodiments of the bonding method, the compressing is applied for a duration of between 30 seconds — 30 minutes, for example between 1 — 2 min. In some embodiments of the bonding method, the temperature is between 20 — 50 °C. At least in some embodiments of the bonding method, the compression strength is between 3 Newton,

N and 300 N, for example between 40 N - 50 N. — [0036] In some embodiments of the bonding method, only one of the at least two metal bumps on the at least two substrates may contain indium prior to compressing. In other embodiments, both metal bumps that are to be attached together are provided with an indium layer prior to the attaching.

[0037] In some embodiments of the bonding method, the first substrate with a metal bump and indium thereon on may be directly compressed to the second substrate, without a respective metal bump. a [0038] It is to be understood that the embodiments of the invention disclosed are not

N limited to the particular structures, process steps, or materials disclosed herein, but are > extended to eguivalents thereof as would be recognized by those ordinarily skilled in the & 25 relevant arts. It should also be understood that terminology employed herein is used for the

E purpose of describing particular embodiments only and is not intended to be limiting. 3 2 [0039] Reference throughout this specification to one embodiment or an embodiment

N means that a particular feature, structure, or characteristic described in connection with the

N embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Where reference is made to a numerical value using a term such as, for example, about or substantially, the exact numerical value is also disclosed.

[0040] As used herein, a plurality of items, structural elements, compositional elements, and/or materials may be presented in a common list for convenience. However, — these lists should be construed as though each member of the list is individually identified as a separate and unique member. Thus, no individual member of such list should be construed as a de facto equivalent of any other member of the same list solely based on their presentation in a common group without indications to the contrary. In addition, various embodiments and example of the present invention may be referred to herein along with alternatives for the various components thereof. It is understood that such embodiments, examples, and alternatives are not to be construed as de facto equivalents of one another, but are to be considered as separate and autonomous representations of the present invention.

[0041] Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the preceding description, — numerous specific details are provided, such as examples of lengths, widths, shapes, etc., to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.

[0042] While the forgoing examples are illustrative of the principles of the present invention in one or more particular applications, it will be apparent to those of ordinary skill < in the art that numerous modifications in form, usage and details of implementation can be

S made without the exercise of inventive faculty, and without departing from the principles = 25 and concepts of the invention. Accordingly, it is not intended that the invention be limited, e except as by the claims set forth below.

E: [0043] The verbs “to comprise” and “to include” are used in this document as open

S limitations that neither exclude nor reguire the existence of also un-recited features. The

O features recited in depending claims are mutually freely combinable unless otherwise

O 30 explicitly stated. Furthermore, it is to be understood that the use of "a" or "an", that is, a singular form, throughout this document does not exclude a plurality.

INDUSTRIAL APPLICABILITY

[0044] At least some embodiments of the present invention find industrial application in electronics assembly. The use of thin, at most 500 nm, layer of indium attached on metal bumps interconnecting substrates provides superconductivity governed and characterized by the metal bumps rather than the interposed layer of indium as the critical temperature of the system is established to be similar to the critical temperature of the metal bumps. The room temperature, for example 0-80°C, bonding of the metal bumps using the indium layer may be accomplished without negatively affecting the performance of the flip chip arrangement caused by heat. Selecting the thickness of the layer of indium facilitates the tuning of superconductivity of the interconnect to desired critical temperature through the proximity effect. Superconducting quantum computers require three-dimensional integration for which the current invention provides scalable solutions and applications for, for example, superconducting electron coolers wherein the performance is strongly dependent on efficient quasiparticle evacuation.

ACRONYMS LIST

TCB Thermocompression bonding

REFERENCE SIGNS LIST

:

N 113 layer of indium on a metal bump on a first face of the first ;

O 123 layer of indium on a metal bump on a second face of the second

142 layer of indium on a metal bump on a first face of the third substrate 143 layer of indium on a metal bump on a second face of the third substrate 152 layer of indium on a metal bump on a first face of the fourth substrate i

N

O

N

> ™

N

I

= © ©

O

LO

+

N

O

N

Claims

CLAIMS:

1. A bonding structure, comprising at least a first substrate (110) and a second substrate (120), with interconnects between the at least two substrates (110, 120) comprising: — at least one metal bump (112) on a first face of the first substrate (110); — at least one metal bump (122) on a first face of the second substrate (120); and — interposed between the at least one metal bump (112) on the first face of the first substrate (110) and the at least one metal bump (122) on the first face of the second substrate (120), a layer of indium (133), wherein a thickness of the layer of indium (133) is at most 500 nanometres, nm.

2. The bonding structure according to claim 1, wherein the thickness of the indium layer is at most 400 nm.

3. The bonding structure according to claim 1 or claim 2, wherein the thickness of the indium layer is at most 200 nm.

4. The bonding structure according to any one of the preceding claims, wherein dimensions of the at least one metal bump (112, 122) are between 80 um and 125 um parallel to the first face of the substrate (110,120) and 60 - 100 um perpendicular to the first face of the substrate (110,120).

<

5. The bonding structure according to any one of the preceding claims, wherein at least one S 25 — of the substrates (110, 120) comprises a control chip and at least one of the substrates (110, 5 120) comprises a device chip. &

E

6. The bonding structure according to any one of the preceding claims, wherein the metal © bumps (112, 122) comprise at least one of gold Au, niobium Nb, copper Cu and aluminium D 30 Al at a concentration of at least 20% weight.

S

7. The bonding structure according to any one of the preceding claims, wherein the arrangement comprises more than two substrates (210, 220, 240, 250), wherein the second substrate (120) has a further layer of indium (133) of at most 500 nm thickness attached to at least one metal bump (122) on a second face of the second substrate (120).

8. The bonding structure according to claim 7, wherein a third substrate (140) has attached on a first face thereof at least one second metal bump which is further attached to the further layer of indium (133).

9. The bonding structure according to any one of the preceding claims, wherein the layer of indium (133) extends solely on a single face of the metal bumps (112, 122).

10. The bonding structure according to any one of the preceding claims, wherein the layer of indium (133) comprises indium which comprises less than 1% weight of ferromagnetic material.

11. The bonding structure according to any one of the preceding claims, wherein a layer of indium (133) comprises indium which comprises less than 1% weight of metallic material.

12. The bonding structure according to ant of claims 1 — 11, wherein the bonding structure is a flip chip interconnect arrangement.

13. A method for manufacturing bonding structures, comprising: — obtaining at least a first substrate (110) and a second substrate (120); — obtaining at least one metal bump (112) on a first face of the first substrate (110); x — obtaining at least one metal bump (122) on a first face of the second substrate (120); N 25 — compressing together the metal bumps (112) on the first face of the first substrate 5 (110) with the metal bumps (122) on the first face of the second substrate (120) at a Q temperature of between 10-80 °C such that a layer of indium (133) is compressed E between respective ones of the metal bumps, thereby forming the bonding structure O with the layer of indium (133) bonded between the respective ones of the metal 3 30 bumps (112,122), wherein the layer of indium (133) is at most 500 nm in thickness. N &

14. The method according claim 13, wherein the thickness of the layer of indium layer after compression is at most 200 nm.

15. The method according any one of the claims 13-14, wherein the compressing is applied for a duration of between 30 seconds and 30 minutes.

16. The method according any one of the claims 13-15, wherein the temperature is between 20-50 °C.

17. The method according any one of the claims 13-16, wherein dimensions of the at least one metal bump (112, 122) are between 80 um and 125 um parallel to the first face of the substrate (110,120) and 60 - 100 um perpendicular to the first face of the substrate (110,120).

18. The method according any one of the claims 13-17, wherein the metal bumps (112, 122) — comprise at least one of gold Au, niobium Nb, copper Cu and aluminium Al at a concentration of at least 20% weight.

19. The method according any one of the claims 13-18, wherein the arrangement comprises more than two substrates (110, 120, 140, 150), wherein the second substrate (120) has a further layer of indium (133) of at most 500 nm thickness attached to at least one metal bump (122) on a second face of the second substrate (120).

20. The method according claim 19, wherein a third substrate (140) has attached on a first < face thereof at least one second metal bump which is further attached to the further layer of N < 25 indium (133). > =

21. The method according any one of the claims 13-20, wherein the layer of indium (133) E extends solely on a single face of the metal bumps (112, 122). a O 2 30

22. The method according any one of the claims 13-21, wherein the layer of indium (133) + ja comprises indium which comprises less than 5% weight of ferromagnetic material. N

23. The method according any one of the claims 13-23, wherein a layer of indium (133) comprises indium which comprises less than 5% weight of metallic material.