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FI20175352A1 - Laitteisto, laite ja menetelmä laitteen osoittamiseksi laitteiston avulla - Google Patents

Laitteisto, laite ja menetelmä laitteen osoittamiseksi laitteiston avulla Download PDF

Info

Publication number
FI20175352A1
FI20175352A1 FI20175352A FI20175352A FI20175352A1 FI 20175352 A1 FI20175352 A1 FI 20175352A1 FI 20175352 A FI20175352 A FI 20175352A FI 20175352 A FI20175352 A FI 20175352A FI 20175352 A1 FI20175352 A1 FI 20175352A1
Authority
FI
Finland
Prior art keywords
address
address signal
connector
signal
composer
Prior art date
Application number
FI20175352A
Other languages
English (en)
Swedish (sv)
Inventor
Vesa Saastamoinen
Original Assignee
Valmet Automation Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Valmet Automation Oy filed Critical Valmet Automation Oy
Priority to FI20175352A priority Critical patent/FI20175352A1/fi
Priority to EP18397513.5A priority patent/EP3392776A1/en
Priority to US15/953,866 priority patent/US10585836B2/en
Priority to CN201810347581.4A priority patent/CN108733599A/zh
Publication of FI20175352A1 publication Critical patent/FI20175352A1/fi

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/409—Mechanical coupling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Power Sources (AREA)
  • Programmable Controllers (AREA)
  • Debugging And Monitoring (AREA)
  • Details Of Connecting Devices For Male And Female Coupling (AREA)

Abstract

Keksintö koskee laitteistoa (20), laitetta (10) ja menetelmää. Laitteisto (20) on järjestetty osoitteen aikaansaamiseksi laitteistoon (20) liitettävälle laitteelle (10). Laitteisto (20) käsittää ainakin yhden liittimen (21, 21b), joka pystyy vastaanottamaan laitteen (10), osoitteenmuodostimen (22) osoitesignaalin muodostamiseksi sekä liittimessä (21, 21b) olevan osoitelinjan (226) osoitesignaalin antamiseksi laitteelle (10), joka osoitesignaali ilmoittaa osoitteen, jota laitteen (10) tulee käyttää, kun se on liitettynä laitteistoon (20). Osoitteenmuodostin (22) on järjestetty muodostamaan osoitesignaali analogisena osoitesignaalina. Laite (20) käsittää ainakin yhden liittimen (21, 21b), joka pystyy vastaanottamaan laitteen (10), osoitteenmuodostimen (22) osoitesignaalin muodostamiseksi, liittimessä (21, 21b) olevan osoitelinjan (226) osoitesignaalin antamiseksi laitteelle (10), joka osoitesignaali osoittaa osoitteen, jota laitteen (10) tulee käyttää, kun se on liitettynä laitteistoon (20), sisäänmenon (23a) osoitesignaalin vastaanottamiseksi analogisena osoitesignaalina, vertailupiirin (11) analogisen osoitesignaalin tason vertaamiseksi joukkoon vertailuarvoja, sekä määrityspiirin (12) laitteen (10) käyttämän osoitteen määrittämiseksi vertailun tuloksen perusteella.
FI20175352A 2017-04-18 2017-04-18 Laitteisto, laite ja menetelmä laitteen osoittamiseksi laitteiston avulla FI20175352A1 (fi)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FI20175352A FI20175352A1 (fi) 2017-04-18 2017-04-18 Laitteisto, laite ja menetelmä laitteen osoittamiseksi laitteiston avulla
EP18397513.5A EP3392776A1 (en) 2017-04-18 2018-04-06 An apparatus, a device, and a method for addressing a device by the apparatus
US15/953,866 US10585836B2 (en) 2017-04-18 2018-04-16 Apparatus, a device, and a method for addressing a device by the apparatus
CN201810347581.4A CN108733599A (zh) 2017-04-18 2018-04-18 装置、设备以及通过装置为设备寻址的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FI20175352A FI20175352A1 (fi) 2017-04-18 2017-04-18 Laitteisto, laite ja menetelmä laitteen osoittamiseksi laitteiston avulla

Publications (1)

Publication Number Publication Date
FI20175352A1 true FI20175352A1 (fi) 2018-10-19

Family

ID=62046855

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20175352A FI20175352A1 (fi) 2017-04-18 2017-04-18 Laitteisto, laite ja menetelmä laitteen osoittamiseksi laitteiston avulla

Country Status (4)

Country Link
US (1) US10585836B2 (fi)
EP (1) EP3392776A1 (fi)
CN (1) CN108733599A (fi)
FI (1) FI20175352A1 (fi)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107562165B (zh) * 2017-08-03 2020-06-26 苏州浪潮智能科技有限公司 一种为服务器供电的电源装置和电源管理系统
KR102565184B1 (ko) * 2018-07-09 2023-08-08 에스케이하이닉스 주식회사 디지털 회로를 모델링하는 회로 모듈 및 이를 포함하는 시뮬레이션 장치
CN109743413A (zh) * 2019-01-04 2019-05-10 浪潮商用机器有限公司 一种服务器节点网络ip地址分配方法、装置及服务器
WO2020147933A1 (en) * 2019-01-15 2020-07-23 Heldeis Christoph Keyboard, bus unit, bus control unit and method for operating a keyboard
CN116074732B (zh) * 2021-10-29 2025-06-24 比亚迪股份有限公司 一种uwb系统、uwb锚点模块、uwb主控模块及车辆

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6438625B1 (en) * 1999-10-21 2002-08-20 Centigram Communications Corporation System and method for automatically identifying slots in a backplane
US6564278B1 (en) 1999-10-21 2003-05-13 Ulysses Esd, Inc. System and method for obtaining board address information
US6577250B1 (en) 2000-05-19 2003-06-10 Microsoft Corporation Resistance based keyboard key discrimination
US7340538B2 (en) 2003-12-03 2008-03-04 Intel Corporation Method for dynamic assignment of slot-dependent static port addresses
TWI281805B (en) 2004-05-18 2007-05-21 Quanta Comp Inc System for automatically distributing communication port address
US7240142B2 (en) * 2004-10-06 2007-07-03 Tellabs Petaluma, Inc. Master electronics card with an adaptive bandwidth circuit
US20070245061A1 (en) * 2006-04-13 2007-10-18 Intel Corporation Multiplexing a parallel bus interface and a flash memory interface
US7827330B2 (en) * 2007-07-27 2010-11-02 Microchip Technology Incorporated Configuring multi-bit slave addressing on a serial bus using a single external connection
JP2009118155A (ja) * 2007-11-06 2009-05-28 Kyocera Mita Corp スレーブノード、及び、画像形成装置、及び、スレーブアドレス設定方法
US7962661B2 (en) 2008-06-30 2011-06-14 Lg Chem, Ltd. System and method for determining a bus address for a controller within a network
JP2010245988A (ja) 2009-04-09 2010-10-28 Yazaki Corp 通信アドレス検出装置、制御回路内蔵コネクタ、及び、通信アドレス検出方法
JP4957813B2 (ja) * 2010-01-26 2012-06-20 株式会社デンソー 通信用スレーブ及び通信ネットワークシステム
US9146259B2 (en) * 2011-04-19 2015-09-29 Schneider Electric It Corporation Smart current transformers
CN105138485A (zh) * 2015-08-21 2015-12-09 上海斐讯数据通信技术有限公司 一种串行总线地址管理装置

Also Published As

Publication number Publication date
CN108733599A (zh) 2018-11-02
EP3392776A1 (en) 2018-10-24
US20180300281A1 (en) 2018-10-18
US10585836B2 (en) 2020-03-10

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