ES397329A1 - Procedure and apparatus for the operation of an intermediary memory. (Machine-translation by Google Translate, not legally binding) - Google Patents
Procedure and apparatus for the operation of an intermediary memory. (Machine-translation by Google Translate, not legally binding)Info
- Publication number
- ES397329A1 ES397329A1 ES397329A ES397329A ES397329A1 ES 397329 A1 ES397329 A1 ES 397329A1 ES 397329 A ES397329 A ES 397329A ES 397329 A ES397329 A ES 397329A ES 397329 A1 ES397329 A1 ES 397329A1
- Authority
- ES
- Spain
- Prior art keywords
- figures
- bits
- data
- translation
- procedure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 title abstract 2
- 230000001902 propagating effect Effects 0.000 abstract 2
- 230000003993 interaction Effects 0.000 abstract 1
- 230000001360 synchronised effect Effects 0.000 abstract 1
Landscapes
- Machine Translation (AREA)
Abstract
Procedure for the actuation of an intermediate memory, in which data bits are represented by physical manifestations that exhibit mutual interaction when they are close to each other, which comprises the step of (a) propagating first bits of data, in sequential order, in a first information channel (ml1, figures 3 and 4, sl2, figures 5 and 6, ml1-1, figure 12, 118, 119, and'0-0','1-1' figure 13), characterized by comprising further the steps of (b) propagating second bits of data in a second information channel (sli, figures 3 and 4; il1, figures 5 and 6; il1-2, figure 12; 115, 116 and 123, 124, figure 13 ) in physical proximity with the first bits of data and synchronously with them; and (o) channel the first data bits (to ml1-1 or ml1-2, figures 3 and 4, ec or sl2-1, figures 5 and 6, ml1 or il1-5, figure 12,'0-0' or e2,'1-1' or e1, e3 or 121, e4 or 122, figure 13) to obtain logic outputs in response to interreaction between corresponding first and second bits of synchronized data when they are physically placed next to each other. (Machine-translation by Google Translate, not legally binding)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US8963170A | 1970-11-16 | 1970-11-16 | |
| US8962170A | 1970-11-16 | 1970-11-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ES397329A1 true ES397329A1 (en) | 1974-05-16 |
Family
ID=26780781
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ES397329A Expired ES397329A1 (en) | 1970-11-16 | 1971-11-15 | Procedure and apparatus for the operation of an intermediary memory. (Machine-translation by Google Translate, not legally binding) |
Country Status (1)
| Country | Link |
|---|---|
| ES (1) | ES397329A1 (en) |
-
1971
- 1971-11-15 ES ES397329A patent/ES397329A1/en not_active Expired
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