ES2561913B2 - Systems and methods for turbo iterative decoding of low error rate and low complexity - Google Patents

Abstract

Systems and methods for turbo iterative decoding of low error rate and low complexity. The invention relates to a method of turbo iterative decoding of low error rate and low complexity characterized in that it comprises (a) the storage of LLR metrics in an input memory bank that subsequently delivers, either the block corresponding to a non-decoder parallel that works forward (fw) and backward (bw), either the sub-blocks corresponding to two or more parallel decoders fw / bw; (b) the calculation of a-posteriori metrics by the decoder (s); (c) the calculation by one or more extrinsic calculation units of the extrinsic information; and (d) the comparison of the LLR a-posteriori fw and bw measurements over different iterations. The invention relates to different implementations of the method as well as systems that implement said method and its variants.

Description

ES 2 561913 Al

Systems and Methods Dara turbo iterative decoding of low error rate and low

complexity

TECHNICAL SECTOR

The invention relates to digital communications, in particular associated systems and methods.

S

to iterative decoding based on the SOYA (Sofl Oulput Viterbi Algorithm) algorithm that

can be applied to mobile communications standards such as 3GPP (3rd Generate / ion

Partneship Projecl), LTE (Long Term Evolution) and UMTS (Universal Mobile

Te / ecommunications System). More particularly, the invention relates to systems and methods

for turbo parallel iterative decoding for which overlap is not required between

10

Adjacent sub-blocks, thereby reducing the latency of drastic foon decoding.

STATE OF THE TECHNIQUE

The turbo codes have been widely used in mobile communications standards

modern due to its enormous corrective capacity that allows reliable data transmissions

close to the ergodic capacity of the system. The turbo encoder consists of concatenation

fifteen

in parallel of two RSC (Recursive Systematic Convolutional) encoders separated by a

interleaver that brings randomness to the code. Decoding consists of a process

iterative in which the extrinsic information is generated (in each iteration), which is used as

a-priori information in the next iteration. This allows to use a MAP criterion (Maximum A

Subsequent) that minimizes the error rate or BER (Bit Error Rate). The classic decoder turbo

twenty

It uses a SISO (Soft In Soft Out) decoder that generates extrinsic information in the form of

LLR values (Log Likelihood Ratio), and two interleavers, one for the data received from the

channel and another for extrinsic information. Fig. 1 illustrates the functional diagram of a turbo

classic decoder In said figure, the SISO I element decodes the message while

the SISO 2 element decodes the interlaced message. It is said that full iterations

25

decode the message while semi-iterations decode the interlaced message. He

Functional diagram of Fig. I can be implemented in different ways that are identified

in this document as: (1) turbo serial decoding, (2) turbo concurrent decoding

and (3) turbo shuffled decoding.

A functional diagram of turbo serial decoding is shown in Fig. 2, where the line

30

Horizontal represents time. Note that, due to the fact that the SISO 2 decoder

you have to wait until SISO I has decoded the entire block, this architecture is

You can implement using only a SISO decoder. Fig. 3 is a functional scheme of the

turbo concurrent decoding. Note that in the literature the tennino turbo decoding

parallel is commonly used to refer to the method we have called here turbo

35

concurrent decoding; however in this document we have preferred to reserve the ténnino

turbo parallel decoding for another type of architecture that will be explained

later. In the turbo concurrent decoding the complete and semi iterations

iterations are performed at the same time by a different SISO decoder: one decodes the

message and the other the interlaced message. Therefore the convergence speed is increased

40

of decoding. The extrinsic infonation exchange is represented with lines

black in that figure. Another architecture known as turbo is shown in Fig. 4

shuffled decoding. This architecture requires two SISO decoders as in the

concurrent architecture However, in this case the a-priori information is allowed to be

exchanged between both decoders in the same iteration provided that

Four. Five

Information is available. Such architecture accelerates the speed of convergence even more

that the turbo concurrent decoding, however requires an access mechanism to

quite complex memory. In Juntan Zhang and others "Shuftled iterative decoding" work

published in the journal IEEE Transactionson Communications, vol. 53, 2005 And in the references

present in this work you can get more information about this architecture for the

S

Decoding with turbo codes. Due to the fact that the turbo serial decoding is the

More commonly we will refer to this architecture in this document.

There are essentially two families of SISO algorithm for turbo decoding: MAP and

I AM A (Soft Output Viterbi AIgorithm). A detailed description of these algorithms can be

Find in "Comparative study of turbo decoding techniques: an overview", published in the

10

IEEE Transactionon Vehicular Technology magazine, vol. 49, 2000 by Woodard and others. He

MAP algorithm offers a decoding gain of approximately 0.6 dB over the

I AM at the expense of having more latency and greater chip area even in their

Simplified versions Max-Log-MAP and Log-MAP. Some proposals have been made with the

in order to reduce this difference in decoding gain due to the attractive

fifteen

SOYA algorithm features for efficient chip implementation. Specific,

Fossorier and others presented in the article entitled "On the equivalence between SOY A and

max-Iog-MAP decodings ", published in IEEE Communication Letters, vol. 2, 1998

a modification of the SOYA algorithm that makes it equivalent to the Max-Log-MAP algorithm.

Unfortunately the proposed algorithm is significantly more complex than the

twenty

original SOYA algorithm. In the article "Adaptive SOYA for 3GPP-LTE Receivers" by

Blanquez-Casado and others, published in IEEE Communications Lettcrs, vol. 18, June

2014 presents a modification of the SOYA algorithm that significantly improves the

corrective capacity., especially when high modulation rates are used and

coding. However, the proposed algorithm requires the use of an update window.

25

of weights of variable size that makes its implementation on a chip difficult.

An alternative is the algorithm known as BISOV A (Bi-directional I AM) in the

that two SOYA decoders decode the sequence received in each iteration by doing

that the corrective capacity is similar to that of the MAP algorithm; however complexity is

double too. This proposal was first presented by Chen and others with the article

30

titled "Bi-directional SOYA decoding for turbo-codes" published in IEEE magazine

Communication Letters, vol. 4, 2000. An architecture to implement said algorithm that is

efficient from the point of view of memory use was presented by Efimov and others in the

patent titled "HIGH-THROUGHPUT MEMORY -EFFICIENT BI-SOY A DECODER

ARCHITECTURE ", US 2008/0152045 A. Notwithstanding this architecture as it is based on the

35

BISOV A algorithm continues to present greater complexity than those based on the algorithm

SOY.

BISOVA requires two SOVA ~ decoders or two banks of SOYA decoders in the

parallel case working at the same time in each iteration. The key idea behind the BISOVA algorithm

is to perform the SOYA algorithm in different pennite directions to obtain information

40

distinct that helps improve turbo decoding. In the SOYA algorithm there is a process

of update that seeks to improve the quality of the weights, or measures of reliability, associated

at each decoded bit for stage k Can in order to obtain the a-posteriori LLR measurements

late. This update process compares reliability or weights associated with the ML path

(Maximum Likelihood) in stage k with the reliability of the competing roads to

Four. Five

ML path that bind to it and are discarded in later stages than k. However, there are

paths that are not taken into account in the update process because they are discarded before

S

of mixing with the ML path. This fact leads to an overestimation of the 3posteriori measures in SOYA that reduces its corrective capacity. However, some roads that are discarded before joining the ML path in one direction may not be ruled out before joining that ML path in the other direction. Therefore, performing the SOYA algorithm in both directions can improve turbo decoding. In the BISOV algorithm A. in the iteration ¡, one of the decoders calculates the LLR a-posteriori measurements forward, identified with the symbol Ui \ (Uk), while the other calculates them backwards, identified with the symbol L ( i) b (Uk) 'Then, the final a-posteriori measurements in BISOVA can be calculated as

(one)

10

This greatly improves the corrective capacity at the cost of doubling the chip area consumption.

15 20 25

The iterative nature of turbo decoding is associated with considerable latency that makes it difficult to meet the binary regime requirements associated with modem standards such as LTE (Long Tenn Evolution). Because of this, parallel decoding becomes essential. In parallel decoding each block to be decoded is divided into several sub-blocks that are decoded at the same time by a different SISO decoder. Although this pennite strategy reduces latency efficiently, the parallelization has two major drawbacks: (1) the consumption of chip area is greater and (2) there is a non-negligible loss in corrective capacity due to the uncertainty that exists in the borders between sub-blocks. With the purpose of mitigating the second problem, overlap between sub-blocks is usually used to reduce the uncertainty between sub-blocks at the cost of increasing the decoding latency. As the AMY A decoder is less complex than MAP, its implementations consume less chip area and therefore the first one is especially suitable for turbo parallel decoders where area consumption is a primary issue. However, the MAP algorithm has been traditionally preferred due to its greater corrective capacity. These facts justify the need to devise modifications of the SOYA algorithm that allow to obtain corrective capabilities close to the MA P algorithm while maintaining the low complexity of the SOYA algorithm.

DESCRIPTION OF THE INVENTION

30 35

The invention relates to a modification of the SOY A algorithm which, unlike the proposals mentioned above, improves its corrective capacity when applied to turbo decoding without any increase in area or latency consumption. This modification called ALSOYA (ALtemated direction SOY A) improves the corrective capacity of the SOYA algorithm without any increase in area or latency. ALSOYA improves the corrective capacity of the SOYA algorithm when it is applied to iterative decoding without any increase in chip area consumption or latency. Therefore this method can be applied to turbo decoding following different architectures such as serial, concurrent and shuffle architecture using parallel and non-parallel embodiments of the SOYA decoder bank. The ALSOV A algorithm can also be applied to iterative equalization, in the same way that the MAP and SOYA algorithms are used in this field.

40

The ALSOYA algorithm is based on the same principle as the BISOVA algorithm, that is, it carries out the process of updating in different directions of fonna that reduces the overestimation of the a-posteriori measures by taking into account more paths. However, unlike the BISOYA algorithm, the ALSOYA algorithm does not perform decoding in

S

both directions during the same iteration. In contrast, the ALSOV A algorithm compares the a-posterior LLR measurements calculated forward and backward through different iterations by exchanging extrinsic information between iterations. This pennite use a single SOYA decoder instead of two. The SOyA decoder must be able to perform decoding both forward and backward; However, this issue has a minimal impact on the area consumption since most of the units that make up the decoder are not affected. Therefore, the invention proposes to calculate the LLR measurements forward in the even iterations, and the LLR measures backward in the odd iterations as follows:

10

. L "'(u.) {Lj) (U.) Ifmod (lij, 2) ~~ l. L ~) (u.) Ifmod (liJ, 2) ~ (2)

The ground function being liJ. In the previous expression it is considered that in a complete iteration the message is decoded, while in each semi-iteration the interlaced message is decoded. The iterations begin at i = l, while the semi-iterations begin at i ~ L5.

fifteen

The overestimation of erroneously decoded bits has a considerable effect on the turbo

twenty

decoding because it can propagate errors throughout iterations. Our approach proposes to decode forward and backward in odd and even executions of the decoder, respectively. Therefore, if in stage k an erroneously decoded bit has an overestimated LLR, this overestimation can be propagated until the next semi-iteration. However, because the other iteration is going in the opposite direction, other paths can be considered, mitigating overestimation and preventing the spread of error.

25

The proposed ALSOVA algorithm can be implemented in turbo serial, parallel or shuffled decoding using both a non-parallel implementation of each constituent SISO decoder and a parallel embodiment of each constituent SISO decoder. In the latter case we have in fact a bank of SISO decoders. The ALSOV A algorithm can also be used in turbo equalization: the ALSOV A algorithm requires the implementation of a forward / backward SOYA decoder, or fwlbw of forwardlbackward English, which can perform decoding in both directions in different iterations. In this document you

30

provides an embodiment of said decoder. In addition, a possible embodiment of a turbo decoder is provided using the ALSOV A algorithm for parallel and concurrent parallel series architectures.

PMSBx

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Additionally, the invention also relates to a new architecture for turbo decoding in parallel, identified with the acronym PMSBx qut: it comes from the English PathMetric / StateBorder Exchange. This architecture mitigates performance degradation in terms of BER (Bit Error Rate) or bit error rate associated with parallel decoding. PMSBx uses the fact that road metrics are reliable on the right edge of the sub-blocks and therefore can be used as initialization metrics for the next subblock of the next iteration.

PMSBx achieves better performance than classical methods based on sub-block overlap. Unlike other approaches, PMSBx does not require overlap between subblocks, therefore it reduces the latency of decoding. The overlap has the disadvantage that it increases the decoding latency, reducing the attainable bit rate. On the other hand, the BER of the turbo decoding in parallel without overlapping undergoes significant degradation due to uncertainty at the edges of the sub-blocks.

PMSBx takes advantage of the different reliability of the PMs and the states of the ML path to improve the performance of the decoding and is based mainly on two premises:

•

Convergence of road metrics: Because the left edge of a sub-block corresponds to the right edge of the previous sub-block, the PMs of the right edge of a sub-block can be used as initial PMs for the following sub-blocks In the next iteration. This takes advantage of the fact that these PMs are reliable. This idea was exploited by Yoon, "A parallel MAP algorithm for low latency turbo decoding", IEEE Communications L. ethers, 2002, which presents a method for the parallel MAP algorithm that achieves the same corrective capacity as in the non-parallel case but without any increase in latency. This method is identified in this document as SBL In the case of the SOY A algorithm, PMs are reliable on the right edge of a sulrblock. Therefore, these metrics can be used as initialization metrics for the next sub-block in the next iteration in the case of the SOY A algorithm.

•

Convergence of the states for the ML path: By initializing with reliable metric values, the states of the ML path will be reliable on the left edge of the sub-blocks. These states produced by an SOY A decoder can be used to make the last backward travel or TB from a reliable state of the previous SOYA decoder, considerably reducing the overestimation of the LLR aposteriori values, which degrades the performance in terms of BER. Because the states on the left sub-border are available before TB is performed on the left edge, these states can be exchanged in the same iteration. Keep in mind that this is not applicable for road metrics since these are exchanged between full iterations.

The invention also relates to (i) computer programs adapted to, or comprising software code adapted to, carry out the methods of the invention; (ii) computer readable storage media comprising said computer programs or comprising instructions for making a data processing apparatus carry out the methods of the invention; (iii) recording carrier media with said computer programs recorded in them; (iv) signal carrying waves carrying signals incorporating said computer programs.

BRIEF EXPLANATION OF THE FIGURES Fig. I illustrates the functional diagram of the turbo decoding. Fig. 2 shows a timing diagram of the turbo serial decoding. Fig. 3 shows a timing diagram of the turbo concurrent decoding. Fig. 4 shows a timing diagram of the turbo decoding shuffled.

Fig. 5 illustrates a functional diagram of parallel decoding using overlap between sub blocks Fig. 6 shows a timing diagram of the proposed turbo decoder architecture in series using ALSQV A. Fig. 7 illustrates the structure of a possible embodiment of the invention using the architecture in parallel series.

Fig. 8 illustrates a possible embodiment of the SOYA fwlbw decoders.

Fig. 9 illustrates a possible embodiment of the Recursion Unit fw / bw of the SOYA fwlbw decoder.

Fig. 10 provides a time diagram associated with the concurrent architecture using the

ALSQVA proposed algorithm. Fig. 11 illustrates a structure of a possible embodiment of the invention using the concurrent parallel architecture.

Fig. 12 illustrates the structure of the PMSBx invention that can be applied to algorithms SOYA, ALSOVA and BISOVA.

EMBODIMENTS OF THE INVENTION Several publications are referenced in this application. The contents and disclosures included in these, as well as in all the references cited by said publications. are incorporated in the present application in order to describe in a complete and detailed way the state of the art to which this invention belongs. the tenninologla that is used from now on is used for the purpose of accurately describing determined concepts, and should not be considered as imimitant.

The invention improves the error correction capacity of a turbo decoder based on the SOYA classic algorithm without any increase in complexity. This invention can be used. with turbo parallel and non-parallel decoding, a functional description is illustrated in Fig. 5 of parallel decoding using overlap between sub-blocks. Codes are assumed with trellis tennination as is the case with the L TE code, that is, the initial and final state is

known, the zero state being commonly. The length of the block to be decoded is K + T where K is the length of the message and T the number of stages required to return to the state zero. In the case of having P SISO decoders working in parallel each sub-block has a length of M + L stages except the last sub-block that has a length of M + U2 + T stages and the first sub-block of M + U2, with M = K1P and L being the number of overlap stages. The sequence decoded by each decoder has a length of M bits.

ALSOVA for turbo parallel series decoding

A timing diagram of the proposed ALSOV A method is shown in Fig. 6, for seric decoding of turbo codes. Specifically, two complete iterations of the algorithm are shown, although the decoding process can be extended to any number of iterations according to the stopping criteria.

In Fig. 7 a possible embodiment of the invention is presented following the architecture of a turbo decoder in parallel series. The block diagram of said figure shows the LLR measurements of the channel associated with a turbo code rate 1/3 with a systematic bit and two parity bits as is the case of the one used in L TE technology. These LLR metrics are represented in the figure as Ls, Lp 1 and Lp2 respectively. The metrics Ls and Lp I are related to the message, while the metric Ls2 is related to the interlaced message. These metrics are stored in the Input Memory Bank 701. Said unit is able to deliver to each parallel decoder within the parallel decoder bank the corresponding block. In addition, the Input Memory Bank 701 intertwines the Ls metrics when carrying out a semi-iteration, thus being able to deliver said metrics to the SOYA Decoder Bank fw (forward) and bw (backward) 704.

The SOY A fwlbw 704 Decoder Bank calculates a-posteriori metrics in the forward direction (odd iterations) and backward (even iterations), respectively. In this way, both the Input Memory Bank 701 and the Extrinsic Memory Bank 70S can deliver data to the SOYA fiN / bw 704 Decoder Bank in both directions. The Control Unit 702 determines the behavior of the different units depending on the iteration or semi-iteration that is carried out at each moment. The Extrinsic Calculation Unit 706 calculates extrinsic information using the LLR metrics of the channel and the a-posteriori metrics. This unit performs a subtraction. although it can also carry out a multiplying by a certain scale factor, and / or a compression or quantification of the metrics. In the figure, buses that deliver P metric LLR per cycle are identified with the letter P.

Note that from the architecture shown in Fig. 7, a non-parallel serial decoder turbo can easily be obtained: In this case (non-parallel serial decoder) P would be equal to, and therefore element 704 would contain so only a SOYA fw "lbw 703 decoder; in addition elements 701 and 70S would have to deliver information relative to a single block, instead of delivering simultaneous information of several sub-blocks, that is, the buses that appear in the figure connecting the Elements 701 and 70S with 704 would only deliver one metric per bus (P = I); finally, as in non-parallel decoding there is a block to be decoded whose start and end states are known, there is no need to apply any type of overlap which simplifies the behavior of elements 701 and 70S.

Each of the soyA fiN / bw 703 parallel decoders has the structure shown in Fig. 8. Recursive Unit fw / bw801 performs the following functions: (i) calculate the path metric or PM for each of the N states; (ii) select the surviving path and (jii) obtain the weight of this decision as the difference of the MPs between the surviving paths. The decision regarding the surviving roads and the corresponding weights for each state is used to construct the vectors Y and W, of length N, as shown in Fig. 8. This unit is responsible for performing the functions mentioned above, both in the forward direction as in the backward direction.

The Control Unit 804 implements a finite state machine that activates the appropriate control signals for the rest of the units presented in Fig. 7, allowing said units to perform their function in the forward or backward direction, depending on the iteration in which you are. The decisions are delivered to the fwlbw 803 Survivors Memory Unit. This unit travels backwards or TB to find the ML path. Since this unit must carry out the calculation of the backward travel, the combinational logic that calculates the previous state for a detained state must be different depending on the direction. One considers the state machine forward and the other the state machine backward. The states of this path are introduced to the Update Process Unit fw / bw 80S. Since element 803 requires a certain number of clock cycles to obtain states of said path, retarder element 802 applies the same delay in clock cycles to weights W (differences between PMs). This unit is responsible for updating the weights calculated by the Twlbw 801 Recursive Unit. To carry out this update process, a double backward travel or TB must be carried out: one TB obtains the ML path, while the other obtains The competing path. In each stage in which the bit decided for both paths differs, an update is carried out. This update consists in the selection of the minimum weight between the competing road and the ML roads. This unit must also work both in the forward and backward direction when carrying out the TB. Finally, after the update process, the LLR a-posterior metrics are obtained in the forward or backward directions depending on the current iteration.

The structure of the Recursive Unit fw / bw 801. is illustrated in Fig. 9. This unit is made up of N Recursion Elements 902, which calculate the PM and carry out the tasks (i) - (iii) for each state. For this, each Element of Recursion 902 needs to know the measures Ls, Lp and La. In the case of a full iteration, Lp is Lpl. In the case of a semi-iteration, Lp is Lp2 and Ls has been interlaced by the Input Memory Bank 701. On the other hand, La is the a priori information, or equivalently the extrinsic metrics of the previous semi-iteration. .

To calculate the PMs for each state If in stage k, the PM of the roads that converge to Si in the previous stage k-1 are needed. One of these paths, the one associated with uk "" l, is identified as PM. (Si), while the other, associated with Uk = O, is identified as PMo (Si). As the roads that converge in each state are different in the forward and backward directions, an interconnection network is required. This task is performed by the Connection Unit fw / bw 901. This unit delivers the appropriate PM from the previous stage to each Recurrence Element 902, depending on the direction (forward or backward). One possible way to implement this element is through a bank of multiplexers and registers to store the previous PM.

ALSOVA for turbo parallel concurrent decoding

Fig. 10 shows a time diagram of the proposed ALSOV A method, for parallel concurrent decoding, while Fig. 11 shows a possible implementation of it. In this implementation, the Input Memory Bank 1101 must simultaneously feed two Banks of SOYA fw / bw decoders. In this way, it must provide the metric Ls both interlaced and non-interlaced There are two banks of extrinsic information. On the one hand, the Extrinsic Information Bank 1 1103 always deinterlaces extrinsic measures. However, in odd iterations you read and write forward while in even iterations you read and write backwards. On the other hand, the Extrinsic Information Bank 2 1104 always intertwines extrinsic measures. This bank works forward on odd iterations and backward on even ones. The Extrinsic Calculation Units 706 and the SOYA fw / bw decoder Bank are equivalent to the case shown in the previous section.

ALSOVA-PMSBx for turbo parallel serial decoding

The PMSBx technique can be combined with the SOYA, ALSOVA and BISOVA algorithms. In the cases of BISOVA-PMSBx and ALSQVA-PMSBx there are two different types of road metrics or PMs and T8s, one in the forward direction and the other in the backward direction. In the case of BISOV A, this fact does not imply any modification with respect to SOYAPMSBx since the initialization is carried out within two independent banks of SOYA decoders. However, in the case of ALSOV A-PMSBx, the PMs have to be exchanged between two iterations since the PMs of the previous iteration have been calculated in a different direction. Formally, the initialization of the PMs can be described with the following equation.

PM (; ~ O, ~ I) (k) 1 PMu.lI) (k): c: 's, /, 11'

n "11

s, / 11 (3)

. {log (or (s)), n ~ l

where the symbol O represents the delay in iterations that is applied to the PMs that are exchanged between parallel decoders. In the case of SOYA and BISOYA 0 = 1 while for ALSOV A 0 = 2. The stage at which initialization is performed for suh-block n is kl, l = O for n = 1 and k1, n = (n-l) M for n> 1.

The initialization of states in order to make the TBs is as follows

SU "" '(k) P

S (i, II) (s, k) = S, r, n, n; Jt

(4) r, 1I {O n = P

,

where the stage in which the last TB is performed is kr, p = K + T for n = P and kr, n = nM for n <P. The above equation is valid for SOVA-PMSBx, ALSOVA-PMSBx and BISOYA-PMSBx since the states are exchanged in the same iteration,

The proposed architecture for a turbo parallel series decoder using ALSOV A-PMSBx is shown in Fig. 7, The decoding direction is changed throughout the iterations (as described above) in order to improve the corrective capacity without significantly increasing latency or area consumption. The Memory Bank at Entry 701 and the Extrinsic Memory Bank 70S are capable of feeding the Bank of decoders SISO 704 in the forward and backward directions. Control Unit 702 determines the behavior of the different units depending on the iteration (or half iteration) to be performed at each moment. However, the case of the SISO parallel decoder bank 704 has another architecture shown in Fig. 12, which confers to which said parallel SISO decoder bank 704 comprises, among others, a Control Unit 1304, as can be seen , the connections between the decoders SOYA fw / bw 703 penniten the exchange of information to alleviate the uncertainty at the edge of the sub-blocks, The exchange of PM is made thanks to the unit 1303, which applies a delay to the PMs of two full iterations (0 = 2), or what is the same, at four half iterations. The exchange of states is carried out thanks to memory records 1302 that store said information during the iteration in which it is required. In addition, decoders 703 are fw / bw decoders with an architecture like that shown in Fig, 8. These decoders are capable of performing the SOY A decoding both forward and backward, depending on the iteration in question.

Claims (17)

l. Method for turbo iterative decoding of low error rate and low complexity characterized by comprising: 3. The storage of LLR metrics in an input memory bank that subsequently delivers, either the block corresponding to a non-parallel decoder that works forward (fw) and backward (bw), or the subblocks corresponding to two or more fw / bw parallel decoders said two or more fw / bw parallel decoders comprised in one or more parallel banks of decoders SOY A fwlbw;

b.

the calculation of a-posterior metrics either by said non-parallel decoder fwlbw or by said two or more parallel decoders fw / bw;

C.

the calculation by one or more extrinsic calculation units of the extrinsic information from the LLR metrics and the a-posterior metrics;

d.

and the comparison of the a-posterior LLR measures calculated forward and backward through different iterations by exchanging the extrinsic information between iterations by calculating the LLR measurements forward in the even iterations, and the LLR measurements backward in odd iterations, it confers to equation (2)

. {L'f "(U,) ifmod ([iJ, 2) ~ 1 L '' '(u), L ~, <u,) ifmod <liJ, 2) ~ being li J the ground function.

2.

Method according to the preceding claim characterized in that the input memory bank delivers the corresponding block to a non-parallel decoder fwlbw, said non-parallel decoder fwlbw responsible for calculating a-posteriori metrics.

3.

Method according to claim 1 characterized in that it comprises:

to.

The storage of LLR metrics in an input memory bank that subsequently delivers the sub-blocks corresponding to two or more fwlbw parallel decoders, said two or more fw / bw parallel decoders comprised in one or more parallel banks of SOYA fwlbw decoders;

b.

The interlacing of LLR metrics before the delivery of the corresponding sub-blocks by I input memory bank to two or more fw / bw parallel decoders, said two or more fwlbw parallel decoders comprised in a parallel bank of SOYA decoders fwlbw;

C.

the calculation of a-posteriori metrics by said two or more fwlbw parallel decoders;

d.

the calculation by one or more extrinsic calculation units of extrinsic infonation from LLR metrics and a-posteriori metrics;

and.

and the comparison of the a-posterior LLR measures calculated back and forth over different iterations by exchanging the extrinsic information between iterations calculating the LLR measurements

forward in even iterations, and LLR measures back in the

odd iterations according to equation (2)

Lj '(U¡) ifmodqij, 2) ~~ 1LV' (u¡) _

{L ~ '(u¡) ifmod (liJ, 2) = O

lj J being the ground function.

5

Four.

Method according to the preceding claim characterized in that it comprises the use of the

road metrics (PMs) on the right edge of the sub-blocks as metrics for

initialization for the next sub-block of the next iteration; and the use of

road states (ML) of the left edge of the sub-blocks to make the last

10

backward travel (TB) from a reliable state of the decoder I AM A fw / bw

prior, said interchangeable path states (ML) in the same iteration.

5.

Method according to claim 3 comprising

to. The delivery of the corresponding sub-blocks by the memory bank

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input to two or more fw / bw parallel decoders, said two or more

fw / bw parallel decoders comprised of two or more parallel banks

of SOYA fw! bw decoders;

b. the calculation by two or more extrinsic calculation units of the information

extrinsic from LLR metrics and a-posteriori metrics;

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C. deinterlacing the extrinsic information calculated by at least one of

extrinsic calculation units by at least one information bank

extrinsic that works forward (fw) in odd iterations while

that works backward (bw) in even iterations;

d. and the interlacing of extrinsic information calculated by at least one of the

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extrinsic calculation units not involved in step (c) by at least one

extrinsic information bank not involved in stage (c) and that works

backward (bw) in even iterations while working forward (fw)

in odd iterations.

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6. System for turbo iterative decoding of low error rate and low complexity that

implements a method according to claim 2 characterized in that it comprises

an input memory bank, a control unit, a decoder I AM A does not

parallel fw / bw, an extrinsic memory bank and an extrinsic calculation unit; from

fonnaque,

35

to. the input memory bank stores LLR metrics, interlaces them

when it performs a semi-iteration, and provides the block to the

corresponding SOYA non-parallel fw / bw decoder;

b. the decoder I AM A non-parallel fw / bw calculates metrics a-posterior towards

forward in odd iterations and backward in even iterations;

40

C. the control unit determines the behavior of the different units

depending on the iteration or semi-iteration that is carried out in each

moment;

d. And the extrinsic calculation unit calculates the extrinsic information using

LLR metrics and a-poster metrics.

7. System for turbo iterative decoding of low error rate and low complexity that It implements a method according to claim 3 characterized in that it comprises an Input Memory Bank 701, a Control Unit 702, a Parallel Bank of SOYA fwlbw 704 Decoders comprising two or more SOY A fwlbw 703 decoders, an Extrinsic Memory Bank 70S, and an Extrinsic Calculation Unit 706; so that

to.

Input Memory Bank 701 stores LLR metrics, interlaces them when performing a semi-iteration, and provides the corresponding suh-block to each SOYA fwlbw 703 decoder included in the Parallel Bank of SOY A 704 Decoders;

b.

each decoder I AM A fw / bw 703 included in the Parallel Bank of Decoders I AM A fwlbw 704 calculates metrics backwards forward in odd iterations and backwards in even iterations;

C.

Control Unit 702 determines the behavior of the different units depending on the iteration or semi-iteration that is carried out at each moment;

d.

and Extrinsic Calculation Unit 1206 calculates extrinsic information using LLR metrics and a-posteriori metrics.

8. System according to the preceding claim characterized in that the SOYA fwlbw 704 Parallel Decoder Bank comprises

to.

One or more elements 1303 that apply a delay of two complete iterations (four semi-iterations) to the PMs to facilitate their exchange between decoders;

b.

and one or more records 1302 that store the state during the same iteration in which they are used.

9. System according to the preceding claim characterized in that each SOYA fwlbw 703 parallel decoder comprises:

to.

A Recursive Unit 801 that performs the following functions, both forward and backward: O) calculate the road or PM metric for each of the N states; (ii) select the surviving road and (ii) obtain the weight of this decision as the difference of the MPs between the surviving roads, using these decisions relative to the surviving roads and the corresponding weights for each state, to construct the vectors Y and W. of length N;

b.

A retarder 802 that applies to the weights W (differences between the PMs) a delay in clock cycles;

C.

A Survivor Memory Unit 803 that, based on the relative decisions it receives, travels backwards (TB) to find the ML path

d.

A Control Unit 804 that implements a finite state machine that activates the appropriate control signals for the remaining units of the SOY A 703 parallel decoder, allowing said units to perform their function in the forward or backward direction depending on the iteration in which you are;

and.

and an SOS Update Unit that. depending on the states of the ML path, it updates the weights calculated by the Recursive Unit 801 by double-traversing backwards (one TB obtains the ML path, while the other obtains the competing path) so that, at each stage in the that the bit decided for both paths differs, an update is carried out consisting of the selection of the minimum weight between the competing path and the ML paths, finally obtaining the LLR aMposter metrics in the forward or reverse directions depending on the current iteration.

10. System according to the preceding claim characterized in that Recursive Unit 801 comprises:

to.

A Connection Network 901 that delivers the appropriate PM from the previous stage to each Recursive Element 902 depending on the direction (forward or backward), implementing for this, for example, a bank of multiplexers and registers to store the previous PM;

b.

and two or more Recursive Elements 902 that (i) calculate the road or PM metric for each of the N states; (ii) select the surviving path and

(iii) obtain the weight of this decision as the difference of the MPs between the surviving roads.

eleven.

System for turbo iterative decoding of low error rate and low complexity according to any of claims 7 to 10 that implements a method according to claim 4 characterized in that the Control Unit 1304 guarantees the

exchange of states and PMs according to the method object of claim 4.

12.

System for turbo iterative decoding of low error rate and low complexity that implements a method according to claim 5 characterized in that it comprises an Input Memory Bank 1101, a Control Unit 1102, two or more SOYA fwlbw 704 Parallel Decoder Banks comprising two or more SOYA fw / bx decoders, one or more Extrinsic Memory Banks 03, one or more Extrinsic Memory Banks 1104, and two or more Extrinsic Calculation Units 706; so that

to.

the 1I0 Input Memory Bank simultaneously feeds the two or more SOYA fw / bw 703 decoders included in the two or more SOYA fwlbw 704 Decoder Parallel Banks;

b.

the at least one Extrinsic Memory Bank 1103 always deinterlaces the extrinsic information, working forward in odd iterations and backward in even iterations;

C.

the at least one Extrinsic Memory Bank 1104 always intertwines the extrinsic information, working forward in odd iterations and backward in even iterations;

d.

Control Unit 702 determines the behavior of the different units depending on the iteration or semi-iteration that is carried out at each moment;

and.

and the two or more Extrinsic Calculation Units 706 calculate the extrinsic information using LLR metrics and a-posteriori metrics.

13.

System according to the preceding claim characterized in that the SOYA fwlbw 704 Parallel Decoder Bank comprises

14.

System according to the preceding claim characterized in that each SOYA fwlbw 703 parallel decoder comprises:

to.

A Recursive Unit 801 that performs the following functions, both forward and backward: (i) calculate the road or PM metric for each of the N states; (ii) select the surviving road and (jii) obtain the weight of this decision as the difference of the MPs between the surviving roads, using these decisions relative to the surviving roads and the corresponding weights for each state, to construct the vectors Y and W, of length N;

b.

A retarder 802 that applies to the weights W (differences between the PMs) a delay in clock cycles;

C.

A Survivor Memory Unit 803 that, based on the relative decisions it receives, travels backwards (TB) to find the ML path;

d.

A Control Unit 804 that implements a finite state machine that

to.

One or more items that apply a two full iteration delay

(four semi-iterations)

to the PMs to facilitate its exchange between the

decoders;

b.

and one or more records that store the status during the same iteration in the

that are used

activates the appropriate control signals for the rest of the units of the parallel decoder SO A fw / bw 703, allowing these units to perform their function in the forward or backward direction depending on the iteration in which they are located; and. and an Update Unit 805 which, depending on the states of the ML path, updates the weights calculated by the Recursive Unit 801 by double-backing (one TB obtains the ML path, while the other obtains the competing path) of Fonna that, at each stage in which the bit decided for both paths differs, an update is carried out consisting of the selection of the minimum weight between the competing path and the ML paths, finally obtaining the LLR metrics a-posterior in the directions towards forward or backward depending on the current iteration. 15. System according to the preceding claim characterized in that Recursive Unit 801 comprises:

to.

A Connection Network 901 that delivers the appropriate PM from the previous stage to each Recursive Element 902 depending on the direction (forward or backward), implementing for this, for example, a bank of multiplexers and registers to store the previous PM;

b.

and two or more Recursive Elements 902 that (i) calculate the road or PM metric for each of the N states; (ii) select the surviving path and

(iii) obtain the weight of this decision as the difference of the MPs between the surviving roads. 16. Computer program adapted for carrying out a method according to any of claims I to 5, or comprising instructions for carrying out the steps comprised in a method according to any of claims 1 to 5. 5 17. Computer readable storage medium comprising a computer program according to the preceding claim, or instructions for making a Data processing apparatus carries out the steps comprised in a method according to any one of claims 1 to 5. 10 18. Recording carrier medium with a computer program according to claim 16 recorded on said recording carrier medium. 19. Signal carrier wave carrying signals incorporating an infonnatic program according to claim 16.