ES2348582T3 - SCALABLE BUS STRUCTURE. - Google Patents

Abstract

A communication procedure between a sending component (102) and a receiving component (104) by means of a bus (106), the bus comprising first (108, 108 ad) and second (110, 110a-b) channels, in the that each of the first and second channels comprises a plurality of subchannels (108a-d), the procedure comprising: issuing first reading and writing address information from the first channel, first reading and writing control signals , and first write data, in which the sending component issues a portion of the information of the first write address for a first (108a) of the subchannels during a first time period (401) concurrently with a portion of the write control signals for one second (108b) of the subchannels; a portion of the first writing data being issued by a third party (108c) of the subchannels during the same first time period; then issue, from the sending component on the first channel, second reading and writing address information, second reading and writing control signals, and second writing data, in which the sending component issues a portion of the information of the second write address for a first (108a) of the subchannels during a second time period (405) concurrently with a portion of the second write control signals for a second (108b) of the subchannels; and issues a portion of the second write data for the first (108a) of the subchannels during a third time period (407); transmitting a signal from the sending component to the receiving component so that the receiving component can distinguish between the read and write address information, the read and write control signals and the write data transmission on the first channel; storing the first and second write data transmission on the first channel in the receiving component based on the information of the first and second write address and the first and second write control signals; retrieve first and second read data from the receiving component based on the first and second read address information and the first and second read control signals; and emit from the receiving component the data recovered from first and second reading by the second channel.

Description

Scalable bus structure.

Countryside

The present revelation verses, in general, about of digital systems and, more specifically, about a scalable bus structure.

Background

Computers have revolutionized the industry of electronics by allowing them to be carried out quickly Sophisticated processing tasks. These sophisticated tasks can be carried out with systems that contain a high number of complex components that communicate with each other quickly and efficient using a bus. A bus is a channel or a route between components in a computer, a computer subsystem, a system computer or other electronic system.

Many buses resident in a computer have traditionally implemented as shared buses. A bus shared provides a means for any number of components communicate through a common channel or channel. In recent years, shared bus technology has been seen complemented with point-to-point switching connections. The point-to-point switching connections provide a connection Direct between two bus components while communicating between yes. Multiple direct links can be used to allow Several components communicate at once.

A common configuration for a computer It includes a microprocessor with system memory. A system bus with high bandwidth to support communications between both. In addition, there may also be a bus for peripherals used to transfer data to peripherals. In In some cases, there may also be a configuration bus, which use in order to program diverse resources. Bridges can be used to transfer data efficiently between buses with major and minor bandwidth, as well as to provide the Protocol translation required. Each of these buses has been implemented with different protocols and can have a wide variation in performance requirements between them.

The use of multiple bus structures in a Computer has provided for many years a viable solution. However, as the surface and power are presented as the fundamental considerations of circuit design integrated, it becomes increasingly desirable to reduce the complexity of bus structure

Summary

According to the present invention, a communication procedure between a sending component and a receiver component by a bus, according to claim 1, and of a processing system according to claim 12.

The procedure may also include store the writing data emitted by the first channel in the receiving component based on the address information of writing and writing control signals, retrieve the reading data of the receiving component based on information from the direction of reading and of the control signals of the reading, and issue the retrieved reading data from the receiving component on the second channel

Broadcast media can be configured to transmit a signal to the receiving component, so that the receiver component can distinguish between the information of the read and write address, read control signals and writing, and the issuance of writing data by the first channel.

The processing system may include in bus which has first and second channels. The processing system may include sending means to broadcast on the first channel read and write address information, Read and write control and write data. System processing may also include receiving means for store write data issued by the first channel in base to the information of the direction of writing and of the signals Write control, retrieve read data based on the information of the reading direction and the control signals of reading, and issue the read data retrieved by the second channel to the sending component. The issuing media may include, in addition, means for transmitting a signal to the receiving means, of so that the receiving media can distinguish between the Read and write address information, signals Read and write control and write data issued by The first channel.

It is understood that other embodiments of the present invention will become immediately apparent to people versed in the art from the following description detailed, in which various are shown and described embodiments of the invention by way of illustration. How I know you will appreciate, the invention is susceptible to other embodiments different, and its various details are subject to change in various different aspects, all without departing from the spirit and the scope of the present invention. Consequently, you must be considered that the drawings and the detailed description have illustrative and non-restrictive nature.

Brief description of the drawings

Aspects of the present invention are they illustrate by way of example and not by way of limitation in attached drawings, in which:

Fig. 1 is a conceptual block diagram which illustrates an example of a point-to-point connection on a bus two channels between two components in a system of processing

Fig. 2 is a schedule showing a read and write operation between two components in a system processing that has a point-to-point connection on a bus two channels;

Fig. 3 is a conceptual block diagram which illustrates an example of a point-to-point connection on a bus two high performance channels between two components in a system of processing;

Fig. 4 is a conceptual block diagram illustrating the time division multiplexed nature of high performance bus of Fig. 3;

Fig. 5 is a conceptual block diagram which illustrates an example of a point-to-point connection on a bus two low bandwidth channels between two components in one processing system;

Fig. 6 is a conceptual block diagram illustrating the time division multiplexed nature of low bandwidth bus of Fig. 5; Y

Fig. 7 is a conceptual block diagram illustrating an example of a point-to-point connection between a high performance component and a low width component of band by means of a bridge.

Detailed description

The detailed description set forth in what still in relation to the attached drawings is presented as a description of various embodiments of the present invention, and not it is contemplated that it represents the only embodiments in which The present invention can be practiced. The description Detailed includes specific details in order to provide a thorough understanding of the present invention. But nevertheless, it will be apparent to those skilled in the art that the The present invention can be practiced without these details specific. In some cases, they are shown in the form of a diagram of well-known structures and components blocks to avoid preventing See clearly the concepts of the present invention. Acronyms and other descriptive terminology can simply be used by comfort and clarity, and are not intended to limit the scope of invention.

Various components in a system of Processing can communicate through a bus. The bus can be scalable, in terms of the width and frequency of the clock to support the bandwidth requirements of the various components. The bus can also use an architecture and a Common signaling protocol for all configurations scalable This can be achieved by reducing the protocol of bus signaling only to the necessary signals either for transmit or to receive information.

The bus can be configured with a "channel of transmission "which provides a generic means to broadcast information from a sending component to a receiving component using the same signaling protocol multiplexed by time division A "reception channel" can also use the same signaling protocol to issue information from the receiving component to the sending component.

Fig. 1 is a conceptual block diagram which illustrates this fundamental concept. A point connection is shown ready on a bus between two components in a system processing The processing system 100 may be a collection of components that cooperate to carry out one or more processing functions Typically, the processing system it will be a computer, or it will be resident in a computer, and it will be able to process, retrieve and store information. System Processing can be a dedicated system. Alternatively, the processing system can be incorporated into any device, including, by way of example, a mobile phone.

In an embodiment of system 100 of processing, bus 106 is a dedicated bus between the component sender 102 and the receiving component. In another embodiment of the system 100, the sending component 102 communicates with the receiver component 104 with a point-to-point connection via the bus 106 by means of a bus interconnection (not shown). Further, as will be immediately captured by those skilled in the art, the inventive aspects described in this disclosure are not limited to a dedicated bus or point-to-point switching connection point, but can be applied to any type of technology of buses, including, by way of example, a shared bus.

The emitting component 102 can be any type of bus management component, including, by way of example, a microprocessor, a digital signal processor (DSP), a direct memory access controller, a bridge, a programmable logic component, a discrete door or a logic of transistor, or any other processing component of the information.

The receiving component 104 can be any storage component, including, by way of example, registers, memory, a bridge or any other component capable of retrieve and store information. The storage capacity in each address location of the receiving component may vary depending on the particular application and the limitations of the global design For the purpose of the explanation, the receiver component with a storage capacity of 1 byte per address location

The emitting component 102 can read from receiver component 104 and write on it. In the case where the sender component 102 writes to receiver component 104, the issuer component can issue an address location, the appropriate control signals, and the payload to the component receiver 104 on transmission channel 108. The "payload" refers to the data associated with a particular operation of reading or writing, and in this case with an operation of writing.

Control signals may include transfer qualifiers. The expression "qualifier of transfer "refers to a parameter that describes an attribute of a read operation, a write operation or another bus related operation. In this case, the qualifiers of transfer may include a "signal with the size of the load useful "to indicate the number of bytes of data contained in the Useful load. If the payload is multiple bytes, then the receiver component 104 can store the payload in a block sequential address locations, starting with the location of the address issued by transmission channel 108. By way of example, if the sending device 102 issues a location of address 100_ {HEX} followed by a payload of 4 bytes, the receiver component 104 can write the payload in a block of sequential address locations starting at 100_ {HEX} and ending in 103_ {HEX}.

Control signals may also include write byte enablers. "Byte enablers write "can be used to indicate which byte lane is will use on the transmission channel 108 to emit the payload for A write operation. As an example, an issue of a 2-byte payload on a 32-byte transmission channel 108 You can use 2 of the 4 byte lanes. The byte enablers Write can be used to indicate the receiving component 104 which of the two byte lanes of the transmission channel 108 is will use to issue the payload.

In the case where the emitting component 102 read from receiver component 104, address location and appropriate transfer qualifiers may be the only information that needs to be broadcast on transmission channel 108. Transfer qualifiers may include a signal with the payload size to indicate the number of bytes of data contents in the payload. The receiving component 104 can give acknowledgment of the broadcast and send the payload through the receiving channel 110. If the payload is multiple bytes, then the component receiver 104 can read the payload of a block of locations of sequential address that begins with the address location broadcast on transmission channel 108. By way of example, if the emitting device 102 issues an address location 200_ {HEX} and requests a payload of 4 bytes, the receiving component 104 you can recover the payload of a block of locations from sequential address starting at 200_ {HEX} and ending at 203_ {HEX}.

In the realization of the processing system described so far, the emitting component 102 has control total of the transmission channel 108 and can emit one or more address locations with their associated control signals before of an active write operation, during the same or with subsequent to it. In addition, channels 108 and 110 of transmission and reception are totally independent and, for this, the emission of address locations, of control signals and write data by the sending component can coincide with the emission of reading data by the receiver component 104. "Writing data" refers to data issued by the issuing component 102, and "data from read "refers to data read from the receiving component 104 and broadcast on the receiving channel 110.

An addressing plan can be used implicit to control the sequence of data operations of reading and writing on channels 108 and 110 of transmission and reception. By way of example, if the sending component 102 starts multiple write operations issuing a series of address locations with the appropriate control signals by the transmission channel 108, the sending component 102 will emit the payload for each write operation with the same sequence where address locations are issued. Similarly, if the sending component 102 initiates multiple read operations issuing a series of address locations with the signals from appropriate control, receiver component 104 will recover the load useful for each read operation with the same sequence in which Receive address locations.

"Transfer tags" can be used as an alternative to this implicit addressing plan. He sender component 102 can assign a transfer label to Each read and write operation. Transfer label may be included in the transfer qualifiers issued on transmission channel 108. In the case of an operation of writing, the sending component 102 can send the label of transfer with payload, and receiver component 104 can use the transfer label retrieved from the qualifiers of transfer to identify the payload. In the case of a read operation, receiver component 104 can send the tag retrieved from transfer with payload, and the issuer component can use the transfer tag to Identify the payload.

The various concepts described so far They can be implemented using any number of protocols. In The detailed description that follows will present an example of a bus protocol This bus protocol is presented to illustrate the inventive aspects of a processing system, with the understanding that such inventive aspects can be used with Any suitable protocol. Table 1 shows the basic protocol signaling for the transmission channel. Expert people in the art they will be able to easily vary and / or add signals to this protocol in the actual implementation of the bus structure described in this document.

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TABLE 1

one

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As shown in Table 2 below, the same signaling protocol can be used for the channel reception.

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TABLE 2

2

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Table 3 shows the definition of the Type field, used in this signaling protocol.

TABLE 3

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3

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Table 4 shows the definition of the signals Valid and Transfer request in this protocol signaling.

TABLE 4

5

Fig. 2 is a schedule showing a read and write operation on a transmission channel of 32 bits and on a 32-bit reception channel. A watch can be used 202 of the system to synchronize communications between the sender component and receiver component. The system clock 202 It is shown with eleven clock cycles, being numbered sequentially each cycle for the sake of simplicity of Explanation.

A write operation can be initiated by the emitting component during the second clock cycle 203. This can be achieved by giving a positive value to the valid 204 signal and setting Type 206 field to indicate a broadcast of a location of address for a write operation. The location of the address can also be issued by transmission channel 208 to the receiving component. In response to this issue, the component receiver stores the address location in its queue addresses.

Issuing address location can be followed by a control signal issued for the operation of writing in the third clock cycle 205. The emitting component can alert the receiving component of the signal emission of control while maintaining the positive value of the signal Valid 204 and appropriately changing the Type 206 field. The issuance of the control signal can include transfer qualifiers and the write byte enablers for the operation of writing. In this case, transfer qualifiers can include a signal with the size of the payload indicating a 8 bytes payload. The write byte enablers may indicate that the 8-byte payload will be transmitted by all byte lanes of Transmission Channel 208. He receiver component can determine from this information that the emission of the payload will be issued in two cycles of watch.

The first 4 bytes of the payload for the write operation can be issued by Channel 208 of Transmission during the fourth clock cycle 207. The component sender can alert the receiving component of the emitted payload maintaining the positive value of the valid signal 204 and changing the Type 206 field to indicate a payload emission. In absence of transfer labels, the receiving component recognizes the write data as the first 4 bytes of the payload in based on the implicit addressing plan presented above. In response to this broadcast, the first 4 bytes of the payload They can be written to the receiving component.

In the next clock cycle 209, the signal Valid 204 and the Type 206 field remain unchanged while the next 4 bytes of the payload are emitted by Channel 208 of Transmission. However, the receiving component has changed to negative the value of the Transfer Request 210 signal, indicating that you cannot accept the broadcast. The emitting component can detect that the Transfer Request 210 signal does not have positive value at the end of this fifth cycle 209 clock, and repeat the emission of the second 4 bytes of the payload in the following 211 clock cycle. The issuing component may continue issuing the seconds 4 bytes of the payload in each clock cycle until the emitting component detects the positive value of the Request signal Transfer 210 from the receiving component. In this In this case, only repeated issuance is required. The second 4 bytes of the payload can be written to the receiving component in the sixth clock cycle. At the end of the sixth clock cycle 211, the second component detects the positive value of the signal Transfer Request 210 and determines that the issuance has been received

A read operation can be initiated by the emitting component during the seventh clock cycle 213. This can be achieved by giving a positive value to the valid 204 signal and setting Type 206 field to signal the issuance of a location of address for a read operation. Address location It can then be broadcast on Transmission Channel 208 at receiving component In response to this issue, the component receiver stores the address location in its queue addresses.

Issuing address location can be followed by an emission of a control signal for the reading operation in the eighth clock cycle 215. The component sender can alert the receiving component of the emission of the control signal maintaining a positive signal value Valid 204 and changing the Type 206 field appropriately. The emision of the control signal may include transfer qualifiers for the read operation. In this case, the qualifiers of transfer can include a signal with the size of the load useful that indicates a payload of 4 bytes. The receiving component You can determine from this information that the issuance of the Payload can be emitted in a clock cycle.

Due to the latency of the reading of the receiver component, a delay of several may be experienced clock cycles before read data is available. A Once the 4-byte payload is available, the component receiver can give a positive value to the valid 212 signal and change the Type 214 field to indicate a payload emission by the Reception Channel 216. Since the sending component gives a value Positive to the Transfer Request signal 218, the issuance of the Payload can be completed in a clock cycle. The component receiver detects the positive value of the signal Request for Transfer 218 at the end of the tenth clock cycle 219 and, with This determines that the issuance of the payload was successful.

Fig. 3 is a conceptual block diagram illustrating a point-to-point connection between two components on a high performance bus. The high performance bus transmission and reception channels 108 and 110 can be implemented as multiple subchannels, each subchannel having a width of 32 bits. In actual embodiments, the number of subchannels and the width of each subchannel may vary depending on the performance requirements of the particular application. In this example, the transmission channel includes 4 32-bit 108a-108d subchannels, and the reception channel includes 2 32-bit 110a-110b subchannels. This embodiment may be suitable, by way of example, for a system bus on a computer, or on any other high performance bus. The term "subchannel" refers to a group of cables or conductors that can be controlled independently of other cables or conductors in the channel. This means that each subchannel can be equipped with an independent signaling capability.
tooth.

This high performance bus can be used by the emitting component 102 to simultaneously issue several combinations of information As an example, the component sender can issue a 32-bit address location, signals 32-bit control that includes transfer qualifiers and write byte enablers, and 8 bytes of write data within a single clock cycle. In the case of receiver channel 110, 8 bytes of read data can be output from the component receiver 104 to transmitter component 102 within a single cycle of watch.

Since the various embodiments of the system processing described above do not include any other type of information transmission through reception channel 110 other than reading data, there is no need for subchannels. May implement a single 64-bit reception channel to reduce signaling requirements (i.e., without subchannels). Without However, in some embodiments of the processing system, the Type field of the signaling protocol can be extended to give place to issue diverse information. As an example, a "write response" can be issued on channel 110 of reception to signal to the sending component that data has been written in receiver component 104. The write response could broadcast on the receiving channel 110 using one of the Type fields reserved. In that case, it may be useful to have two 32-bit subchannels independently controlled so that read data and write response can be issued simultaneously on the receiving channel 110. With 2 subchannels of 32 bits, it is then possible to simultaneously issue 4 bytes of read data, 2 bytes of read data and a response of 32-bit write, or 2 32-bit write responses. By On the other hand, a single 64-bit reception channel 110 may be capable only of supporting reading data or responses of writing in any given clock cycle.

Similarly, the transmission channel can also be extended to include the issuance of other types of information that is common in many bus protocols, such as standard instructions. As an example, it is possible that a microprocessor connected to a bus needs to issue information to other system components, such as a TAB Sync instruction or a TAB invalidation instruction. These instructions can be classified in the Type field without signaling additional.

Fig. 4 is a block diagram illustrating the time division multiplexed nature of a channel 108 of Transmission with 4 subchannels 108a-108d. In this For example, the emission of a full payload of 8 can be completed bytes for the 4 subchannels within a single clock cycle. Plus specifically, during the first clock cycle 401, the component sender can issue a 32-bit address location by the first subchannel 108a and 32 bits of control signals for the second subchannel 108b for the first write operation. The component emitter can also emit, during the same clock cycle, the 4 higher order bytes of the payload by the third subchannel 108c and the 4 bytes of lower order of the payload per quarter subchannel 108d. Each subchannel 108a-108d can be equipped with independent signaling capability and, in the case described above, positive value can be given to the signal Valid with the appropriate Type field for each subchannel.

Having a positive value the Request for Transfer for each subchannel 108a-108d at the end of the first clock cycle 401, two operations of reading by the emitting component during the second cycle 403 clock This can be achieved by issuing an address location 32 bits for the first subchannel 108a and 32 bits of signals control by the second subchannel 108b for the first operation of reading, with appropriate signaling for each subchannel 108a-108b. The emitting component can also emit a 32-bit address location by the third subchannel 108c and 32 bits of control signals through the fourth subchannel 108d for the second read operation, again with the appropriate signaling for each subchannel 108c-108d.

Having a positive value the Request for Transfer for each subchannel 108a-108d at the end of the second clock cycle, a second operation can be started writing and a third reading operation by the emitting component during the third clock cycle 405. This can achieved by issuing a 32-bit address location by the first subchannel 108a and 32 bits of control signals for the second subchannel 108b for the second write operation, with the appropriate signaling for each subchannel 108a-108b. The sending component can also issue an address location 32-bit by the third subchannel 108c and 32 bits of signals control by the fourth subchannel 108d for the third operation of reading, again with the appropriate signaling for each subchannel 108c-108d.

In this example, at the end of the third cycle 405 clock, the Transfer Request signal has a positive value in the first and second subchannels 108a and 108b, but not in the third and fourth subchannels 108c and 108d. The sending component can detect that the Transfer Request of the third subchannels and fourth 108c and 108d has no positive value and, therefore, determine that address location and control signals should reissue It shows that the location of the address and the control signals of the third read operation are emitted during the fourth cycle 407 clock by the third subchannels and fourth 108c and 108d, respectively, but can be issued again by any subchannel during any cycle subsequent clock.

In the previous example, the receiving component is configured either to accept or to reject both the address location as the third control signals reading operation However, in some embodiments of the processing system, the receiving component may be set to accept the address location and reject the control signals, or vice versa, for the same operation of reading or writing Similarly, the receiving component can be configured to accept or reject individually higher or lower order bytes of the payload. In this case, there must be a way to link a new broadcast, say, of the control signals of the third read operation with the location of the address of the same operation previously issued. This can be achieved in several ways. As an example, once that an address location is sent for an operation of read or write and that the receiving component acknowledges, it is not issues the address of the next read or write operation until the control signals associated with the current request Read or write operation are received and are subject to acknowledgment by the receiving component.

During the fourth clock cycle 407, the emitter component can emit the payload for the second write operation and try to start a second time a Third reading operation. This can be achieved by issuing the 4 higher order bytes of the payload for the first subchannel 108a and the 4 bytes of lower order of the payload per second subchannel 108b for the second write operation, with the appropriate signaling in each subchannel 108a-108b. The sending component can also reissue the location of the 32-bit address by the third subchannel 108c and 32 bits of control signals by the fourth subchannel 108d for the third reading operation

In this embodiment of a high bus performance, sorting of read / write requests It can be implied by position. The sending component can issue the first read / write request for the first subchannel 108a, the second read / write request by the second subchannel 108b, the third read / write request by the third subchannel 108c and the fourth read / write request for the fourth subchannel 108d. The receiving component can process requests based on this implicit positioning for Maintain sequential coherence. By way of example, if address locations for read and write operations started during the third clock cycle 405 are the same, the receiver component can wait until data is written issued by subchannels 108a and 108b first and second during the fourth clock cycle 407 at address location before provide the newly written data in this location of address to the reception channel for transmission to the component transmitter.

In the realization of the high performance bus described above, it is not necessary that the data of deed are issued immediately after the issuance of the write operation request (that is, the location of the address and control signals). Other ones can be inserted requests for a read operation and / or further instructions priority with the writing data broadcast on channel 108 of transmission. However, if the sending component interleaves the requests for a read operation and / or instructions with the write data, then the sending component should be configured with a steering recoil mechanism.

As described above in relation to Fig. 2, the sending component samples the Request signal 210 of Transfer following an emission on Channel 208 of Transmission. If the sending component fails to detect a value Positive of the 210 Transfer Request signal, you can then repeat the broadcast during the next clock cycle. The broadcast can be repeated in each clock cycle until the emitting component detects a positive value of signal 210 of Transfer request. A problem may arise when it is full the address queue during a request for a transaction reading and therefore cannot accept more locations from address. At the same time, the receiving component needs to complete the write pending operation to free up queue space addresses. In this case, it is said that the receiving component is interlocked

The steering recoil mechanism is designed to allow the write operation to complete when the receiving component is interlocked. This can achieved by limiting the number of repeated emissions by the issuer component in relation to a request for a transaction of reading. If the receiving component does not acknowledge receipt of a request for a read operation with a Request Request signal Transfer within a certain number of clock cycles, then the issuing component can abort the request by sending the remaining write data instead of the address location for the current request for a read operation. If there is not one pending write operation that needs to be completed, then the issuance of the request for a reading operation The broadcast may continue until the Receiving component acknowledges the request.

The steering recoil mechanism may not be necessary if the issuing component does not insert requests from A read operation with write data. That is, if the address location of a write operation is followed immediately by control signals, and then it is followed immediately by writing data, then the component receiver will never be interlocked. However, this may degrade the performance of the reception channel, because the component emitter may not be able to maintain duct adequacy of read operations to fully utilize bandwidth of the reception channel.

Fig. 5 is a conceptual block diagram illustrating a point-to-point connection between two components in a low bandwidth bus The low bandwidth bus can be implemented with a single transmission channel 108 and a single channel 110 reception that require less signals and give as result in less energy dissipation. In the example shown in Fig. 5, the emitting component 102 can issue information to the receiver component 104 on a 32-bit transmission channel 108, and the receiving component 104 can issue return information to the transmitter component 102 through a 32-bit reception channel 110. From alternatively, this same architecture of bus with narrower bus widths.

Although this configuration still allows transmitting and receiving channels 108 and 110 emit information simultaneously, each read and write operation can now require multiple clock cycles, as shown in the block diagram of Fig. 6. In this example, two are used clock cycles to start a read operation. Plus specifically, an address location of 32 may be issued bits on the transmission channel 108 in the first cycle 601 of clock, followed by 32 bits of control signals in the next 603 clock cycle. A payload of 4 bytes can be read from receiving component in response to this request and issue by the reception channel 110 in the third clock cycle 605.

Concurrently with the issuance of the cargo useful by the receiving channel, the sending component can start A write operation. In this case, the write operation Use three clock cycles. In the third clock cycle 605, the sender component issues a 32-bit address location by the Transmission channel 108, followed by 32 bits of control signals in the fourth clock cycle 607, followed by a payload of 4 bytes in the fifth clock cycle 609.

In many processing systems, some devices may require a wide interconnection of band, while others may work sufficiently with an interconnection with a lower bandwidth. Using a Escabre bus architecture, the implementation of bridges can be implemented with a common signaling protocol. Fig. 7 is a conceptual block diagram illustrating a point to connection point between two components by means of a bridge. The 702 bridge can be used to interconnect a transmitter component 102 connected to a high performance bus with a receiver component 104 connected to a bus with low side width. The high performance bus can be equipped with a transmission channel 108 that has 4 subchannels 108a-108d 32-bit and one receiving channel 110 which has 2 channels 110a and 110b 32-bit reception. The bus with low bandwidth can be provided with a single channel 108 'of 32-bit transmission and single channel 110 '32-bit reception bits

In this example, an operation can be completed write between the sending device 102 and the bridge 702 inside of a single clock cycle using the 4 subchannels 108a-108d high performance bus transmission to issue the address location, control signals and an 8-byte payload, as previously described in relationship with Figures 3 and 4. Bridge 702 can introduce the information in the buffer and issue it to the component receiver 104 on channel 108 '32-bit transmission of the bus low bandwidth in 4 clock cycles, as described above in relation to Figures 5 and 6.

In the case of a read operation, the sender component 102 can issue an address location and control signals to bridge 702 by 2 transmission subchannels of the High performance bus within a single clock cycle. The bridge 702 you can enter this information in buffer and emit it to the receiver component 104 on the transmission channel 108 ' 32-bit in two clock cycles. It can then be issued an 8-byte payload from receiver component 104 to the bridge 702 through the 32 '32-bit reception channel 110, enter in buffer memory on bridge 702 and then issued by the bridge 702 to the emitter component 102 by the two subchannels 110a and 110b reception in a single clock cycle.

The various illustrative logical blocks, modules and circuits described in relation to the embodiments disclosed in this document can be implemented or be performed with a general purpose processor, a processor digital signals (DSP), an integrated circuit for applications specific (ASIC), an array of programmable field doors (FPGA) or another programmable logic component, a discrete gate or a transistor logic, discrete physical components or any combination thereof designed to carry out the functions described in this document. A use processor general can be a microprocessor, but, alternatively, the processor can be any conventional processor, controller, microcontroller or state machine. You can also implement a processor as a combination of computer components, by example a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in union with a DSP core or any other configuration of that kind.

The procedures or algorithms described in connection with the embodiments disclosed herein can be embodied directly in hardware , in a software module executed by a processor or in a combination of both. A software module can reside in RAM, in flash memory, in ROM, in EPROM, in EEPROM, in registers, on a hard disk, on a removable disk, such as a CD-ROM, or in any other way of storage medium known in the art. A storage medium can be connected to the processor, so that the processor can read information from the storage medium and write information to it. Alternatively, the storage medium can be an integral part of the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in the sending component and / or in the receiver, or elsewhere. Alternatively, the processor and the storage medium may reside in discrete components of the sending and / or receiver component, or elsewhere.

Claims (22)

1. A communication procedure between a emitting component (102) and a receiving component (104) by means of a bus (106), the bus comprising channels first (108, 108 a-d) and second (110, 110a-b), in the that each of the first and second channels comprises a plurality of subchannels (108a-d), comprising the process:

issue from sender component by the first channel address information of first reading and writing, first reading control signals and writing, and first writing data,

in which the issuer component issues a portion of the information from the first write address for a first (108a) of the subchannels during a first time period (401) concurrently with a portion of the write control signals for a second (108b) of the subchannels; issuing a portion of the data from first writing by a third party (108c) of the subchannels during the same first time period;

to issue then, from the sending component on the first channel Second reading and writing address information, signals second reading and writing control, and second data writing,

in which the issuer component issues a portion of the information from the second write address for a first (108a) of the subchannels for a second time period (405) so concurrent with a portion of the second control signals writing for one second (108b) of the subchannels; and issues a portion of the second write data by the first (108a) of the subchannels during a third time period (407);

transmit a signal from the sending component to the receiving component in such a way that the receiving component can distinguish between the information in read and write address, control signals of read and write and write data issuance for the first channel;

store the first and second write data broadcast on the first channel in the receiving component based on the address information first and second write and control signals of first and second writing; retrieve read data first and second of the receiving component based on information from first and second reading direction and to the control signals of first and second reading; Y

issue from receiver component the data retrieved from read first and Second by the second channel.

2. The method of claim 1 in the that the first time period is a clock cycle, the third time period is a clock cycle that immediately follows the Second time period. 3. The method of claim 1 in the that the second (108b) of the subchannels is operable to carry a second portion of the second write data during the third time period (407). 4. The method of claim 2 in the that the read and write signals comprise a plurality of transfer qualifiers and byte enablers of writing. 5. The method of claim 1 in the that the writing data comprises a plurality of charges useful and in which the emitting component (102) emits a portion of read and write address information between a portion First and second of one of the payloads. 6. The method of claim 1 which It also includes the transmission of a signal from the component receiver to the sending component to acknowledge emissions through the first channel (108, 108 a-d). 7. The method of claim 6 which it also includes the repetition of an emission of the same portion of the information of the direction of reading or writing, of the read or write control signals, or data from writing in response to signal transmission from the receiving component (104) to the sending component (102). 8. The method of claim 7 in the that the writing data comprises a plurality of charges useful and in which the same portion of the read address information or control signals of reading during a period following the issuance of a portion of the write address information associated with one of the payloads, but before said one of the payloads is completely emitted to the receiving component (104), the procedure in addition suspend repeated issuance at the end of temporary period, complete the issuance of said one of the charges useful, and repeat the issuance of the same portion of the information of the read address or of the read control signals following the termination of the issuance of said one of the charges tools. 9. The method of claim 1 which It also includes the transmission of a signal from the component receiver (104) to the sending component (102) to indicate when The receiving component is broadcasting the read data. 10. The method of claim 9 which It also includes the broadcast on the second channel (110, 110a-b) instruction from the component receiver (104), and signal transmission from the component receiver to the sending component (102), such that the emitter component can distinguish between reading data and instructions. 11. The method of claim 10 in which the second channel comprises a plurality of subchannels (110a-b), issuing a first (110a) of the subchannels a portion of the reading data during a period temporarily concurrently with the issuance of a portion of the instructions for one second (110b) of the subchannels during the Same time period. 12. A processing system (100) that understands:

a bus (106) that It has first (108, 108 a-d) and second (110, 110a-b), in which each of the channels first and second comprises a plurality of subchannels (108a-d);

means of broadcast to broadcast address information from the first channel first and second read and write, first control signals and second reading and writing, and second data writing,

in which the broadcast media are configured to issue a portion of the first write address information for a first (108a) of the subchannels during a first time period (401) of concurrently with a portion of the control signals of writing for one second (108b) of the subchannels; issuing a portion of the first write data by another (108c) of the subchannels during the same first time period;

issue a portion of the second write address information by the first (108a) of the subchannels during a second period temporary (405) concurrently with a portion of the signals second write control for the second (108b) of the subchannels; and issue a portion of the second write data for the first (108a) of the subchannels during a third period temporary (407); Y

means of reception to store the first write data broadcast and second by the first channel based on the address information first and second write and control signals of First and second writing, retrieving data from first reading and second based on the first read address information and second and to the first and second read control signals; Y issue to the sending media the data recovered from first reading and second through the second channel;

in which the emitting means further comprise means for transmitting a signal to the receiving media, such that the receiving media can distinguish between reading address information and writing, read and write control signals and data of writing issued by the first channel.

13. The processing system of the claim 12 wherein the first time period is a cycle clock, the second time period is a clock cycle that follows immediately to the first time period. 14. The processing system (100) of the claim 12 wherein the emission means (104) are also configured to issue a second portion of the data of writing for the second (108b) of the subchannels during the Second time period (407). 15. The processing system (100) of the claim 12 wherein the read and write signals they comprise a plurality of transfer qualifiers and of write byte enablers. 16. The processing system (100) of the claim 12 wherein the writing data comprises a plurality of payloads and in which the emitting means (102) are also configured to issue a portion of the read and write address information between a portion First and second of one of the payloads. 17. The processing system (100) of the claim 12 wherein the receiving means (104) are also configured to transmit a signal to the media emitters (102) to acknowledge emissions through the first channel (108, 108 a-d). 18. The processing system (100) of the claim 17 wherein the emitting means (102) are also configured to repeat an emission of the same portion of the information of the direction of reading or writing, of the read or write control signals, or data from writing if no acknowledgment of such broadcast is received from the media receivers (104).

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19. The processing system (100) of the claim 17 wherein the emitting means (102) comprise, In addition, a steering recoil mechanism. 20. The processing system (100) of the claim 12 wherein the receiving means (104) are also configured to transmit a signal to the media emitters (102) to indicate when the receiving means are issuing the reading data. 21. The processing system (100) of the claim 20 wherein the receiving means (104) are also configured to issue instructions on the second channel and to transmit signals to the sending means (102), in such a way that the sending media can distinguish between reading data And the instructions. 22. The processing system (100) of the claim 21 wherein the second channel (110, 110a-b) comprises a plurality of subchannels (100a-b), the receiving media being configured (104), in addition, to issue a portion of the reading data by a first (110a) of the subchannels during a temporary period of concurrently with the issuance of a portion of the instructions for one second (110b) of the subchannels during the same period temporary.