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EP4356417A1 - Élément de bit quantique - Google Patents

Élément de bit quantique

Info

Publication number
EP4356417A1
EP4356417A1 EP21733936.5A EP21733936A EP4356417A1 EP 4356417 A1 EP4356417 A1 EP 4356417A1 EP 21733936 A EP21733936 A EP 21733936A EP 4356417 A1 EP4356417 A1 EP 4356417A1
Authority
EP
European Patent Office
Prior art keywords
quantum well
well structure
qubit
layer
backgate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP21733936.5A
Other languages
German (de)
English (en)
Inventor
Matthias KÜNNE
Lars SCHREIBER
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rheinisch Westlische Technische Hochschuke RWTH
Original Assignee
Rheinisch Westlische Technische Hochschuke RWTH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rheinisch Westlische Technische Hochschuke RWTH filed Critical Rheinisch Westlische Technische Hochschuke RWTH
Publication of EP4356417A1 publication Critical patent/EP4356417A1/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/383—Quantum effect devices, e.g. of devices using quantum reflection, diffraction or interference effects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/402—Single electron transistors; Coulomb blockade transistors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/40—Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/383—Quantum effect devices, e.g. of devices using quantum reflection, diffraction or interference effects
    • H10D48/3835—Semiconductor qubit devices comprising a plurality of quantum mechanically interacting semiconductor quantum dots, e.g. Loss-DiVincenzo spin qubits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H10D62/812—Single quantum well structures
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures

Definitions

  • the invention relates to a qubit element and a use of the qubit element and a production method for the qubit element.
  • the spin of a charge carrier can be used as qubits. However, this requires access to the charge carrier in such a way that its spin can be determined and influenced. For this purpose it is known to localize charge carriers in quantum points. However, semiconductor structures known for this do not allow satisfactory control over the spin.
  • the object of the present invention is, based on the described prior art, to present a qubit element with which the spin of a charge carrier can be controlled particularly well. In addition, a corresponding use and a manufacturing process are to be presented.
  • a qubit element which comprises:
  • ⁇ an electrode arrangement which is set up to restrict movement of a charge carrier in the quantum well in and against a second direction and in and against a third direction in order to form a quantum dot, the first direction, the second direction and the third direction each because pairs are perpendicular to each other,
  • ⁇ a base layer formed from strained silicon, which is adjacent to the quantum well structure in the opposite direction to the first direction.
  • qubit is used here - as is common practice - for the abstract concept of a quantum mechanical two-state system which can be used for quantum computing.
  • a qubit element here - to distinguish it from the abstract concept - is to be understood as a device with which a qubit can be realized.
  • the term “qubit element” the term “device for realizing a qubit” can therefore also be used.
  • the qubit element is a semiconductor structure.
  • the term “semiconductor structure for realizing a qubit” can also be used in this case.
  • the qubit can be part of a device which has a multiplicity of qubit elements designed as described. Such a device is also part of the invention.
  • a quantum dot can be formed in the qubit element.
  • the movement of a charge carrier in the quantum dot is restricted in all directions to such an extent that the charge carrier can only assume discrete energy states.
  • a quantum dot can be said to be zero-dimensional.
  • the charge carrier can be an electron or a hole.
  • a charge carrier in a quantum dot can be used to implement a qubit.
  • the spin of a charge carrier in a quantum dot can be used to create a qubit.
  • the qubit element is described using a coordinate system having a first direction, a second direction and a third direction, with the three directions being orthogonal in pairs.
  • the qubit element has a quantum well structure.
  • a quantum well is formed in the quantum well structure.
  • a quantum well is a potential curve that restricts the movement of a charge carrier in one direction.
  • the quantum well of the quantum well structure is formed along the first direction. This means that the movement of a charge carrier in the quantum well in and against the first direction is confined to the quantum well.
  • the potential that forms the quantum well can be the valence band or the conduction band of a semiconductor layer structure.
  • the movement of a charge carrier in and against the first direction can be restricted by the quantum well structure.
  • the movement of the charge carrier in and against the other two directions can be limited by electric fields that can be generated by applying electric voltages to electrodes (which can also be referred to as "gates").
  • the qubit element has an electrode arrangement for this purpose This is designed in such a way that the movement of the charge carrier in the quantum well can be restricted in and against the second and third direction.
  • the electrode array is preferably spaced from the quantum well structure in the first direction. If the first direction points from bottom to top, the electrode arrangement is therefore above the quantum well structure.
  • the electrode arrangement is preferably electrically isolated from the quantum well structure and in this respect is not directly adjacent to the quantum well structure.
  • the electrode array is spaced from the quantum well structure by an oxide layer and/or a cap layer.
  • the oxide layer is used for electrical insulation, the top layer for adhesion of the electrode arrangement on the oxide layer.
  • the electrode arrangement is preferably at a distance of 10 to 200 nm [nanometers] from the edge of the quantum well structure. This refers to the edge of the quantum well structure closest to the electrode array.
  • the quantum well structure could be grown directly on a wafer, in particular a silicon wafer. Irrespective of the lattice structure of the quantum well structure, lattice defects can occur. This applies in particular when the quantum well structure does not have silicon with the naturally occurring lattice constant on its side facing the wafer. When the first direction is from bottom to top, it refers to the bottom of the quantum well structure.
  • the advantages of the qubit element described can be used particularly well in the case that the quantum well structure has a lattice constant on its surface pointing in the opposite direction to the first direction, which deviates from the lattice constant naturally present in silicon.
  • the qubit element described can be produced in a particularly simple manner thanks to the base layer. This is especially true against a case where the quantum well structure is grown directly on a silicon wafer or on a junction layer.
  • the base layer is adjacent to the quantum well structure in the opposite direction to the first direction. If the first direction points from bottom to top, the base layer thus borders the quantum well structure at the bottom.
  • the base layer is formed from strained silicon. As is generally the case, this means that the silicon has a lattice constant that differs from that which occurs naturally. The naturally occurring lattice constant of silicon is around 0.5 nm [nanometer]. Strained silicon should be considered here as silicon whose lattice constant deviates by at least 0.2%, in particular at least 1%, from the naturally occurring value. Instead of the term "strained silicon", the expression "the base layer is formed from silicon which has a lattice constant which is at least 0.2%, in particular at least 1%, of the lattice constant naturally occurring in silicon” can also be used deviates".
  • the base layer is at most 20 nm [nanometers] thick.
  • the thickness of the base layer is the extension of the base layer in the first direction.
  • the thickness of the base layer is preferably between 1 and 10 nm [nanometers].
  • the base layer preferably has the lattice constant exhibited by the quantum well structure at the interface between the base layer and the quantum well structure. The base layer therefore goes into the quantum well structure without changing the lattice constant. As a result, there are particularly few lattice defects in the quantum well structure. This enables a particularly good control of the spin of a charge carrier in the quantum dot.
  • the qubit element further comprises an insulating layer of silicon dioxide abutting the base layer on an opposite side of the base layer from the quantum well structure.
  • the silicon dioxide layer is referred to herein as the insulating layer because the silicon dioxide can be used for electrical insulation between the base layer and another layer adjacent to the insulating layer.
  • the insulation layer can be amorphous.
  • the insulating layer preferably has a thickness in the range from 5 to 30 nm [nanometers]. The thickness of the insulation layer is the extension of the insulation layer in the first direction.
  • the quantum well structure has three layers consecutive in the first direction, of which the middle layer is formed from strained silicon and of which the two remaining layers are formed from silicon and germanium, respectively.
  • the middle layer of strained silicon has a lattice constant that deviates from the natural lattice constant of silicon.
  • the silicon of the middle layers is strained.
  • the material of the middle layer can in particular be silicon with a lattice constant which corresponds to the lattice constant of the material of the other layers. This term can be used in place of the term "strained silicon" for the middle layer material.
  • the two remaining layers are preferably formed from silicon-germanium or germanium-silicon.
  • a semiconductor material made of silicon and germanium is referred to as silicon-germanium, which has more silicon than germanium.
  • germanium-silicon is a semiconductor material that contains more germanium than silicon.
  • the material of the remaining layers of the quantum well Structure preferably has a silicon content in the range of 60 and 80% or in the range of 20 and 40%.
  • the material is Sio,yGeo, 3 or Geo,7Sio, 3 . Due to the layer sequence silicon-germanium, silicon, silicon-germanium, the conduction band forms a quantum well.
  • the spin of an electron can then be used to realize a qubit. Due to the layer sequence germanium-silicon, silicon, germanium-silicon, the valence band and the conduction band form a quantum well. This can restrict the movement of holes and/or electrons as charge carriers. The spin of an electron or hole can then be used to realize a qubit.
  • the middle layer preferably has a thickness in the range of 3 to 12 nm [nanometer].
  • the remaining layers of the quantum well structure preferably have a thickness in the range of 30 and 70 nm [nanometers]. The thickness of a layer is in each case the expansion of this layer in the first direction.
  • the qubit element further comprises a magnet which is arranged at a distance from the quantum well structure in the opposite direction to the first direction.
  • a gradient in the magnetic field of the magnet causes spin-orbit coupling of the states of the charge carrier in the quantum dot and the energy splitting of the two qubit states is individualized for each qubit in the vicinity of the magnet. This is advantageous for quantum computing.
  • one magnet can be used for multiple qubit elements.
  • the magnet is spaced from the quantum well structure in the opposite direction to the first direction. If the first direction points from bottom to top, the magnet lies below the quantum well structure and also below the base layer adjoining the quantum well structure and—if present—also below the on the base layer adjacent insulation layer.
  • the magnet is electrically isolated from the base layer, preferably by the insulating layer.
  • the magnet is provided on the opposite side of the quantum well structure from the electrode array. This places the magnet much closer to the quantum point than would be the case with a magnet placed on the same side as the electrode array. This is because the closer the magnet is to the quantum dot, the greater the influence of a magnetic field generated by a magnet on the quantum dot. The gradient of the magnetic field is decisive for the spin-orbit coupling of the charge carriers in the quantum dot. This is all the more pronounced the closer the magnet is to the quantum dot.
  • the arrangement of the magnet on the side of the quantum well structure opposite the electrode arrangement is possible in particular because of the base layer.
  • the layer of the quantum well structure facing the magnet is made of silicon-germanium, for example, a transitional layer made of silicon-germanium with a gradually decreasing proportion of germanium could also be provided between the quantum well structure and a silicon wafer.
  • the transition layer would have to have a considerable thickness, for example 1 mm [micrometer].
  • a significantly smaller distance between the magnet and the quantum dot can be realized through the base layer and the preferably provided insulating layer made of silicon dioxide.
  • the qubit element further comprises a backgate, which is arranged at a distance from the quantum well structure in the opposite direction to the first direction.
  • the backgate can be designed as a global backgate for a large number of qubit elements.
  • the charge carriers in the quantum dot can be influenced via the backgate.
  • the Fermi energy can be pushed, which can influence the occupation of the quantum dot.
  • the occupation number of the quantum dot can be adjusted independently of an electric field between the backgate and the electrode arrangement.
  • the combination of backgate and electrode arrangement results in a particularly high degree of flexibility in the design of the qubit element, especially with regard to electric field gradients in the area of the quantum dot.
  • the backgate can be designed in one piece or be composed of several ren parts. The parts of the backgate can adjoin one another or be spaced apart from one another. In the latter case one can also speak of a structured backgate.
  • the backgate Due to the comparatively short distance between the backgate and the quantum dot, a charge carrier in the quantum dot can be influenced in a particularly targeted and rapid manner.
  • the valley splitting in the quantum dot is particularly large and homogeneous, so that the operating temperature of the qubit element can be selected to be particularly high.
  • the backgate is preferably at a distance of 30 to 200 nm [nanometers] from the edge of the quantum well structure. This refers to the edge of the quantum well structure closest to the backgate.
  • the magnet it is possible to provide the magnet with no backgate or the backgate with no magnet. It is also possible to provide the backgate in addition to the magnet. In that case it is preferred that the backgate is electrically isolated from the magnet. Alternatively, it is preferred that the magnet is electrically conductively connected to the backgate. In this respect, the magnet can be understood as part of the backgate. Therefore, the embodiment of the qubit element in which the backgate is at least partially magnetized is preferred.
  • the magnet can be arranged between the insulating layer and the remaining part of the backgate.
  • the magnet is directly adjacent to the remaining part of the backgate and is therefore electrically conductively connected to the remaining part of the backgate.
  • the magnet can therefore be used on the one hand to control the magnetic field gradient for the spin create orbit coupling.
  • the magnet is part of the backgate and in this respect can contribute to the generation of an electric field.
  • the qubit element further comprises a wafer with a recess, the backgate and/or the magnet being arranged within the recess. If a backgate but no magnet is provided, the backgate is arranged in the recess. If a magnet but no backgate is provided, the magnet is arranged in the recess. If a backgate and a magnet are provided, both the backgate and the magnet are preferably arranged in the recess.
  • the wafer is preferably a silicon wafer.
  • the silicon wafer can be etched locally in such a way that the backgate and/or the magnet can be inserted into a recess in the wafer. In this way, the backgate and/or the magnet can be brought particularly close to the quantum dot.
  • the qubit element has an insulating layer made of silicon dioxide, which abuts against the base layer on a side of the base layer which is opposite to the quantum well structure.
  • the silicon dioxide also serves as an etch stop for the etching of the wafer.
  • the material of the wafer can be completely removed in the recess.
  • the recess thus extends along the first direction over the entire extent of the wafer.
  • the backgate and/or the magnet can therefore be arranged directly adjacent to the insulating layer.
  • a use of a qubit element designed as described is presented as a further aspect of the invention, with electrical voltages being applied to the electrode arrangement in such a way that a quantum dot is formed in the quantum well of the quantum well structure.
  • the qubit element is preferably used at a temperature ranging from 0.01 to 4K. This is particularly possible in a cryostat.
  • a spin of a charge carrier is used in the quantum dot to realize a qubit.
  • a method for producing a qubit element comprises: a) providing a wafer, an insulating layer of silicon dioxide on a surface of the wafer and a base layer of strained silicon adjacent to the insulating layer, b1) providing a quantum well structure adjacent to the base layer, where within the quantum well structure a quantum well is or will be formed along a first direction, b2) local etching of the wafer on a side of the wafer opposite the insulating layer, so that a recess is formed in the wafer, c) arranging a backgate and/or a magnet within according to Step b) etched recess.
  • the described advantages and features of the qubit element and the use are applicable and transferable to the method and vice versa.
  • the qubit element described can preferably be generated using the method described.
  • the method described is preferably designed to produce the qubit element described.
  • Steps b1) and b2) can be carried out in any order.
  • Step b1) preferably takes place before step b2).
  • step a) a wafer, an insulating layer of silicon dioxide on a surface of the wafer and a base layer of strained silicon adjacent to the insulating layer are provided.
  • Providing here means that each wafer provided with the insulating layer and the base layer of strained silicon is obtained from a supplier or that one is produced as part of the process.
  • a wafer with an insulating layer and a base layer of strained silicon can be obtained using the method, also referred to as the "Jülich process", which is described in US Pat. No. 6,464,780.
  • the content of this document is considered to be part of the invention which is incorporated herein by reference in its entirety.
  • an auxiliary layer structure is grown from a Si substrate, an adjacent SiGe layer, and an Si cap layer adjacent to the SiGe layer.
  • the Si top layer becomes the base layer in the course of the process, i.e. has the same thickness as the base layer. This is preferably at most 20 nm [nanometers], in particular between 1 and 10 nm. In this arrangement, the SiGe is strained.
  • the SiGe relaxes and retains its natural lattice constant.
  • This continues on the comparatively thin Si cover layer, so that the silicon in the Si cover layer becomes strained silicon.
  • This is the base layer.
  • the described auxiliary layer structure is placed "upside down" on the insulation layer by wafer bonding.
  • the SiGe layer and the Si substrate of the layer structure can be removed by selective etching. This leaves only the Base layer on the insulation layer.
  • the quantum well structure can be grown on the base layer, for example by means of Molecular Beam Epitaxy (MBE. This takes place in step b1), in which the quantum well structure is provided on the insulation layer.
  • MBE Molecular Beam Epitaxy
  • step b2) the wafer is etched locally. This is done from the back of the wafer insofar as the etching begins on the side of the wafer opposite the insulating layer.
  • the material of the wafer is preferably removed in the area of the recess to such an extent that the recess extends to the insulating layer.
  • the silicon dioxide serves as an etching stop.
  • the recess thus etched can be used for a plurality of qubit elements.
  • step c) the magnet and/or the backgate are inserted into the recess. This is preferably done in such a way that the magnet and/or the backgate adjoin the insulating layer.
  • a backgate and/or a magnet can be used globally for a plurality of qubit elements.
  • Fig. 2 The band structure of a part of the qubit element from Fig. 1.
  • the qubit element 1 shows a qubit element 1. This is described using a coordinate system consisting of a first direction x, a second direction y and a third direction z, pairs of which are perpendicular to one another.
  • the qubit element 1 comprises a quantum well structure 2, within which a quantum well 3 is formed along the first direction x. This can be seen in FIG.
  • the qubit element 1 further comprises an electrode arrangement 4.
  • the electrode arrangement 4 is spaced apart from the quantum well structure 2 by a cover layer 15 and an oxide layer 16.
  • FIG. The electrode arrangement 4 is set up to restrict the movement of charge carriers in the quantum well 3 in and against the second direction y and in and against the third direction z in order to form a quantum dot 5 . Two such quantum dots 5 are drawn in.
  • the quantum dots 5 can be formed by applying electrical voltages to the electrode arrangement 4 .
  • the spins of carriers in the quantum dots 5 can each be used as a qubit.
  • the spins of charge carriers in the two quantum dots 5 shown can be used in particular as qubits that are coupled to one another.
  • the qubit element 1 also includes a base layer 6 formed from strained silicon, which adjoins the quantum well structure 2 counter to the first direction x. Furthermore, the qubit element 1 comprises an insulation layer 7 made of silicon dioxide, which is in contact with the base layer 6 on a side of the base layer 6 opposite the quantum well structure 2 .
  • the quantum well structure 2 has three successive layers 8,9,10 in the first direction x, of which a second layer 9 is formed of strained silicon, and of which a first layer 8 and a third layer 10 are each made of silicon-germanium or germanium silicon are formed.
  • the qubit element 1 also includes a magnet 12 and a backgate 14, which are arranged at a distance from the quantum well structure 2 counter to the first direction x.
  • the backgate 14 can be electrically isolated from the magnet 12 (by insulation between the magnet 12 and the backgate 14, not shown) or can be electrically connected to the magnet 12 . In the latter case, the backgate 14 can be considered to be partially magnetized.
  • the magnet 12 forms the magnetized part of the backgate 14.
  • the qubit element 1 also includes a wafer 11 with a recess 13. The magnet 12 and the backgate 14 are arranged within the recess 13. FIG.
  • the qubit element 1 can be produced by first providing the wafer 11 which has the insulation layer 7 on one surface and a base layer 6 made of strained silicon adjoining the insulation layer 7 .
  • the quantum well structure 2 adjoining the base layer 6 can then be produced.
  • the wafer 11 can be etched locally on a side of the wafer 11 opposite the insulation layer 7 (that is to say at the bottom in FIG. 1) in such a way that the recess 13 is formed in the wafer 11 .
  • the insulation layer 7 serves as an etching stop.
  • the magnet 12 and the backgate 14 can then be arranged inside the recess 13 .
  • FIG. 2 shows the band structure of part of the qubit element 1 from FIG. 1.
  • the quantum well 3 can be seen on the conduction band E c and valence band E v shown.
  • insulation layer 8 first layer of quantum well structure

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Evolutionary Computation (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Artificial Intelligence (AREA)
  • Recrystallisation Techniques (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

L'invention concerne un élément de bit quantique (1) comprenant : une structure à puits quantiques (2), à l'intérieur de laquelle un puits quantique (3) est formé le long d'une première direction (x) ; un ensemble électrode (4) qui est conçu pour réduire le mouvement d'un porteur de charge dans le puits quantique (3) dans et contre une deuxième direction (y) et dans et contre une troisième direction (z), afin de former un point quantique (5), la première direction (x), la deuxième direction (y) et la troisième direction (z)étant chacune perpendiculaires les unes aux autres par paires ; et une couche de base (6), formée à partir de silicium contraint, qui est adjacente à la structure à puits quantiques (2) contre la première direction (x).
EP21733936.5A 2021-06-14 2021-06-14 Élément de bit quantique Pending EP4356417A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2021/065943 WO2022262934A1 (fr) 2021-06-14 2021-06-14 Élément de bit quantique

Publications (1)

Publication Number Publication Date
EP4356417A1 true EP4356417A1 (fr) 2024-04-24

Family

ID=76553756

Family Applications (1)

Application Number Title Priority Date Filing Date
EP21733936.5A Pending EP4356417A1 (fr) 2021-06-14 2021-06-14 Élément de bit quantique

Country Status (4)

Country Link
US (1) US20240297241A1 (fr)
EP (1) EP4356417A1 (fr)
CN (1) CN117480592A (fr)
WO (1) WO2022262934A1 (fr)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19802977A1 (de) 1998-01-27 1999-07-29 Forschungszentrum Juelich Gmbh Verfahren zur Herstellung einer einkristallinen Schicht auf einem nicht gitterangepaßten Substrat, sowie eine oder mehrere solcher Schichten enthaltendes Bauelement
CA2438871C (fr) * 2001-03-09 2011-01-04 Wisconsin Alumni Research Foundation Dispositifs a points quantiques a l'etat solide et calcul quantique utilisant des portes logiques nanostructurees
US8816325B2 (en) * 2011-10-07 2014-08-26 The Regents Of The University Of California Scalable quantum computer architecture with coupled donor-quantum dot qubits
US9842921B2 (en) * 2013-03-14 2017-12-12 Wisconsin Alumni Research Foundation Direct tunnel barrier control gates in a two-dimensional electronic system
WO2018057013A1 (fr) * 2016-09-24 2018-03-29 Intel Corporation Structures d'empilement de puits quantique pour dispositifs à points quantiques
US11327344B2 (en) * 2018-06-20 2022-05-10 equal1.labs Inc. FinFET quantum structures utilizing quantum particle tunneling through oxide
CN112582256B (zh) * 2020-11-23 2024-08-06 中国科学院微电子研究所 一种用于半导体量子计算的应变纯化硅衬底及其形成方法

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US20240297241A1 (en) 2024-09-05
CN117480592A (zh) 2024-01-30
WO2022262934A1 (fr) 2022-12-22

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