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EP4231335A1 - A heteroepitaxial wafer for the deposition of gallium nitride - Google Patents

A heteroepitaxial wafer for the deposition of gallium nitride Download PDF

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Publication number
EP4231335A1
EP4231335A1 EP22156958.5A EP22156958A EP4231335A1 EP 4231335 A1 EP4231335 A1 EP 4231335A1 EP 22156958 A EP22156958 A EP 22156958A EP 4231335 A1 EP4231335 A1 EP 4231335A1
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Prior art keywords
heteroepitaxial wafer
aluminum
wafer according
hydrogen
substrate
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EP22156958.5A
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German (de)
French (fr)
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EP4231335C0 (en
EP4231335B1 (en
Inventor
Brian Murphy
Sarad Bahadur Thapa
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Siltronic AG
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Siltronic AG
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Priority to EP22156958.5A priority Critical patent/EP4231335B1/en
Application filed by Siltronic AG filed Critical Siltronic AG
Priority to JP2024547705A priority patent/JP7735584B2/en
Priority to US18/838,284 priority patent/US20250154682A1/en
Priority to TW112104410A priority patent/TWI851010B/en
Priority to CN202380021991.9A priority patent/CN118715593A/en
Priority to PCT/EP2023/053061 priority patent/WO2023156265A1/en
Priority to KR1020247026439A priority patent/KR20240123435A/en
Publication of EP4231335A1 publication Critical patent/EP4231335A1/en
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Publication of EP4231335C0 publication Critical patent/EP4231335C0/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C30B25/183—Epitaxial-layer growth characterised by the substrate being provided with a buffer layer, e.g. a lattice matching layer
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/36—Carbides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/02447—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3223—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering using cavities formed by hydrogen or noble gas ion implantation

Definitions

  • Gallium nitride offers some fundamental advantages over silicon.
  • the higher critical electrical breakdown field makes it very attractive for power semiconductor devices with outstanding specific dynamic on-state resistance and smaller capacitances compared to silicon MOSFETs. So, GaN HEMTs are great for high speed switching. This is not only because of the resulting power savings and total system cost reduction, it also allows a higher operating frequency, improves the power density as well as the overall system efficiency.
  • the GaN crystal is unstable at growth temperatures and the p-type GaN region is susceptible to decomposition which results in surface damage.
  • the conventional method for avoiding this decomposition is to maintain the flow of NH 3 during reactor cooling.
  • US 649 8111 B1 discloses methods of fabricating passivation-barrier layers to prevent or reduce doping species passivation during the semiconductor growth process, thus eliminating or at least reducing the effects described above.
  • Silicon substrate diameters and thicknesses are standardized, however, with little concern for GOS applications.
  • the improvement is achieved by a combination of layers that can prevent the diffusion through gettering, barriers and passivation/neutralization of the malign effects of hydrogen on dopants.
  • a substrate that can be used of a for heteroepitaxial wafer comprises a silicon substrate which is oriented in ⁇ 1-1-1> direction.
  • the silicon substrate comprises an intermediate or buried gettering layer that is able to getter the diffusing species of hydrogen.
  • the gettering layer preferably comprises a stress field or implanted Helium or Oxygen layer to disturb the crystal and thus gettering the hydrogen species. More preferably the gettering layer comprises a "stable getterer".
  • a “stable getterer” is understood as crystal defects that act as gettering centers for metals that maintain the gettering properties even after high temperature processing steps lasting up to 30 minutes at a temperature up to 1200°C.
  • stable getterer voids can be generated by Helium implantation in the crystal and those voids can be stabilized by co-implantation of Oxygen. It is understood that the implanted Oxygen atoms form silicon oxide on the surface of the the inner walls of the generated voids and thus stabilizes those voids.
  • a test can be carried out in the course of which the wafer to be tested is intentionally contaminated with metal ions on the back side ("Graff test").
  • the impurities are then driven into the crystal lattice by heating the semiconductor wafer. If no effective getter centers are present, they can reach the front side of the semiconductor wafer, where they can be detected by etching and by means of scattered light measurement (haze measurement).
  • This test can be performed, for example, with impurities such as copper (Cu), iron (Fe), nickel (Ni) or palladium (Pd). This test is performed using metals as contaminants; however, the inventors came the conclusion that this test is valid for hydrogen, too.
  • the silicon substrate is covered by a 3C-SiC epitaxial layer.
  • the epitaxial layer is covered by a layer of Aluminum-Nitride.
  • the Aluminum-Nitride layer which is made by MOCVD preferably comprises in the given order a first nitrogen enriched Aluminum-Nitride region, an Aluminum-Nitride region and a second nitrogen enriched Aluminum-Nitride region.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

A heteroepitaxial wafer comprising in the following order (1) a substrate made of Silicon having a thickness a diameter and a resistivity, comprising a buried gettering layer for Hydrogen, (2) a 3C-SiC layer, (3) an Aluminum-Nitride nucleation layer, comprising in the given order a first nitrogen enriched Aluminum-Nitride region, an Aluminum-Nitride region and a second nitrogen enriched Aluminum-Nitride region.

Description

  • The present invention relates to a heteroepitaxial wafer that is optimized for depositing Gallium nitride on it.
    • Description of the Related Art
  • Gallium nitride (GaN) offers some fundamental advantages over silicon. In particular, the higher critical electrical breakdown field makes it very attractive for power semiconductor devices with outstanding specific dynamic on-state resistance and smaller capacitances compared to silicon MOSFETs. So, GaN HEMTs are great for high speed switching. This is not only because of the resulting power savings and total system cost reduction, it also allows a higher operating frequency, improves the power density as well as the overall system efficiency.
  • During growth of GaN p-n junction diodes using Metal- Organic Chemical Vapor Deposition (MOCVD), it is very difficult to grow a p-type material with good structural, optical and at the same time electrical integrity. The p-type region of a GaN junction diode is commonly grown in a MOCVD reactor by adding magnesium (Mg) to achieve the desired conductivity.
  • However, a common problem is the electrical passivation of acceptors like Mg, zinc (Zn), carbon (C) and others by hydrogen atoms. It is believed that Hydrogen atoms diffuse into the GaN material, where they neutralize the Mg acceptors and the holes produced by the Mg.
  • The passivation process leaves the Mg acceptors inactive, resulting in the material becoming insulating or weakly p-type in its as grown state. The passivation of the p-type region results in critical performance problems for the diode. Hydrogen passivation of acceptors and donors has been reported for a wide variety of semiconductors including silicon [see S.J. Pearton et. al., Appl. Phys. A 43, 153 (1987)], gallium arsenide [N.M. Johnson et. al., Phys. Rev. B 33, 1102 (1986); W.C Dautremont-Smith, Mater. Res. Soc. Symp. Proc. 104, 313 (1988)], indium phosphide [G.R. Antell et. al., Appl. Phys. Lett., 53, 758 (1988)], and cadmium telluride [L. Svob et. al., J. Cryst. Growth 86, 815 (1988)].
  • Passivation has been demonstrated both intentionally and unintentionally as a result of the epitaxial growth process. The growth of GaN diodes represents an example where hydrogen passivation plays an important role. It has been shown that passivation of acceptors occurs after growth, during the reactor cooling stage. [G.R. Antell et al., Appl. Phys. Lett. 73, 2953 (1998)]. Hydrogen is common in a MOCVD reactor during growth of the GaN material and subsequent reactor cooling, generally coming from two sources. Hydrogen is commonly used during growth as a carrier gas for the growth source gases.
  • In addition, ammonia (NH3) is used as a source gas for nitrogen (N) during growth of the GaN material and is also used to stabilize the GaN material during reactor cooling. Hydrogen is produced as a by-product of the ammonia decomposition during growth and cooling. During a conventional GaN growth process, there is sufficient hydrogen available in the reactor to cause passivation of the p-type region during cooling.
  • Passivation of a p-type region could theoretically be avoided by removing the hydrogen source from the reactor prior to cool down as disclosed in US 5,891,790 A .
  • However, the GaN crystal is unstable at growth temperatures and the p-type GaN region is susceptible to decomposition which results in surface damage. The conventional method for avoiding this decomposition is to maintain the flow of NH3 during reactor cooling.
  • However, the presence of NH3 during reactor cooling produces hydrogen and leads to passivation. As such, it was thought that the removal of all hydrogen sources was not practical and that passivation during reactor cooling could not be avoided.
  • US 649 8111 B1 discloses methods of fabricating passivation-barrier layers to prevent or reduce doping species passivation during the semiconductor growth process, thus eliminating or at least reducing the effects described above.
  • It is advantageous to heteroepitaxially grow GaN layers onto a silicon substrate, both from a perspective substrate cost and for the potential to more closely integrate GaN-based devices with silicon-based devices.
  • Such GaN-on-silicon (GOS) growths are difficult, to produce because of both lattice mismatch and mismatch of the linear thermal expansion coefficient between the nitride material and silicon substrate.
  • During a high temperature process, such as epitaxial growth, thermal expansion mismatch can cause substrate bowing and warping. Bow is a measure of vertical displacement of the substrate surface and becomes more significant as the substrate diameter increases unless the silicon substrate thickness is increased significantly to provide the greater rigidity needed to resist larger thermal mismatch stress.
  • Silicon substrate diameters and thicknesses are standardized, however, with little concern for GOS applications.
  • As a result, high temperature GaN growth that induces a bow of around 300 µm in substrate having a diameter of 200 mm and a thickness of 725 µm may induce a bow of over 650 µm for a substrate having a diameter of 300 mm and a thickness of 775 µm which is not acceptable for modern device manufacturing processes.
  • It is also known that hydrogen has a rather high diffusion coefficient in silicon at high temperatures. Therefore, the quality of GaN layers deposited on a silicon substrate would be reduced by hydrogen, which can diffuse into the GaN layer via the substrate.
  • In this invention it is the task of the present invention to provide a substrate made of silicon that can be coated with doped GaN without causing described passivation effects of the dopant caused by hydrogen.
  • The solution is given by the features of the claims of this invention.
    • Detailed Description
  • Although having some technical measures in place which are known in the prior art the inventors realized that diffusion of hydrogen in GaN is still a problem on Si wafers. This diffusion results in quality flaws especially concerning the dopant of the GaN. The inventors realized (without scientific proof) that the diffusion of hydrogen through the backside of the wafer (through silicon) is responsible for that.
  • Preferably, the improvement is achieved by a combination of layers that can prevent the diffusion through gettering, barriers and passivation/neutralization of the malign effects of hydrogen on dopants.
  • The granted patent document US 649 811 1 B1 teaches methods of fabricating passivation-barrier layers to prevent or reduce doping species passivation during the semiconductor growth process, thus eliminating the need for in-situ or ex-situ annealing steps. However, the inventors realized that the methods presented in the prior art are not sufficient to entirely solve the problem.
  • Preferably, a substrate that can be used of a for heteroepitaxial wafer comprises a silicon substrate which is oriented in <1-1-1> direction.
  • Preferably, the thickness of the substrate is more than 700 µm and less than 1100 µm.
  • Preferably the diameter of the substrate is more than 125 mm and less than 310 mm.
  • The resistivity of the silicon substrate layer depends on the power device application. In many power device applications conducting substrates are preferred. If electrical conducting substrates are required, the resistivity is preferably less than 10 mOhmcm. If RF HEMT devices semi-insulating or insulating substrates are required, resistivity is preferably higher than 1000 Ohmcm with a low Oi concentration of preferably less than 2 × 1017 At/cm3. So, the resistivity of the silicon substrate preferably is less than 10 mOhmcm or more than 1000 Ohmcm.
  • The inventors further realized that it is most preferred to use a substrate having an interstitial oxygen content of less than 2 × 1017 At/cm3 (ASTM-Norm F121-83) and at the same time the resistivity of the silicon substrate is more than 1000 Ohmcm.
  • Preferably, the silicon substrate comprises an intermediate or buried gettering layer that is able to getter the diffusing species of hydrogen.
  • The gettering layer preferably comprises a stress field or implanted Helium or Oxygen layer to disturb the crystal and thus gettering the hydrogen species. More preferably the gettering layer comprises a "stable getterer". A "stable getterer" is understood as crystal defects that act as gettering centers for metals that maintain the gettering properties even after high temperature processing steps lasting up to 30 minutes at a temperature up to 1200°C.
  • As an example of the above mentioned stable getterer voids can be generated by Helium implantation in the crystal and those voids can be stabilized by co-implantation of Oxygen. It is understood that the implanted Oxygen atoms form silicon oxide on the surface of the the inner walls of the generated voids and thus stabilizes those voids.
  • To determine the efficiency of the gettering, a test can be carried out in the course of which the wafer to be tested is intentionally contaminated with metal ions on the back side ("Graff test"). The impurities are then driven into the crystal lattice by heating the semiconductor wafer. If no effective getter centers are present, they can reach the front side of the semiconductor wafer, where they can be detected by etching and by means of scattered light measurement (haze measurement). This test can be performed, for example, with impurities such as copper (Cu), iron (Fe), nickel (Ni) or palladium (Pd). This test is performed using metals as contaminants; however, the inventors came the conclusion that this test is valid for hydrogen, too.
  • The inventors understood (without scientific proof) that the end of range damage during the implantation process can create some getter centers for the hydrogen species. This measure is effective even at elevated temperatures which are common during the device manufacturing process. More preferably, the gettering layer comprises voids.
  • Preferably, the silicon substrate is covered by a 3C-SiC epitaxial layer. Even more preferably, the epitaxial layer is covered by a layer of Aluminum-Nitride.
  • The Aluminum-Nitride layer which is made by MOCVD preferably comprises in the given order a first nitrogen enriched Aluminum-Nitride region, an Aluminum-Nitride region and a second nitrogen enriched Aluminum-Nitride region.
  • So, a region of the nitrogen enriched Aluminum-Nitride is preferably in contact with the 3C-SiC layer. This region is thought to act as a passivation layer.

Claims (9)

  1. A heteroepitaxial wafer comprising in the following order
    (1) a substrate made of Silicon having a thickness a diameter and a resistivity, comprising a buried gettering layer for Hydrogen,
    (2) a 3C-SiC layer,
    (3) an Aluminum-Nitride nucleation layer, comprising in the given order a first nitrogen enriched Aluminum-Nitride region, an Aluminum-Nitride region and a second nitrogen enriched Aluminum-Nitride region.
  2. A heteroepitaxial wafer according to claim 1, characterized in that the gettering layer comprises voids.
  3. A heteroepitaxial wafer according to claim 1, characterized in that the gettering layer comprises end of range damage.
  4. A heteroepitaxial wafer according to claim 1, characterized in that the crystal orientation of the substrate is <1-1-1>.
  5. A heteroepitaxial wafer according to claim 1, characterized in that the diameter is more than 125 mm and less than 310 mm.
  6. A heteroepitaxial wafer according to claim 1, characterized in that the thickness is more than 700 µm and less than 1100 µm.
  7. A heteroepitaxial wafer according to claim 1, characterized in that the resistivity of the silicon substrate is less than 10 mOhmcm.
  8. A heteroepitaxial wafer according to claim 1, characterized in that the resistivity of the silicon substrate is more than 1000 Ohmcm.
  9. A heteroepitaxial wafer according to claim 8, characterized in that the oxygen content of the silicon substrate is less than 2 × 1017 At/cm3 (ASTM-Norm F121-83).
EP22156958.5A 2022-02-16 2022-02-16 A heteroepitaxial wafer for the deposition of gallium nitride Active EP4231335B1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
EP22156958.5A EP4231335B1 (en) 2022-02-16 2022-02-16 A heteroepitaxial wafer for the deposition of gallium nitride
US18/838,284 US20250154682A1 (en) 2022-02-16 2023-02-08 Heteroepitaxial wafer for the deposition of gallium nitride
TW112104410A TWI851010B (en) 2022-02-16 2023-02-08 Heteroepitaxial wafer
CN202380021991.9A CN118715593A (en) 2022-02-16 2023-02-08 Heteroepitaxial wafers for GaN deposition
JP2024547705A JP7735584B2 (en) 2022-02-16 2023-02-08 Heteroepitaxial wafers for depositing gallium nitride
PCT/EP2023/053061 WO2023156265A1 (en) 2022-02-16 2023-02-08 A heteroepitaxial wafer for the deposition of gallium nitride
KR1020247026439A KR20240123435A (en) 2022-02-16 2023-02-08 Heteroepitaxial wafers for deposition of gallium nitride

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EP22156958.5A EP4231335B1 (en) 2022-02-16 2022-02-16 A heteroepitaxial wafer for the deposition of gallium nitride

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EP4231335A1 true EP4231335A1 (en) 2023-08-23
EP4231335C0 EP4231335C0 (en) 2024-06-19
EP4231335B1 EP4231335B1 (en) 2024-06-19

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CN (1) CN118715593A (en)
TW (1) TWI851010B (en)
WO (1) WO2023156265A1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5891790A (en) 1997-06-17 1999-04-06 The Regents Of The University Of California Method for the growth of P-type gallium nitride and its alloys
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